JPH0646269A - Expansion method and compression method for still picture data or device executing the methods - Google Patents

Abstract

PURPOSE:To provide the expansion method and compression method for still picture data or a device executing the methods in which bits are used optimizingly while keeping compatibility with the JPEG standards. CONSTITUTION:The expansion method for still picture data to invert the conversion converting a sequence for a substantial value into a sequence for a conversion area coefficient is provided with a stage in which each conversion area coefficient is multiplied with a Q coefficient stored in an N-bit storage register in a form of M-bit exponent part identified to be a Q exponent part and an (N-M)-bit mantissa part identified to be a Q mantissa part and a value of a range larger than 2AN is provided to the Q coefficient by a form of Q coefficient=Q mantissa part *2AQ exponent part and with a stage in which a sequence of the multiplied conversion area coefficient is converted into a 2nd sequence approximated to the sequence for a substantial value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND AND SUMMARY OF THE INVENTION The present invention is based on JPEG (Joint Ph
The present invention relates to a still image data decompression method and compression method compatible with the still image decompression / compression standard of otographic Experts Group), and a corresponding apparatus therefor.

When high quality images must be compressed to save memory or transfer requirements, it is common to transfer the image first to another space where the information can be represented smaller. This is usually performed by linear conversion (matrix multiplication) for each block. A typical configuration performs an 8-point transform on an 8-pixel row component, and then performs an 8-point transform on an 8-pixel column component of this row-transformed image. Even if 64 pixel conversion is executed at once for a pixel block of 64 pixels arranged in an 8 × 8 block, it is equivalent.

A good choice for the one-dimensional transform is the independent Chebychev transform, as shown in Eq.

F (u) = c (u) * sum f (i) * cos u (2i + 1) pi / 16 (where sum relates to i = 0 to 7) where:

[Equation 2] Is.

There are several advantages to this conversion.
That is: a) compression is nearly optimal on several criteria b) there is a fast computation algorithm to perform this transformation and its inverse transformation c) the document "Acherloy, M." DCT for reproduction of image sequences , SPIE Vol. 593, Medical Image Processing (1985) ”, based on certain assumptions, including the ability to easily perform deblurring (extension of the initial image) in the transform space. .

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a decompression method and compression method for still image data and a corresponding apparatus therefor. It is a further object of the present invention to provide a still image data compression method that is compatible with the JPEG standard and a corresponding device. Another object of the invention is the optimization of the use of bits in the quantization and compression stages of data compression. Another object of the present invention is the minimization of root mean square error in a data compression scheme that integrates quantization and coefficient compression. A further object of the invention is the range of data compression, as well as the use of a certain amount of bits in the method of optimizing the resolution. A further object of the invention is the resolution of the JPEG standard H.264 for small quantization values. 261 specifications. More specifically, the object of the present invention is to provide a dynamic range of 28 by using a 16-input 1-output multiplexer and a 16-bit multiplier.
It is to provide a method for enabling pre-compression of quantization in bits. Another object of the present invention is to use the speed of generalized chain transformations in a pipelined implementation of processing to the maximum advantage. A further object of the invention is to minimize the number of gates required to perform the conversion. More particularly, it is an object of the present invention to perform the addition of vertical and horizontal transforms with the same hardware, taking advantage of the speed of the adder network portion of the transform. Further objects, advantages and novel features of the invention will be set forth in the detailed description which follows and will be apparent to those skilled in the art upon examination of the detailed description, or from the examples of the invention. Will be found. The objectives and features of the invention may be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

[0006]

[Discussion on theoretical aspects of the present invention] Image compression and reproduction (decompression)
The complete system for can be expressed as: 64 pixel input ↓ A) Discrete Chebychev conversion (or similar row conversion) ↓ B) Discrete Chebychev conversion (or similar column conversion) ↓ Z) (optional) ↓ Difficulty classification ↓ C) Rate scaler multiplication ↓ D ) Multiply by weight of psychological factor ↓ E) Multiply by debra ringing weight ↓ F) Thresholding, quantization, encoding and transfer ↓ G) Reception, decoding, interpolation ↓ H) Inverse rate scaler ↓ I) Inverse Multiply by weight of orientation psychological factor ↓ J) Inverse discrete Chebyshev transform ↓ K) Inverse discrete Chebychev transform ↓ L) Smoothing around pixel block ↓ Reproduced 64 pixels → Adjacent pixel

The above procedure describes the invention and also describes the current state of the art by omitting any of the steps (L, Z). Multiply by debra ring weight (stage E)
Can also be performed in the decoding stage (eg after stage I). Deblurring is performed to compensate for the point spread function of the input device. This must be set for the device or eliminated if the input image is already highlighted. There are other good ways to make an image stand out, but the one shown here is cheaper to calculate,
It is suitable for certain applications, such as color copiers.

It is possible to arrange the calculation of the forward transform (A, B) so that most of the calculation load consists of the final multiplication process. The product of these multipliers, as well as the stages (C,
By pre-calculating that of E), the compression process can proceed. Similarly, it is possible to arrange the inverse transform (J, R) computations such that most of the computation load consists of preliminary multiplication processes. Again, the preliminary calculation of the product effectively eliminates the effort in the calculation (H, I) stage. Further, another transform is replaced with a two-dimensional discrete cosine transform (two-dimensional DCT transform), and further simplification of calculation is obtained. Further, the weight of the psychological factor can be selectively changed to improve the calculation efficiency in the integrated multiplier of the stage (B, D), for example, to be proportional to the square. Small changes in the weight of the psychological factors of the low energy output conversion element have little effect on the image quality or compression ratio. Finally, the steps (L, Z) of FIG.
Attention should be paid to the difficulty level of the image and smoothing around the block. Since these are optional and independent of the subject matter of the invention, only a minimal discussion will be given here.

[Chen algorithm] One-dimensional chain algorithm (reference "Chen, W et al.
"High-speed calculation algorithm for DCT" IEEE Trans.
Commun. COM-25 (1977) ”)

Equation 3] is as _{X = 2 / N A N x} . Where x is a vector of data,
X is the transformed vector and A _N is

## EQU4 ## A _N = c (k) cos ((2j + 1) kπ / 2N); j, k = 0, 1, 2, ..., N-1.

Further, such an A _N has the following determinant

[Equation 5] Can be disassembled with. Where R _{N / 2} is

## EQU6 ## R _{N / 2} = c (2k + 1) cos ((2j + 1) (2k + 1) π / 2N); j, k = 0, 1, 2, ..., N / 2−1.

Note that the determinant Z is the Chien matrix. In this application, the notation is changed to avoid confusion with the determinant P.

Example of 8-point (N = 8) one-dimensional Chen transform: In order to perform 8-point conversion, the Chen algorithm shown in Equation 5 is recursively used twice. In the first iteration, the determinant Z
₈ , R ₄ , and B ₈ are used. The second iteration solves for A ₄ and uses the determinant Z ₄ , R ₂ , A ₂ , B ₄ . These are described in the above formula or in the Chen article "Chen, W et al.," D
High-speed calculation algorithm for CT "IEEE Trans. Commu
n. COM-25 (1977) ”can be easily derived.

[0013]

[Equation 7]

Here, Z ₈ is the number 8, B ₈ is the number 9, R ₄ is the number 10, Z ₄ is the number 11, B ₄ is the number 12, R ₂ is the number 13,
A ₂ is shown in equation (14).

[Equation 8]

[Equation 9]

[Equation 10]

[Equation 11]

[Equation 12]

[Equation 13]

[Equation 14] Here, from Equation 6,

## EQU15 ## Cn = cos (n.pi./16).

... Cheng Woo (variant method) or parameter conversion ... The Chen conversion has been performed so far. Multiply this to achieve computational savings and multiply intensive DCT implementations. However, this was not provided by the applicant. To minimize the multiplication, the determinant is
Or, retake the parameters as shown in Eq. This is what the applicant calls Chen Woo (modified method) and is a creation by the applicant.

[0016]

[Equation 16]

[Equation 17]

[Equation 18]

Here, a, b, c and r are shown in the equation (19).

A = C1 / C7 = sin (7π / 16) / cos (7π / 16) = tan (7π / 16) b = C2 / C6 = tan (6π / 16) c = C3 / C5 = tan ( 5π / 16) r = C4 = tan (4π / 16)

Note that the diagonal determinant RF ₄ contains the standardization factor for the unparameterized determinant RA ₄ . Also note that the diagonal determinant can be made from the constants of R ₂ and A ₂ .

In reproducing the A ₈ matrix, the two determinants are separated. The diagonal determinant is kept separate from the main determinant. The main determinant is multiplied by the B _N term. After proper rearrangement and multiplication by a constant term, the number 3 decreases to the number 20.

[0020]

X = Q (a, b, c) P (a, b, c, r) x where Q (a, b, c) is the number 21 and P (a, b, c,
r) is shown in Equation 22.

[Equation 21]

[Equation 22]

Generalized transform ... The generalized 8-bit DCT transform has four parameters a, b, and
Calculated from c and r, it can be expressed as

T (a, b, c, r) = P (a, b, c, r) XQ (a, b, c) where P () and Q () are as described above.

The image transformation is such that two such transformations T, T _v and T _h , respectively, are required to transform the image vertically and horizontally, respectively. A complete two-dimensional transformation is expressed as in Equation 24.

[F] = [T _v ] ^ t [f] [T _h ] where f is a block of the input image, F is an output transform coefficient,
Also, the power multiplier “t” represents matrix transformation. here,
All matrices are 8 rows and 8 columns.

Since a diagonal matrix (eg, Q) is its own transformation, for every matrix,

[Number 25] [A] ^ t [B] ^ t = ([B] [A]) ^ t [T v] = [P v] [Q v] [T h] = [P h] [Q h ] Is represented. So, if you rewrite equation 24,

[Number 26] the _{[F] = [Q v]} [P v] ^ t [f] [P h] [Q h].

This can also be expressed as in Equation 27.

F (i, j) = q (i, j) * g (i, j) where:

[The number 28 is a _{[g] = [P v]} ^ t [f] [P h] q (i, j) = Q v (i, i) * Q h (j, j).

In transforming an image block, the [C] -Cho transform is used to solve for [g] and then the coefficient q (i, j)
Will be multiplied by. Now

If P _v = P (a, b, c, r _v ) and P _h = P (a, b, c, r _h ), then the reverse direction of the above-mentioned conversion is expressed as To be done.

[F] = [P _v ′] [Q _v ] [F] [Q _h ] [P _h ′] ̂t Here, P _v ′ and P _h ′ are shown in Expression 31.

P _v ′ = P (a, b, c, ½r _v ) P _h ′ = P (a, b, c, ½r _h ), and the solution method is via the Cheng-U transformation.

... Chen's algorithm ... Several methods have been devised to speed up the one-dimensional or two-dimensional Chebyshev transform and vice versa. Well-known algorithm (Chen) ... Reference "Coolie and Tukey,
JW. "(Fast) Fourier Series Algorithm" Math
Comput, Vol. 19, No. 90, pp. 296-301, 19
See "Chang, W et al.," High-speed calculation algorithm for DCT ", IEEE Trans. Commun. COM-25 (1977)" in 1965 .... Any eight sets are multiplied by the above matrix T, and multiplication is performed. It uses only 16 times, 13 times addition, and 13 times subtraction.
It does not depend on any special attributes of b, c, r.

... Chen-Woo Algorithm (Modified Method) As described above, by taking a factor of [T] = [P] [Q], the Chen algorithm is divided into two stages, and [Q] The multiplication by uses eight multiplications, [P]
The multiplication by uses 8 multiplications and the remaining numerical calculations. This is the result of the choice on [Q],
Some elements of [P] become "1" or "-1", and the calculation disappears.

As pointed out above, similar simplifications apply to inverse transforms, two-dimensional transforms and inverse two-dimensional transforms.
In 8 × 8 blocks, 128 multiplications are used in either forward or backward two-dimensional transformation (except multiplication by [q]). Looking at the internal data flow of Chen's algorithm, these multiplications are embedded in a structure of eight add / subtract stages and four multiply stages.

The Chen algorithm uses the parameter a,
It is important to emphasize that it works regardless of b, c, or r. However, the 8-point DCT used in the prior art
Has the following "true cosine transform" parameters. a = tan (7 * pi / 16) b = tan (6 * pi / 16) c = tan (5 * pi / 16) r = sqrt (1/2) = 0.70710678 ... Then, the matrix T should be orthogonal. Select necessary and sufficient r.

... Selection of parameter value ... The chain transformation operates regardless of the values selected for the parameters a, b, c and r. This is because the transforms generated by QP are orthogonal. It is quite possible to have a transform that can perform the desired decorrelation of the image data that needs to be compressed using any number. Note that this transform is neither a discrete cosine transform nor a DCT approximation. This is its own transformation.

However, for efficient decorrelation of the input image, and for conversion to relatively significant spatial frequency coefficients, DCT is generally considered highly desirable (see "Li, BC "High-speed cosine transform" IEEE AS
SP, Vol. 33 (1985) ”). Therefore, in order to realize the advantages of the DCT, the parameters should be set close to those of the DCT shown in the equation (19). Computation efficiency: Addition is cheaper than multiplication (hardware savings are silicon resources, software savings is cycles), so the parameters are chosen to be computationally efficient.

Other algorithms ... Other calculation methods have also been devised for the discrete Chebyshev transform. For example, Lee's algorithm uses 8-point 1-dimensional and 64-point 2-dimensional transformations 12 times and 144 times, respectively.
It is executed by multiplying the number of times (reference “U, HR. And Paolini, FJ.“ Two-dimensional fast cosine transform ”IEEE image processing conference, Volume 1 (1989)”) or reference “Lee, BC. "High-speed cosine conversion" IEEE ASS
P. 33 (1985) ").

However, these "faster" algorithms have some drawbacks when compared to the Chen algorithm: a) The simplification of T = P × Q (and similar factorization for the inverse transform) fails. Separation of the diagonal matrix Q is essential for subsequent simplifications. b) These algorithms have arbitrary parameters a,
It does not work for b, c and r. Instead, they rely on trigonometric attributes that are particularly valid for true cosine parameters. c) These algorithms are more structurally complex. This can be an engineering obstacle and increases the likelihood of numerical instability.

Detailed Description of the Invention A] Referring again to the system in the theoretical discussion above, steps (C, D, E) are incorporated into the forward transform post-multiplier derived from "Q". I understand that it can be done. Similarly,
Stage (H, I) can be incorporated into the inverse transform premultiplier. This is a rate scaler operation, a psychological factor weighting operation (generally known as a quantum value), and a debra ring weighting operation are all point multiplication operations.
When b, c, d, and e are outputs of stages B, C, D, and E, respectively,

C (i, j) = b (i, j) * q (i, j) d (i, j) = c (i, j) * r (i, j) = b (i, j) ) * Q (i, j) * r (i, j) e (i, j) = d (i, j) * u (i, j) = b (i, j) * q (i, j) * r (i, j) * u (i, j) or

[Expression 33] e (i, j) = b (i, j) * all (i, j) Where all (i, j) is

(34) all (i, j) = q (i, j) * r (i, j) * u (i, j). Also, q (i, j) is the rate scaler and r
(i, j) is a quantization weight selected as a psychological factor (or selected by the user), and u (i, j) is a debraling weight. Similarly, stages H and I can be combined.

This clearly means that the rate scaler, adaptive weighting and debraling functions are provided without any extra computational overhead. As mentioned above, this method is not applicable to "fast" algorithms such as Lee's algorithm.

B] The Chen algorithm operates with the parameters a, b, c and r, so that quality and compression comparable to DCT can be obtained, but a value that allows fast multiplication is selected. .

The following parameters are reasonably close to the DCT parameters, but the calculation efficiency is significantly high. The a = 5.0 b = 2.5 c = 1.5 r = 0.75 multiplication is now replaced by a much simpler arithmetic calculation. For example, 5 times becomes copy; shift-left-2; add. 1.5 times becomes copy; shift-right-1; add. Otherwise, the inverse numerator of a rational multiplier can be factored into a bond multiplier [q].
Therefore, 2.5 times is 5 in terms of affecting and not affecting.
It can be double and double.

According to the latter concept, the handling of the parameter r = 0.75 in the original Chen algorithm requires 96 multiplications of 4 and 4 multiplications of 3. The improvement of U Paolini in the two-dimensional implementation eliminates the entire multiplication stage, which is 36 multiplications of 16, 24 multiplications of 12, and 4 multiplications of 9 (36 multiplications of 9 in the inverse transform,
6 times 24 times, 4 times 4 times used).

Regarding the cost of calculation speed, a parameter value close to the cosine transform may be selected. b = 12/5, and /
Alternatively (and / or), a substitution of r = 17/24 is possible. Another interesting substitution is rRow = 0.7008333 (17/24) rCol = 0.7 (7/10).

Here, a slightly different transformation (another parameter r) is used for rows and columns. This is done to simplify the multipliers obtained by the U-Paolini method. With this method, 15 multiplications 36 times, 85/8 multiplications 12 times, 21/2 multiplications 12 times, 119/16 multiplications 4
Times are obtained (119/16 multiplications 36 in reverse transformation)
Times, 85/16 multiplications 12 times, 21/4 multiplications 12 times,
Use 4 multiplications of 15/4).

In the method described above, all the multipliers are fast and cheap except for the combination multiplier [q] in the compressor (compressor) and the combination multiplier [q] in the expander (decompressor). Each of these requires one multiplication per conversion element. The latter is simplified so that most of the transform coefficients are "0" and the coefficients other than "0" are integers extremely close to "0" that can be specially handled.

C] In the compressor, an additional technique is used to reduce the computational cost of the combined multiplier [q]. rate·
The scaler is actually an arbitrary value, and is adjusted between two points to make the calculation of the [q] matrix element a simple value, for example, square. These 64 adjustments need to be performed only once (after specifying the rate scaler and deblurring filter).

For example, if the element C of the combination multiplier and the corresponding expansion multiplier element D are C = 0.002773 D = 0.009367, the approximation C≈3 / 1024 = 0.002930 is found, and in order to simplify the multiplication, used. This results in C '= 3/1024 and D' = D * C / C'≈0.008866.

[0044]

[Detailed Description of Primary Processing] ... Precautions ... a) In the quantization transform space, a non-zero stage of the coefficient quantization “AC” that should have a constant width (w) is taken, and the width (w) is also taken.
It is convenient and effective to take 0 steps, which should be * q). Furthermore, q = 2 is arithmetically convenient and nearly optimal for quality over a wide range of compression factors. Although “= 2” (“double width zero”) is used in the description, the present invention can take any possible q. b) The following algorithm is designed for two's complement binary integer arithmetic with limited precision except for the intermediate determination of steps 2, 4 and 8 which is performed only once by high precision computation. is there. Furthermore, with the further exclusion of step 9.1, the integer multipliers described in this paper are optimized for cost and speed. For example, considering the following multiplication Nrr * Nrc = Drr '* Drc' = 1.75 * 4.25 = 7.4375, by selecting the sameness 7.4375 = (8-1) * (1 + 1/16), the multiplication by shift and addition can be performed. It is done efficiently. c) The debraling multiplier, shown here in step 8, should normally be done in step 4. In many applications, the decompressor "does not know" how or how to deblurr an image. Note that the best value for Thr () depends on the input device and debraling method. The recommended method is to calculate for the value m (i, j) (see step 8) the compression time (see step 4) and transfer or save it as part of the compressed image. d) There are some explicit ways of parallelizing, time-sequencing, or fragmenting subsequent computations. The preferred method for a given hardware configuration is self-evident.

Pseudo Code Embodiment ... This part of the application is basically a preferred embodiment of the invention described in the text and pseudo code. Multiple chapters including parametrization, calculation of all (i, j) similar to equation 34 above, execution of forward GCT body, calculation of all backwards (i, j), execution of inverse GCT body Have.

Step 1 Parameters a, b, c and r are as described above. Note that there are r values for both rows and columns. The two-dimensional GCT is a separable transform and can be performed in two steps, but there are no constraints that require it to be symmetric. Therefore, the compression (scaling) factor can be asymmetric as shown.

The balance of numerator N and denominator D indicates possible combinations of numerator and denominator that can be equal to the above values. Designers of GCT implementations have a clue about the actual values to use in an adder circuit array. The choice of values will be corrected in the final multiplication stage.

That is,

Tan 7 * pi / 16 ≈a = Na / Da tan 6 * pi / 16 ≈b = Nb / Db tan 5 * pi / 16 ≈c = Nc / Dc sqrt (0.5) ≈rRow = Nrr / Drr sqrt (0.5) .apprxeq.rCol = Nrc / Drc0.5 / rRow = rRow '= Nrr' / Drr'0.5 / rCol = rCol '= Nrc' / Drc 'are selected as parameters of the generalized Chien transform as described above. The “numerator” N and the “denominator” D do not have to be integers, but are selected for convenience of calculation. Some useful combinations are: Na = 5, Nb = 3, Nc = 1.5, Nrr = 1.75, Nrc = 4.2
5, Nrr ′ = 1.25, Nrc ′ = 3, Da = 1, Db = 1.25,
Dc = 1, Drr = 2.5, Drc = 6, Drr ′ = 1.75, Drc ′
= 4.25.

Again, the present invention includes all rational approximations to the tangent. This calculates the required standardized compression (standardized scaler).

Step 2 In addition,

[Equation 36] U (0) = U (4) = sqrt (0.5) U (1) = U (7) = 1 / sqrt (Na * Na + Da * Da) U (2) = U (6) = 1 / It can also be written as sqrt (Nb * Nb + Db * Db) U (3) = U (5) = 1 / sqrt (Nc * Nc + Dc * Dc).

Step 3 Let i be a vertical position (in image space) or a series of vertical changes (in transform space) {0, 1, 2, 3, 3.
4, 5, 6, 7}. Similarly, j
, {0, 1, 2, 3, 4, 5, representing a series of lateral positions (in the image space) or horizontal directions (in the transform space).
6, 7} index. Debl (i, j) represents the debraing coefficient, and Deb if deblurring is not performed.
Set l () = 1. Thr (i, j) represents the weighting of the reverse psychological factor recommended by CCITT, for example. v (i, j)
Represents some luminance value in the image (spread) space. L (i, j) represents the transformed luminance value in the transformation (compression) space. Let S be any small integer that represents the arithmetic correctness used in the reproduction.

The psychological factor weight 1 / Thr (i, j) is re-optimized for each parameter set of the generalized Chen transform. However, the parameters given in step 1 are sufficiently close to the optimal CCITT parameters for the same determinant Thr ().

Step 4 Here, g (i, j) is equal to all (i, j). Conversion position
(i, j) Iterating over 64 places, solving k (i, j) and s (i, j) so as to satisfy Eq.

[Formula 37] q (i, j) <{M * U (i) * U (j) * 2 ^ s (i, j)} / {k (i, j) * Zr (i) * Zc (j ) * Thr (i, j)}. Assuming that the right side is as close as possible to g (i, j) and s (i, j) is an integer,

Q (i, j) = 1.0, k (i, j) in {1,3,5,7,9} where i + j <4 q (i, j) = 0.9, k (i, j ) in {1,3,5} where i +
j <4 q (i, j) = 0.7, k (i, j) = 1, where i +
j <4 Zr (i) = 1 (when i = 0,1,2 or 3) Zr (i) = Drr, (when i = 4,5,6 or 7) Zc (j) = 1 (j = 0, 1, 2 or 3) Zc (j) = Drc (when j = 4, 5, 6 or 7) Zr '(i) = 1 (when i = 0, 1, 2 or 3) Zr '(i) = Drr' (when i = 4,5,6 or 7) Zr '(j) = 1 (when j = 0,1,2 or 3) Zr' (j) = Drr '( j = 4,5,6 or 7). The factor g (i, j) is intended to make the quantization bias independent of the size chosen.

Step 5 ... Execution of Forward GCT (Forward GCT) ... Step 5 is execution of pseudo-code for forward conversion. The following steps perform a two-dimensional transformation on the fragmented form. The following execution is repeated for the entire image for each 8 × 8 block of the luminance value v (,).

Step 5.1 Prepare the values.

[Equation 39] M (i, 0) = V (i, 0) + V (i, 7) M (i, 1) = V (i, 1) + V (i, 6) M (i, 2) = V (i, 2) + V (i, 5) M (i, 3) = V (i, 3) + V (i, 4) M (i, 4) = V (i, 3) − V ( i, 4) M5 (i) = V (i, 2) -V (i, 5) M6 (i) = V (i, 1) -V (i, 6); i = 0,1,2, ... , For 7

Step 5.2 Prepare the values.

H (0, j) = M (0, j) + M (7, j) H (1, j) = M (1, j) + M (6, j) H (2, j) = M (2, j) + M (5, j) H (3, j) = M (3, j) + M (4, j) H (4, j) = M (4, j) − M ( 4, j) H5 (j) = M (2, j) -M (5, j) H6 (j) = M (1, j) -M (6, j) H (5, j) = H6 (j ) + H5 (j) H (6, j) = H6 (j) = H5 (j) H (7, j) = M (0, j) -M (7, j); j = 0,1,2 ,,, for 7

Step 5.3 Multiply each H (i, j).

When i = 0, 1, 2 or 3, Nrc (when j = 5 or 6) Drc (when j = 4 or 7) 1 (no action) (j = 0, 1, 2 or 3) i = 4 or 7; Drr Nrr (j = 5 or 6) Drr Drc (j = 4 or 7) Drr (j = 0, 1, 2 or 3) i = When 5 or 6; Nrr Nrr (when j = 5 or 6) Nrr Drc (when j = 4 or 7) Nrr (when j = 0, 1, 2 or 3)

Step 5.4 Prepare the values.

[Equation 42] E (0, j) = H (0, j) + H (3, j) E (1, j) = H (7, j) + H (5, j) E (2, j) = H (0, j) -H (3, j) E (3, j) = H (7, j) -H (5, j) E (4, j) = H (I, j) + H ( 2, j) E (5, j) = H (6, j) -H (4, j) E (6, j) = H (I, j) -H (2, j) E (7, j) = H (6, j) + H (4, j) F (0, j) = E (4, j) + E (0, j) F (4, j) = E (0, j) − E ( 4, j) F (2, j) = Db * E (6, j) + Nb * E (2, j) F (6, j) = Db * E (2, j) + Nb * E (6, j) F (1, j) = Da * E (7, j) + Na * E (1, j) F (7, j) = Da * E (1, j) + Na * E (7, j) F (3, j) = Dc * E (5, j) + Nc * E (3, j) F (5, j) = Dc * E (3, j) + Nc * E (5, j); j = 0, 1, 2, ...

Step 5.5 Prepare the values.

Z (i, 0) = F (i, 0) + F (i, e) Z (i, 2) = F (i, 0) −F (i, 3) Z (i, 4) = F (i, 1) + F (i, 2) Z (i, 6) = F (i, 1) + F (i, 2) Z (i, 1) = F (i, 7) + F ( i, 5) Z (i, 3) = F (i, 7) -F (i, 5) Z (i, 5) = F (i, 6) -F (i, 4) Z (i, 7) = F (i, 6) + F (i, 4) G (i, 0) = Z (i, 4) + Z (i, 0) G (i, 4) = Z (i, 0) -Z ( i, 4) G (i, 2) = Db * Z (i, 6) + Nb * Z (i, 2) G (i, 6) = Db * Z (i, 2) -Nb * Z (i, 6) G (i, 1) = Da * Z (i, 7) + Na * Z (i, 1) G (i, 7) = Da * Z (i, 1) -Na * Z (i, 7) G (i, 3) = Dc * Z (i, 5) + Nc * Z (i, 3) G (i, 5) = Dc * Z (i, 3) -Nc * Z (i, 5); i = 0, 1, 2, ...

Besides this, it is possible to divide the conversion into two steps by one-dimensional conversion. The following is an example of a one-dimensional conversion path. These steps are shown in FIGS. 8 and 9.

[0061]

[Equation 44] Note that all the multipliers in these equations shown in equation 44 are performed by shift and add operations. To relate this to the GCT matrix shape, vector point Y6 is demonstrated as in the example.

[0062]

[Equation 45] Y6 = C1-C4 = (1.25 B1)-(3 B4) = 1.25 (A1-A2) -3 (A4-A3) = 1.25 ((X0 + X7)-(X3 + X4))-3 ((X1 + X6) -(X2 + X5)) = 1.25 X0-3 X1 + 3 X2-1.25 X3 + 1.25 X4 + 3 X5-3 X6 + 1.25 X7 Y6 / 1.25 = X0-2.4 X1 + 2.4 X2-X3 + X4 + 2.4 X5-2.4 X6 + X7 = | 1 -b b -11b-b1 | x Here, b = 2.4. This is the sixth row of the determinant P of the equation. The division by 1.25 is a scaling factor collected in the rate scaler matrix. 8x
The row data of the 8-pixel block passes through this adder circuit array. The obtained one-dimensional frequency component is transposed and passes through the same array again.

Step 6 After Step 5.5, in the lower block of each image, and for each of the 64 positions (i, j), Step 4
From k (i, j) and s (i, j), a value as shown in Expression 46 is prepared.

L (i, j) = G (i, j) * k (i, j) * 2 ^ (-s (i, j)) However, if this is negative (or i = j = 0) ), And add 1 to this. The result is the conversion coefficient L (i, j).

Comment on step 6 ... The calculation here is simple, because -k (i, j) is always 1,
3, 5, 7 or 9, and because it is always 1, -2 ^
This is because the multiplication of (-s (i, j)) is simply a right shift (or perhaps a left shift if M is chosen to be very large). A mathematical right shift always causes rounding. 0
Rounding towards is actually desirable, and is thus the expression "if (negative) add 1." 1 when i = j = 0
The addition of p depends on v (i, j) ≧ 0, which is only a device to simplify the declaration of step 9.1 below.

Step 7 Encoding, storing and / or transmitting the values L (i, j) Finally these values are captured and the image is reproduced in the next step.

Step 8 This is the inverted version of all (i, j). Iterate for 64 conversion positions (i, j), and m (i, j) is

M (i, j) = {U (i) ² * U (j) ² * Zr (i) * Zc (j) * Debl (i, j)} / (4-Ss (i, j )) Solve as the integer closest to Zr '(i) * Zc' (j) * k (i, j) * 2. Where s (i, j) and k
(i, j) has already been solved in step 4 and the expression "Z" has been defined in step 4. Also, let A (i, j) be

A (0,0) = {(2 ^ (S-2)) / Drc '* Drr'}-0.5 * m (0,0) A (i, j) = m (i, j) * (25-i-j) / 64; for i = 0 or j = 0, choose as the closest integer to.

Comment on step 8 The value m (i, j) may be calculated in advance in step 4 and transmitted together with the compressed image. This is a constant term and m (i,
It is not necessary for A (i, j) which depends only on j). rate·
In applications where the scaler and debraling weights are fixed, m (i, j) and A (i, j) are considered constant terms. The coefficient 2 ^ S is an arithmetic right shift in steps 9.2 and 10 to reflect the remainder bits of accuracy that are to be subsequently removed. Adjustment to A (0,0) corrects the rounding bias and allows the use of the following outputs without rounding correction. As mentioned here, A
(0,0) depends on the addition of 1 to L (0,0) in step 6. The interpolation "(25-i-j) / 64" is a heuristic, but it is an optimum approximation value in the root mean square error detection. Furthermore, it is a fragmented version of 20.

Step 9 Iterate over the transformed image and for each 8 × 8 block of transformed luminance values L (,) derived in step 5 above, do the following:

Step 9.1 Prepare the values.

When L (i, j)>0; E (i, j) = L (i, j) * m (i, j) + A (i, j) L (i, j) <0 When; E (i, j) = L (i, j) * m (i, j) -A (i, j) L (i, j) = 0; E (i, j) = 0; For each (i, j), it means that A (0,0) for i = 0,1,2, ..., 7, j = 0,1,2, ..., 7 is always added. The present invention also
The check "L (0,0)>0" is not performed, and steps 6 and 8 encompass the (optionally) non-simplified part as described above. In practice, a small multiplication, for example −11 <L (i,
j) Recognize <11 as a special case that should save the calculation cost of multiplication.

Step 9.2 If it is convenient to reduce the cost of the semiconductor device, the numerical value E (i, j) is right-shifted by an arbitrary number at the position S1. Note that these shifts are "free" in certain implementations of the method. In the realization method that shift is not free, E
When (i, j) becomes 0, it may be selected so as to be ignored (or, by setting S1 = 0, it is also possible to select so as to eliminate all shifts. is there.)

Step 9.3 Once again, prepare the values in the two-dimensional shape.

F (0, j) = E (4, j) + E (0, j) F (4, j) = E (0, j) -E (4, j) F (2, j) = Db * E (6, j) + Nb * E (2, j) F (6, j) = Db * E (2, j) -Nb * E (6, j) F (1, j) = Da * E (7, j) + Na * E (1, j) F (7, j) = Da * E (1, j) -Na * E (7, j) F (3, j) = Dc * E (5, j) + Nc * E (3, j) F (5, j) = Dc * E (3, j) -Nc * E (5, j) H (0, j) = F (0, j ) + F (2, j) H (1, j) = F (4, j) + F (6, j) H (2, j) = F (4, j) -F (6, j) H ( 3, j) = F (0, j) -F (2, j) H (4, j) = F (7, j) -F (5, j) H5 (j) = F (7, j) + F (5, j) H6 (j) = F (1, j) -F (3, j) H (5, j) = H6 (j) + H5 (j) H (7, j) = F (1 , j) + F (3, j); for j = 0,1,2, ..., 7

Step 9.4 Prepare the values.

G (i, 0) = H (i, 4) + H (i, 0) G (i, 4) = H (i, 0) −H (i, 4) G (i, 2) = Db * H (i, 6) + Nb * H (i, 2) G (i, 6) = Db * H (i, 2) -Nb * H (i, 6) G (i, 1) = Da * H (i, 7) + Na * H (i, 1) G (i, 7) = Da * H (i, 1) -Na * H (i, 7) G (i, 3) = Dc * H (i, 5) + Nc * H (i, 3) G (i, 5) = Dc * H (i, 3) -Nc * H (i, 5) M (i, 0) = G (i, 0 ) + G (i, 2) M (i, 1) = G (i, 4) + G (i, 6) M (i, 2) = G (i, 4) -G (i, 6) M ( i, 3) = G (i, 0) -G (i, 2) M (i, 4) = G (i, 7) -G (i, 5) M5 (i) = G (i, 7) + G (i, 5) M6 (i) = G (i, 4) -G (i, 3) M (i, 5) = M6 (i) -M5 (i) M (i, 6) = M6 (i ) + M5 (i) M (i, 7) = G (i, 1) + G (i, 3); for i = 0, 1, 2, ..., 7

Step 9.5 Calculate each M (i, j) by Equation 52
And multiply according to.

When i = 0, 2 or 3, Nrc ′ j = 5 or 6 Drc ′ j = 4 or 7 1 (no action) j = 0, 1, 2 or 3 i = When 4 or 7; When Drr'Nrc 'j = 5 or 6 When Drr'Drc' j = 4 or 7 When Drr 'j = 0, 1, 2 or 3 When i = 5 or 6; Nrr When'Nrc 'j = 5 or 6 Nrr'Drc' j = 4 or 7 Nrr 'j = 0, 1, 2 or 3

Step 9.6 Prepare the values.

[Equation 53] Z (i, 0) = M (i, 0) + M (i, 7) Z (i, 1) = M (i, 1) + M (i, 6) Z (i, 2) = M (i, 2) + M (i, 5) Z (i, 3) = M (i, 3) + M (i, 4) Z (i, 4) = M (i, 3) − M ( i, 4) Z (i, 5) = M (i, 2) -M (i, 5) Z (i, 6) = M (i, 1) -M (i, 6) Z (i, 7) = M (i, 0) -M (i, 7); For i = 0, 1, 2, ..., 7

Step 9.7 Prepare the value.

[Equation 54] Y (0, j) = Z (0, j) + Z (7, j) Y (1, j) = Z (1, j) + Z (6, j) Y (2, j) = Z (2, j) + Z (5, j) Y (3, j) = Z (3, j) + Z (4, j) Y (4, j) = Z (3, j) − Z ( 4, j) Y (5, j) = Z (2, j) -Z (5, j) Y (6, j) = Z (1, j) -Z (6, j) Y (7, j) = Z (0, j) -Z (7, j); For j = 0, 1, 2, ..., 7

Step 10 After step 9.7, a value is prepared for each of the 64 positions (i, j) in the lower block of each image.

V (i, j) = Y (i, j) * 2 ^ (S1-S) where S and S1 are arbitrary integers defined in steps 7 and 9.2 above. Also, the multiplication is actually a right shift.

Step 11 Depending on the system implemented, it may now be necessary to perform range verification. For example,
If the allowable range of luminance is 0 ≦ v (i, j) ≦ 255, the values of V (i, j) of 0 or less or 255 or more are 0 and 25, respectively.
Will be replaced by 5. The value v (i, j) becomes the image luminance value reproduced by this.

[0078]

Consideration of Secondary Processing It is customary to take further measures and supplement the primary processing to improve the compression or quality of the image. After step 10, the accuracy of the image is determined by all pixel pairs V (8I + 7, j), V (8I + 8, j), and all pixel pairs V (k, 8J + 7), Iterating through V (i, 8J + 8) (ie, adjacent pixels that had been split into another image block), and also, for example, M being the rate scaler used in step 4, optimizes the fractional representation. (V2-v1) / max (2,11sqrt (M)) which is also a suitable approximation to
Can be improved by increasing and decreasing these values v1 and v2, respectively.

Before performing step 6, the objective difficulty of the local image area is set to the prefix "0", "10" or "1".
It is preferable to classify the output of "1" into one of three formats, single precision, double precision and quadruple precision, each of which is attached to each output. The calculation in step 6 is replaced by the following equation.

L (i, j) = G (i, j) * K (i, j) ^ (Ps (i, j)) * 2 where single precision, double precision, and double precision , P
= 0, 1 or 2. It has additional precision (incremental)
Compensated in step 9.2, which needs to be eliminated on the right shift.

Unfortunately, no very effective single classification scheme has been found. At present, the difficulty level P is the following four sources a) The difficulty level of the image area where P left and P up are adjacent b) sum (i + j) G (i, j) ′ 2) / sum (G ( i, j) ′ 2 is the distortion of the conversion energy c) −G (0,0) is the inverted mean luminance d) max (sum over fixed width (Histogram (v (i,
j)))) is used as a troublesome method.

In step 7, the transformed data L (,) to be stored or transferred can be further reduced by entropy coding. CCITT created zigzag run and template codes on some default Hoffman tables according to bit rate.
(template code) is used and is recommended. For determinism, examples of this will be described in detail in the following sections.

Example of compressed file format: A compressed image is expressed as follows. 1) Prefix (image width, height, rate scaler M, etc.) 2) Pixel block 0 Pixel block 1 Pixel block 2 ... Pixel block N-1 3) Suffix (if any)

Here, each pixel block is expressed as follows. 1) Precision code (determined in the selection stage Z) 2) DC coefficient delta code 3) AC coefficient code (0 or more iterations) 4) Block termination code

Here, each AC coefficient code is expressed as follows. 1) 9-digit 0 extension (E times repeated, E0) 2) Run and template code description (R, T) 3) Coefficient value code (1 bit) 4) Absolute value of coefficient with the most significant bit removed (T bit)

Here, "R + (* E" is the number of zero-valued coefficients preceding this in a "zigzag" order, and T is the bit position of the most significant bit of the absolute value of the coefficient, for example, T =
If 3, the coefficient is 11 or -11. Bit position: 876543210 11 = 000001011 (binary) --- most significant bit

The selection or encoding of the DC coefficient delta will not be detailed, but it will be the AC run and template.
e) An example of a Hoffman code useful as a code at a higher bit rate is presented below. Note that {0} is n consecutive 0s (n = 0, 1, 2,
, ...), where xx is 2 bits interpreted as w = 0, 1, 2 or 3 and x is 1 bit interpreted as w = 0 or 1.

128-point and 256-point transforms ... The above method can be used with larger 8 × 16 or 16 × 16 generalized chain transforms. Furthermore, the generalized method for the Chien transform is a one-dimensional 16-point GCT.
However, it should be clear by describing that it is given by the following equation (there is no need for post-standardization multiplication accompanied by the row of "butterfly permutation").

[0088]

[Equation 57]

Here, GCT 8 (a, b, c, r), G
Q 8 (e, f, g, h, r, s, t) is shown in Equation 58.

[Equation 58]

Furthermore, the "true cosine" parameter is
It is shown by the following formula.

Q = tan 15 pi / 32 ≈ 10.1532 a = tan 14 pi / 32 ≈ 5.0273 f = tan 13 pi / 32 ≈ 3.2966 b = tan 12 pi / 32 ≈ 2.4142 g = tan 11 pi / 32 ≈ 1.8709 c = tan 10 pi / 32 ≈ 1.4966 h = tan 9pi / 32 ≈ 1.2185 r = cos 8pi / 32 ≈ 0.7071 t = cos 12pi / 32 ≈ 0.3827 s = cos 4pi / 32 = t * b

The parameters used are as follows:

[Equation 60] e = 10 a = 5 f = 3.25 b = 2.4 g = 1.875 c = 1.5 h = 1.25 r = 17 / 240.708333 t = 5/13 ≈ 0.384615 s = t * b = 12/13 GQ 8 (e , F, g, h, r, s, t) is the inverse of GQ
8 (e, f, g, h, 1 / 2r, t ', b, t').

Here,

B = s / t t ′ = 1 / (t + t * b * b).

[Example of determinant ...] Transposition of determinant TP Cosine transform (a = 5.02734, b = 2.41421, c = 1.4966
1, r = 0.70711)

(Expression 62) 0.1768 0.1768 0.1768 0.1768 0.1768 0.1768 0.1768 0.1768 0.2452 0.2079 0.1389 0.0488 -0.0488 -0.1389 -0.2079 -0.2452 0.2310 0.0957 -0.0957 -0.2310 -0.2310 -0.0957 0.0957 0.2310 0.2070 -0.0488 -0.2452 -0.1389 0.1389 0.2452 0.0488 -0.2079 0.1768- 0.1768 -0.1768 0.1768 0.1768 -0.1768 0.1768 0.1768 0.1389 -0.2452 0.0488 0.2079 -0.2079 -0.0488 0.2452 -0.1389 0.0957 -0.2310 0.2310 -0.0957 -0.0957 -0.2310 -0.2310 0.0957 0.0488 -0.1389 0.2079 -0.2452 0.2452 0.2452 -0.2079 0.1389

Associated Chain Transform (a = 5.0, b = 2.4, c =
1.5, r = 0.7)

(Equation 63) 0.1768 0.1768 0.1768 0.1768 0.1768 0.1768 0.1768 0.1768 0.2451 0.2059 0.1373 0.0490 -0.0490 -0.1373 -0.2059 -0.2451 0.2308 0.0962 -0.0962 -0.2308 -0.2308 -0.0962 0.0962 0.2308 0.2080 -0.0485 -0.2427 -0.1387 0.1387 0.2427 0.0485 -0.2080 0.1768- 0.1768 -0.1768 0.1768 0.1768 -0.1768 -0.1768 0.1768 0.1387 -0.2427 0.0485 0.2080 -0.2080 -0.0485 0.2427 -0.1387 0.0962 -0.2308 0.2308 -0.0962 -0.0962 0.2308 -0.2308 0.0962 0.0490 -0.1373 0.2059 -0.2451 0.2451 -0.2059 0.1373 -0.0490

[0095]

Detailed Description of the Apparatus Having provided a detailed description of the present invention, an apparatus embodying aspects of the present invention will be described. Throughout the following discussion, "point" represents a scaler register or datapath of arbitrary precision,
Usually 8 to 12 bits. Methods for determining the appropriate precision are known (reference "Jalari and Lao.
"Limited word length and accuracy of FDCT processing" IEEE ASS
See P-81, Volume 3, pages 1180-2 ").

In the software method, the conversion stages were integrated and the U. Paolini extension was adopted. In the semiconductor device of the preferred embodiment, it is most convenient to simply provide two 8-point converters, one for vertical and one for horizontal detection. It is necessary to provide a 64-point shift array between the vertical and horizontal transforms, as well as a buffer between the transform and the encoder.

Although the present invention includes a black and white device and / or separate devices for compression and decompression, the preferred embodiment (FIG. 7) is a compressor (image data compression device ... 1 (a)) and a decompressor (image data decompression device ... Fig. 1 (b)).

The data is stored in the compressor in a vector of 8 pixels (see FIG. 2A), which is further arranged in a block of 64 pixels in the order of the dictionary. The block processing is pipelined (FIG. 2 (b)). Pixel input to the compressor consists of "R" (red), "G" (green) and "B" (blue). These are immediately transformed into luminance-chrominance space (the reasons for such transformations are well known).

The transformation can use any fixed or programmable coefficient (FIG. 3 (a)), or it can be "hardwired" to simple values for dedicated applications. The conversion space is represented by XYZ here, but 3
Any linear form of primary color input may be used, C
The CITT standard (Y, RY, BY) is also possible. In fact, the three values of X, Y, Z are each fed to a separate black and white compressor. The decompressor uses the same or equivalent circuitry as in FIG. 3, but differs in that the XYZ vectors are now converted to RGB vectors.

The values Y, X, Z are input to the three shift registers (see FIG. 5) and await supply to the first conversion unit. Since the transform unit operates by (2 + 2/3) pixel times, some of the data will be delayed as shown. The indication "XYZ" is an incorrect bit. The optimized coding scheme requires the luminance ("Y") to be processed first.

During the decompression process, the XYZ distortion problem is reversed. Note that 5 points of the register are saved in the preferred embodiment by inverting the use of the Y and Z shift registers during decompression.

Referring to FIG. 1 (a), the main part of the compressor transforms its input into XYZ space and buffers it for transfer to a subsequent transformation unit 3.
including. The conversion 1 unit performs a triple cycle for each section of 8 pixels (once for each of the X, Y, and Z data). The output of transform 1 is placed in shift array 4, where it is held until the 8x8 pixel block is completely read. The conversion 2 units 5 and 6 operate the pre-read pixel block, and each of the 8 pixel block sections has 3 units.
Double the cycle and provide the data to the encoder input buffers 7, 8. The coding circuits 9, 10, 11 are also shared between the three primary color coordinates, but the entire luminance block is coded without interruption, followed by each of the chrominance blocks. The processing of these 3 blocks is 64
If it cannot be completed within the pixel interval, the timing and control logic circuit holds the pixel clock to the external input circuit. The storage areas (the input shift register 2, the shift array 4, and the encoding circuit input buffers 7 and 8) need to be made in three sets for the three primary colors.
5, 6, 9, 10, and 11 are shared (time division) among Y, X, and Z data.

Encoding circuits 9, 10, 11, encoding circuit input buffers 7, 8, code programming 12, 13, 1.
4 and the timing and control logic (not shown) may follow conventional techniques or methods. Similarly, methods for time-sharing the three primary colors with a single circuit are also well known. Three
The point converter 1 (see FIG. 3) and the shift register 2 (see FIG. 5) are also known.

The scaler 6 (FIG. 1) uses the quantisation multiplier of the present invention described below. This is a simple realization. The 8-point conversion circuit (see FIGS. 8 and 9) is also simple, given the definition of the generalized Cheng conversion and appropriate parameters. The shift array (FIG. 6 (a)) deserves special discussion. The vertical vector (converted to) from the current input block is assembled while the horizontal vector from the previous pixel block is supplied to the horizontal conversion circuit. 128 registers are required without special design (64 blocks each for the current block and the previous block)
This is because the points are used in a different order than they were received. However, this need is eliminated by shifting data from left to right during even numbered pixel blocks and from top to bottom during odd numbered pixel blocks. The described shift array is bidirectional. A four-way shift array is preferred in certain embodiments.

FIG. 6B shows the mode of the shift array of FIG. 6A in more detail. In the figure (b), the vectors are removed one by one from the shift array at the bottom and sent to the 8-point DCT5 part of the figure (a). Meanwhile, the vertical vector from the other 8-point DCT portion is input to the shift array at the top. Gradually the old vector is removed from the shift array and the shift array is completely filled with vertical vectors from the next block of pixels.

In the next pixel block, the data flow direction is different from the data flow direction of the immediately previous pixel block by 90 degrees. In this way, the horizontal vector is removed from the right of the shift array and sent to the 8-point DCT, with the new vertical vector coming in from the left. Block (N + 2)
Another 90 degree rotation returns to the original form, and so on.

The decompressor (see FIG. 1B) has a structure very similar to that of the compressor shown in FIG. 1A, but is different in that the data flow direction is opposite. In the preferred embodiment, a single device operates in two modes, either compressor or decompressor.

Possible VLSI arrangements (see FIG. 4) have different data flows for compression (FIGS. 4 (b) (c)) and expansion (FIGS. 4 (e) (f)). Other data flows are possible with the pipelined implementation method described in detail in the following chapters. The operation of the transform and shift array units has the same directional meaning for both compression and decompression in one arrangement, but not in the other (see Figure 4 (a)).
This is more clearly seen when considering the integrated compressor / decompressor data flow (FIG. 7).
If two transform units are involved in each of the RGB and compressed data (Fig. 4 (a)), the placement difficulty will not be resolved unless a four-way shift array is used. Therefore, two conversion units are respectively associated with the input and output parts of the shift array (FIG. 4 (d)).

In one embodiment, the conversion unit in the compressor (see FIG. 8) uses 38 adders. Shift one ("R1"), two ("R2"), or four ("R4") positions to the right or one to the left ("L1")
It is easy to shift the 1 ") position. The circuit shown uses the parameters (a, b, c, r) = (5,2.4,1.5,17 / 24). B = 2.5. In the implementation method described above, only 36 adders were required in the other embodiment.

An associated circuit is required in the inverse transform unit of the decompressor. By careful use of the "output enable" signal, most adders in the forward transform circuit can be reused. Implementation of this would be easy for a person skilled in the art. The scaler uses a programmed RAM or ROM and a system of unconditional shift, multiplexer and adder circuits. This is a simple realization. Descaler can be realized by various methods, but a multiplier with RAM connected to a small hard wire, an accumulator,
Timing and control logic and a small template cutoff are desirable. In dedicated low cost applications, the descaler can be simplified by noting that the debra ring weights are nearly optimal over a wide range. Therefore, simple scaling can be used in the scaler. The descaler can be placed either between the encoding circuit and its output buffer, or between the output buffer and the conversion circuit, as shown in FIGS. 1 (b) and 7. The encoding circuit input buffer can be implemented in various ways and includes a cycle sharing register reduction arrangement similar to a shift array. 384 x 1 for a simpler design
RA using 64x7 bit ROM for 0 bit RAM
Provides M address.

An example of the operation cycle will be described in relation to FIG. 1 (a) and FIG. 1 (b). In the same figure (a), the data is input to the compressor as three primary color information, red, green and blue. It is immediately transformed into an alternative space called XYZ. The three elements X, Y, Z are input to each shift register. From the shift register (step 2) these go to the 8-point DCT unit. One 8-point DCT unit multiplexed between the three primary colors X, Y, Z, or each having an independent 8-point DCT unit,
Either of them can be. Information is input to the 64-point shift array 4. There is a separate shift array for each color. Information is transferred from block 4 shift array to block 3
Proceed to another DCT unit in block 5, similar to. The information is compressed here, which is the further layer of the added shift. Information is transformed only in both horizontal and vertical directions. The shift array actually rotates the data 90 degrees conceptually, allowing it to be translated in the other direction.
After compression of the data, the data goes to another buffer (Z1 and Z2) indicated by blocks 7 and 8 where the data is held so that it is finally encoded and output from the chip (Z1 and Z2 are equal). It is zigzag).

Conceptually, this is similar to the shift array of block 4 except that the data is not rotated 90 degrees. Instead, the zigzag order used in the CCITT standard has been changed in the related art. The information is passed to the run and template control unit of block 9 where 0 is detected and 0
, Run non-zero and detect the log-valued estimate of the value. This is called a template. The combination of run and template, referred to as the RT code, is referenced in RAM or ROM and is output from the chip.

The mantissa part, which is the upper bit of the transform coefficient, is also output from the chip. The mantissa part, the run, and the template code may be of any length, 1 bit, 2 bits, etc., and the output from the chip is always 16 bits, 8 bits, 32 bits, etc., so block 11 (alignment) facilitates this. To

The programming blocks 12 and 13 of the other blocks (arbitrary) shown in FIG. 1A are for XYZ conversion of arbitrary RGB, arbitrary weights of rate scaler and psychological factor, and runs and templates. It can be set to any modified Hoffman code.

FIG. 1B is very similar to FIG. The run and template codes now have to be decoded into a combination of run and template, with the required number of 0's.
Must be ignored.

In FIG. 1A, the scaler 7 is a simple array of adder circuits and shift circuits. In the figure (b), the descaler 15 is realized as a multiplier of extremely small hardware.

FIG. 10 shows a schematic of a non-pipelined implementation of the two-dimensional generalized Chien transform. Pipelined implementation will be explained in a later section. The pixels enter from the top and are usually 8 bits wide. The pixels pass through a wide array of adders in the horizontal converter circuit 10 with a standard 128 bit data width. The output from the horizontal conversion circuit passes through the transfer RAM 12 to rotate the information from the horizontal direction to the vertical direction. The data then passes through a vertical conversion circuit 16, which also consists of an adder circuit only (usually 128 bits wide). The output coefficients are eventually reduced to a width of approximately 16 bits and pass through a single multiplier 20 which is JPEG compatible in the present invention.

FIG. 11 is a block diagram of VLSI packaging according to the present invention. In FIG. 11, the data is block 40.
Is input to the input latch 42, is latched in the input latch 42, passes through the multiplexer 44, and proceeds to the first half of the GCT conversion circuit 50 (this is composed of an adder network as shown in FIG. 8). The latter half of the GCT conversion circuit 50 is connected to the right side of the interruption latch 54. The output is passed through a multiplexer 62 and the transfer RAM for horizontal to vertical conversion is performed.
Proceed to 66. The output of the transfer RAM 66 is supplied to the background to the first stage of the GCT conversion circuit 50 for the purpose of forming the first half of the vertical conversion in a time sharing or time slicing arrangement. The output of the GCT conversion circuit 50 is supplied to the input of the second stage of the vertical GCT conversion circuit 60. The output of the last GCT conversion circuit 60 is taken from the output latch / multiplexer 70, passes through the multiplier 74 and the rounding circuit 76 to the zigzag ordering circuit 80, and its output is output from the block 84 as a 12-bit coefficient. It

Further, with reference to FIG. 11, the process of the reverse transformation of the present invention will be briefly described. In FIG. 11, the 12-bit coefficient passes through the block 84 and the zigzag sequential circuit 80.
To the Y input of the. The output of the zigzag sequential circuit 80 is passed through a multiplier 74 and a rounding circuit 76 which performs an inverse quantization process similar to that performed in the forward process. The output of the multiplier 74 is input to the latch 42 which is the first stage of the reverse conversion process. From the latch 42, the reverse transform process follows the same two-stage time multiplex path that the forward process followed. The output appears in the output latch 70, the output of which is the pixel rounded by the rounding circuit 76, and the output of the rounding circuit 76 is provided to the output 2 block 40.

[0120]

Quantization Multiplier of the Present Invention To compress a large amount of data to be encoded, the frequency domain coefficient F (i, j) is divided by a positive integer quantum value Q (i, j), and further, Rounded to the nearest integer (note that Q (i, j) is used to represent quantum determinants in this chapter, as opposed to the previous chapter). On the contrary, the reverse operation requires multiplication by Q (i, j). Large quantum values provide significant compression, but lead to significant degradation of image quality (as measured by root mean square error (MSE)). Small quantum values do not provide significant compression, but produce smaller MSE.

The quantized coefficient Q (i, j) can be combined with a matrix of stages C, D and E, referred to herein as the forward scaling matrix Sf (i, j). Similarly, the inversion of the quantized coefficients can also be combined with the determinant of steps H and I, referred to herein as the inversion scaling matrix Si (i, j). Therefore, the forward transform is Sf / Q (the exponent part was deleted for convenience)
, And the inverse transform is related to the application of Si * Q. Since the forward operation is division, there is an inverse correlation between the magnitude of Q and the mathematical resolution of S. In terms of computational efficiency, integer division is generally performed by multiplication and shift. For example, in a 16-bit calculation, the integer k
The division by can be performed more expediently by a multiplication of 2 ¹⁶ / k = 65536 / k followed by a 16-bit right shift.

In the inverse transform, there is an inverse correlation between the Q and Si ranges due to the multiplication of Q and Si, so that there is an antiphase between the Q range and the product resolution. become. In the JPEG reference system, the quantized value is unsigned 11 bits. Therefore, the maximum possible quantization coefficient is 1023 or 2 ¹⁰ . If the multiplication is carried out in a 16-bit calculation, Si has a range of 2 ⁶ . Q
The smaller the value of, the greater the resolution of Si is than MSE.

Conventional Method ... Most modern computers, microprocessors and dedicated digital signal processing chips have 32 bits (32b).
Having multiplication and more than enough to solve this problem when used correctly.

In high speed dedicated hardware, it is desirable to use the same multiplier for both forward and backward transforms. At “real time” speeds (approximately 30 megacycles or more for video images),
The 16b multiplication circuit is close to the resolution that is most easily realized. In addition, large multipliers require more silicon and are slower to execute. Some JPEG transform chips use a discrete cosine transform DCT instead of a generalized Cheng transform and do not have the need for scaling and pre-scaling, Sf and Si. On the other hand, many DCT implementations require some form of scaling that the GCT calls.

Note, however, that for a reasonable MSE, most of the 32-bit output needs to be freely available. In positive mode, division is achieved by reducing the number from a large standardized number. You need to get the result from the high order bits of the output. In reverse mode, the numbers are multiplied, so a small standardized number is desirable. You need to get the result from the low order bits of the output. There is little or no reduction in combinatorial multiplier hardware, such as truncation of unnecessary bits.

If the multiplication is limited to 16 bits, then
The performance is significantly reduced due to US patent application Ser. No. 07/5
This corresponds to the cross-referenced example of the generalized Cheng transform of No. 11,245 (see the performance discussion section below). In particular, the range of Q competes with the range of Si in the inverse transform. The resolution of Si is most important when the quantization value is low, because a large quantization number adds distortion so large that the resolution of the multiplication makes no sense.

DESCRIPTION OF THE INVENTION One of the objects of the present invention is to provide maximum performance using 16-bit hardware multipliers, ie 16-bit arithmetic, with both forward and backward quantization. That is. This requires a balance between range and resolution.

Forward Scaling and Quantization In empirical mode, empirical results indicate that a 16-bit hardware multiplier can provide sufficient resolution. The largest value (Sf × 2 ¹⁶ ) is (2 ¹⁶ −
It is possible to select 1). Big Q
Reduces the range of values of (Sf / Q × 2 ¹⁶ ), but the error due to the lack of resolution of this number is small compared to the error introduced by quantization.

By properly scaling the input as well as Sf / Q, the output appears in the upper N bits of the multiplier output. That is,

[Equation 64] Result = (input * Q coefficient) >> N where ">>" represents a shift operation to the right. Also,

[Equation 65] Q coefficient = Sf / Q * 2 ¹⁶ . The multiplication of two N-bit coefficients is generally a 2N-bit product. The result is the high-order side 1 of the hardware multiplier
Since it is taken from 6 bits, it is possible to truncate the gate supplying the lower 16 bits. All that is needed from the lower N bits is the relevant term.

This is illustrated in the method of implementation by the bimodal hardware shown in FIG. When performing forward conversion, the forward input (/ Forward) is at L level (that is, 0). Therefore, the control multiplexer (M
UX) 100 is a 0 input GND signal with 16 inputs and 1 output MU
Send to X104. The 0 signal on the forward input / Forward goes to the MUX 108 and sends 4 bits of the Q exponent to the 16 bits × 16 bits inputs A0 to A3 signed by the multiplier 106. In this example

Q coefficient = (Q mantissa part << 4) + Q exponent part, and the multiplier 106 generates the product “Q coefficient * input”. The output Result is equal to (Q coefficient * input >> 16) because the lower 16 digits are discarded as unused words.

Inverse Prescaling and Dequantization: The present invention performs inverse dequantization by allocating a compromise between range and resolution that allows the highest accuracy in 16-bit arithmetic. It is related to the assisting process. Empirically, MS that resolution of about 12 bits is desired
It was decided that it was necessary for E. Since 10 bits are required for quantization in the JPEG standard specifications, 24 bits are required as a range. This is achieved by using the upper 12 bits of the 16-bit coefficient as the mantissa and the lower 4 bits as the exponent term with base 2. With a combination of 2 ⁴ possible shift values and a (16-4) bit mantissa, the effective range is

[Equation 67] Effective range = [(16-4) +2 ⁴ ] bits = 28 bits. As shown in the two-mode hardware implementation of FIG. 12, in the reverse mode, when the forward input / Forward is at the H level, the 16-input 1-output MU
The control input to X104 produces an i digit left shift in the input value. The 12 bits of the Q mantissa are input to the inputs A4 to A15 of the multiplier 106. The control value on the H level side from the forward input / Forward to the MUX 108 sends 0 from the GND signal to the bits A0 to A3 of the multiplier 106. Here again, it should be noted that the output result exists in the upper 16 bits of the multiplication output and the 16 digits of the L level are discarded as unused words. The result will therefore be determined as

[Equation 68] Result = ((input << Q exponent part) * Q scaler) >> 16 where:

Q scaler << Q exponent part = Si x Q x 2 ¹⁶ Q scaler <2 ¹²

0 <Q exponent part <(2 ⁴ −1).

Since the input value is shifted to the left, the input needs to be restricted. Otherwise, the value will overflow, producing a false result. However, this is done unconditionally due to the fact that these numbers are quantized by the coefficients used here for multiplication. This is why the present invention cannot be generalized to any multiplication.

An extension of the invention is illustrated in FIG.
Here, the left shift by MUX 110 is 16 bits ×
It occurs after the multiplication step by the 16-bit MUX 112. In the forward conversion, the forward input / Forward is at the L level. The 0 signal to the control input of MUX 114 sends the 4 bits of the Q exponent to inputs A0-A3 of multiplier 112. The 16 most significant digits (Q31 to Q16) of the product of 32 bits of the multiplier 112 are selected according to the GND signal from the MUX 116 by the multiplexer of 16 inputs and 1 output.

In reverse conversion, forward input / Forwa
The rd signal is at H level. Therefore, the GND signal is MUX
16-bit × 16-bit signed multiplier 1 114
Sent to 12 inputs A0-A3. i = 32-Q exponent part and bit Qi-Qj of the 32 bit output from multiplier 112 such that j = i-15 is MUX11.
It is selected as a result according to the value of the Q exponent part input to the multiplier 110 having 16 inputs and 1 output via 6. The input value is not limited in range (ie, not pre-formatted), as no left shift of the input value is performed. In this case, the operation is mathematically expressed as follows.

[Equation 71] Result = (input * Q scaler) >> Q exponent >> 16

Performance discussion ... Table 1 shows 704 × 5 by CCITT which was experimentally executed.
Root Mean Error (MSE) for the Barbara image, a 76x8b gray level test image
It shows the result of. Quantization values are all 1's in the first example and in the second example are from the proposed luminance quantization table in the JPEG standard. The image is processed by software simulation of the chip using the present invention realized by the 32b multiplier, the 16b multiplier, and the 16b multiplier using the 12b mantissa part and the 4b exponent part as explained in the previous chapters. It was The results are shown in Table 1 below.

[0136]

[Table 1]

As can be inferred, the main difference in the multiplication engine occurs when Q is small, that is, when quality reproduction is desired. With less hardware,
The present invention provides an accuracy close to 32 bits. MS
The difference at E is not visually significant. However, CCITT
Recommendation H. To comply with the 261 conversion nonconformance follow-up test,
The present invention requires the use of discrete cosine transforms and parameter values that more closely approximate.

Implementing a 32b multiplier would use approximately 85% more silicon surface area than a 16b multiplier (estimate based on 1.0 μm CMOS standard cell technology. This is for HGCT implementations). Technology), which is a major problem in integrated circuit technology. The present invention only adds 30% to this area. It is worth noting that a single multiplier uses approximately 10% of the silicon.

[0139]

[Pipelined implementation of GCT conversion] Background ... It is desired to manufacture a VLSI chip that implements the international standard image compression system proposed by the JPEG committee of CCITT. Many applications require VLSI chips to operate at video speeds, which means (depending on resolution) about 8 to 10 million pixels per second. Each pixel is usually 3 such as red, green, blue, etc.
It consists of primary colors. Most VLSI implementations operate on one component at a time and the required clock frequency is three times the pixel rate. This will boost the clock frequency of the chip to approximately 25-30 MHz. This is a high clock speed by the 1991 standard.

The most conventional implementation of DCT uses a combination of multipliers and adders to perform the transformation. Multipliers are often an obstacle in many implementations. Other functions, such as RAM and ROM, constitute a secondary obstacle. To overcome these obstacles, use long pipeline structures. A pipeline in a typical DCT chip can extend up to 200 clock cycles, meaning that 200 processes are occurring in parallel within the chip.

FIG. 15 shows a conventional pipeline structure in the discrete cosine transform. The pixel components arrive on the left hand side of the drawing and are latched inside the latch device 120 in a parallel vector of size 1x8. These 1 × 8 vectors are passed to the one-dimensional transform circuit 122 to perform the DCT. The 1 × 8 row vector is then transposed by the transposition device 124 to be converted into a column vector having an 8 × 1 shape. After transposition, in the conventional system, the transposed vector is transferred to the second DCT unit 126 for conversion.
Is supplied to. While this second conversion is taking place,
The first transform unit 122 is occupied by the next 1 × 8 row vector. Therefore, the pipeline works effectively. The final multiplication is performed in multiplication unit 128.
Since DCT is a computational impediment to the system, structures such as those described above are required to achieve video rates.

Although FIG. 15 has been simplified for clarity, it is important to understand the constraints on the overall transformation. Recall that multiplication operations are a bottleneck in the system. The conversion units 122, 126 include multiplications, so that they and the last multiplier 128 constitute roughly equal faults. Now assume that it takes x nanoseconds to perform a single multiplication. In FIG. 15 (where there are two transform units 122 and 126), each transform unit 122, 126 simultaneously performs an 8-component calculation. Therefore, the conversion unit is performing the calculation in 8x nanoseconds. This is still feasible today with today's architecture.

The Invention The Generalized Chain Transform (GCT) of the present invention requires no multiplication in the main transform, only one multiplication per component at the end of the conversion process. Main one-dimensional GC
T is some 3 made up of up to 7 discontinuity levels
It consists of an array of 8 adder circuits (see FIGS. 8, 9 and 1).
0). The adder circuit array includes hard-wired shift circuits, which can generate the exponential multiplication and division as described above. Furthermore, by dividing the seven stages into two separate parts (GCT
(This division is easy due to the simple structure of), and the maximum number of adder circuit levels is reduced to four. By doing this division, the conversion is no longer an obstacle to the flow of data. This means that maximum capability is controlled by the design of these devices. However, now that the last multiplication becomes an obstacle, it is possible to use additional features in the conversion unit. FIG. 14 illustrates such a configuration.

In FIG. 14, following the input latch 130 for the 8 × 1 row vector is a MUX 132 that selects one of the two inputs supplied to the one-dimensional conversion circuit 134. The important difference here is that there is only one conversion unit 134. After a predetermined amount of time, transform unit 134 completes the transform on the input row vector. After being passed to the transfer RAM 136, the transformed row vector is returned by the second MUX 138 to the first MUX 132 and further to the only translation unit 134. The columns are converted here. After the columns have been transformed and transposed, the result is forwarded to multiplier 140. It is clear that on average the conversion unit should operate in 4x nanoseconds. This is,
This is where the GCT network of simple adder circuits offers great advantages. The adder circuit is significantly faster than the multiplier, thus enabling such time division multiplication.

The GCT itself is a significant savings over the DCT. The realization method shown in FIG. 14 is not one but two.
Just because it has only one conversion unit,
It offers an additional 50% savings. Looking at this, the design of the present invention has only one conversion unit 134, and this unit is 40% on chip.
Occupy% to 50%. The remaining 50% is allocated to RAM, latches, multipliers 140, I / O, etc.
It will be appreciated that the second conversion unit will increase the silicon area by approximately 50%.

The use of a network of adder circuits only, in combination with time division multiplication, provides an efficient JPEG implementation that provides performance greater than 50% above video speed.

After all, a transform such as DCT is useful for image compression, and a method similar to DCT is desirable in terms of computational simplicity. In this respect, the method and apparatus disclosed in the present invention can perform a quantization operation at a speed comparable to 16-bit conversion, and the root mean square error is comparable to that of 32-bit conversion. Effectively pipelined data flow by factorizing the transform into a relatively fast set of additions and a set of multiplications, with the addition part of the vertical and horizontal conversions being the final stage. Will be executed by the same hardware before the multiplication part of.

[0148]

Generalization Although the embodiments in this disclosure are limited to transforms based on image coding, the multiplier of the present invention allows any output where the output is multiplied by the same number that the input is divided. It can be generalized to a quantization method. Although some algorithms use similar quantization schemes, they can be generalized to some extent, but the multipliers of the present invention have meaning only in the context of quantization and dequantization. While the preferred embodiment uses 16-bit arithmetic, the present invention is generally applicable to such processes using N-bit arithmetic. Also, the present invention is compatible with existing standards such as the JPEG standard. The preferred embodiment has been chosen and described in such a manner as to best explain the principles of the invention, and the actual application by which those skilled in the art will appreciate that the invention and various embodiments may be best practiced. It can be used and various modifications can be made to suit the particular intended use. The scope of the invention is intended to be defined only by the claims that follow.

[0149]

Since the present invention is configured as described above, the still image data decompression method, compression method, and corresponding apparatus can maintain compatibility with the JPEG standard. The use of bits in the quantization and compression stages is optimized and the root mean square error in data compression schemes that integrate quantization and coefficient compression can be minimized. Further, in the method of optimizing the range of data compression and the resolution, it is possible to use a fixed amount of bits, and for a small quantization value, the resolution is JPEG standard H.264. The H.261 specifications can also be adapted. That is, more specifically, by using a 16-input 1-output multiplexer and a 16-bit multiplier, it is possible to perform preliminary compression for quantization with a dynamic range of 28 bits. Moreover, in pipelined implementations of the transformation process, the speed of generalized chain transformation can be used to the full advantage. It is also possible to minimize the number of gates required to perform the conversion process, and in particular to take advantage of the speed advantage of the adder network portion that performs the conversion process, both vertically and horizontally by the same hardware. The addition of transformations can be performed.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, (a) is a block diagram of a compressor configuration, and (b) is a block diagram of a decompressor configuration.

2A and 2B are diagrams for explaining the operation, where FIG. 2A is an explanatory diagram showing the order of input pixels, FIG. 2B is a block timing diagram, and FIG. 2C is a vector timing diagram.

FIG. 3 is a block diagram showing three-point conversion of data from RGB to XYZ.

FIG. 4 is a schematic diagram showing a layout of VLSI.

FIG. 5 is a schematic block diagram showing a shift register configuration example.

FIG. 6 shows a shift array configuration example, (a) is a schematic block diagram, and (b) is a block diagram of a specific configuration thereof.

FIG. 7 is a schematic diagram showing a flow of integrated data.

FIG. 8 is a block diagram showing a configuration example of an addition array in forward processing.

FIG. 9 is a block diagram showing another example of the addition array configuration of the forward processing.

FIG. 10 is a schematic block diagram showing a two-dimensional generalized Chien transform.

FIG. 11 is a block diagram showing a preferred embodiment of the present invention.

FIG. 12 is a block diagram showing a hardware configuration example for inversion precompression and quantization with shift before multiplication.

FIG. 13 is a block diagram illustrating a hardware configuration example for inversion precompression and quantization with shift after multiplication.

FIG. 14 is a block diagram schematically showing a flow of implementation of a two-dimensional generalized chain transformation that utilizes the speed of transformation of the present invention.

FIG. 15 is a block diagram schematically showing a flow of realizing a conventional two-dimensional DCT calculation.

[Explanation of symbols]

 12 migration memory means 16 conversion means 50 first GCT addition circuit network stage 60 first GCT addition circuit network stage 66 migration memory means 74 multiplication table means 76 rounding means 80 zigzag order means 134 conversion means 136 migration memory means

Claims (57)

[Claims] 1. A method of decompressing still image data for inverting a transform for transforming a sequence of original values into a sequence of transform domain coefficients, wherein each of the transform domain coefficients is Q.
The M-bit exponent identified as the exponent and the (N−M) -bit mantissa identified as the Q mantissa are multiplied by the Q coefficient stored in the N-bit save register, Q coefficient = Q A mantissa part * 2 ^ Q to provide the Q coefficient with a value in the range larger than 2 ^ N by forming an exponential part; and a second step of approximating the sequence of the transformed domain coefficient to the original sequence of values. And a step of converting it into a sequence of values. 2. The method of decompressing still image data as claimed in claim 1, wherein the step of multiplying includes the steps of multiplying by Q mantissa using an integer multiplier unit and shifting left by Q exponent bits. 3. The method of decompressing still image data according to claim 2, wherein the step of left shifting by the Q exponent bits follows the step of multiplying by the Q mantissa using an integer multiplier unit. 4. The method of decompressing still image data according to claim 2, wherein the step of multiplying by the Q mantissa using the integer multiplier unit follows the step of left shifting by the Q exponent bits. 5. The still image data decompression method according to claim 2, further comprising a scaling coefficient and a quantized coefficient, and a Q coefficient being equal to a product of the scaling coefficient and the quantized coefficient. 6. The sequence of transform domain coefficients has a value of length L, and an inverse transform operation is divided into a network of adder circuit arrays into said initial multiplication of length L and a series of add and shifts. The still image data decompression method according to claim 1, further comprising: 7. An inverse transformation operation is divided into a product of a diagonal determinant and a non-diagonal determinant, including the use of an adder array, and a diagonal determinant operation can be performed by the adder array. The method for expanding still image data according to claim 1. 8. The method of decompressing still image data according to claim 7, wherein the adder circuit array has seven stages or less and comprises 39 or less adder circuit units. 9. The method for decompressing still image data according to claim 7, wherein the transform is a generalized Cheng transform that approximates a discrete cosine transform. 10. The still image data expansion method according to claim 5, wherein the scaling coefficient includes a psychological factor weighting coefficient. 11. The still image data decompression method according to claim 5, wherein the scaling coefficient includes a debraing coefficient. 12. The method of decompressing still image data according to claim 2, wherein the original sequence values represent a two-dimensional grid of image pixels. 13. The method of decompressing still image data according to claim 1, wherein N is equal to 16 and M is equal to 4. 14. The method of decompressing still image data according to claim 2, wherein the Q coefficient is standardized in advance by 2 ^ N, and the lower N digits of the multiplication product are discarded. 15. A method of compressing still image data for performing conversion from a value of an original sequence into a sequence of transform domain coefficients, the method comprising converting the sequence of original values into a sequence of converted values. Transforming the sequence of transformed values into a sequence of transform domain coefficients by multiplying each transformed value by a Q coefficient, and discarding the lower N bits of the output, where the Q coefficient is 2
A method of compressing still image data, which is standardized in advance by a factor of ^ N and is stored in an N-bit storage register. 16. The method of compressing still image data according to claim 15, further comprising a scaling coefficient and a quantized coefficient, wherein the Q coefficient is equal to 2 ^ N times the scaling coefficient divided by the quantized coefficient. . 17. The maximum value of all Q factors is (2 ^ N −
17. The method of compressing still image data according to claim 16, which is characterized in 1). 18. The static of claim 15, wherein the original sequence of values has a value of length L and the transformation operation is divided into a series of additions and a final multiplication of said length L. Image data compression method. 19. The still image data according to claim 15, wherein the transform operation is divided into a product of a diagonal determinant and a non-diagonal determinant, and the operation by the non-diagonal determinant can be executed by an adder circuit array. Compression method. 20. The adder circuit array has 7 stages or less.
20. The method of compressing still image data according to claim 19, characterized by comprising not more than one adder circuit unit. 21. The method of compressing still image data according to claim 19, wherein the transform is a generalized Cheng transform that approximates a discrete cosine transform. 22. The method of compressing still image data according to claim 16, wherein the scaling coefficient includes an inverse psychological factor weighting coefficient. 23. The original sequence value is 2 of the image pixels.
16. The method of compressing still image data according to claim 15, wherein the method represents a three-dimensional lattice. 24. The method of compressing still image data according to claim 15, wherein N is equal to 16. 25. In a forward mode / reverse mode bimodal processor for performing multiplication of an input integer and a Q value to calculate a product, the input integer is left-shifted by shifting an integer number of bits. , An integer multiplier for multiplying the coefficient with the shifted input integer, and 2
A mode Q value processor, the shift integer is set to 0 and the coefficient is set equal to the Q value when the processor is in forward mode, and the shift integer is Q index when the processor is in reverse mode. The two-mode processing device is characterized in that the coefficient set to the part is equal to the Q mantissa part, and Q value = Q mantissa part * 2 ^ Q exponent part. 26. Including a compression factor, the Q factor is inversely proportional to the compression factor in forward mode and the Q factor is inversely proportional to the compression factor in reverse mode, whereby the device functions as a data compression / decompression device. The two-mode processing device according to claim 25, wherein: 27. A 4-bit storage register, a 12-bit storage register, and a 16-bit storage register, wherein a Q exponent part is stored in the 4-bit storage register,
27. The two-mode processing device according to claim 26, wherein a Q mantissa part is stored in the 12-bit storage register and an input integer is stored in the 16-bit storage register. 28. The Q value is premultiplied by 2 ^ N,
26. The bimodal processor of claim 25, wherein N bits are clipped from the multiplier output. 29. The two-mode processing apparatus according to claim 25, wherein the input integer is a generalized Chien transform coefficient in the backward mode. 30. The Q value in a forward mode is proportional to a psychological factor weighting coefficient, and the Q value in a reverse mode is proportional to a reverse psychological factor weighting coefficient. Mode processor. 31. The two-mode processor according to claim 26, wherein the Q value is proportional to the debraling coefficient in the forward mode. 32. In a forward mode / reverse mode bimodal processor for performing multiplication of an input integer and a Q value to calculate a product, the input multiplier is left-shifted by shifting an integer number of bits. And an integer multiplier unit for pre-multiplying the coefficient with the input integer,
The shift integer is set to 0 and the coefficient is set to the Q value when the processing device is in the forward mode and the processing device is in the forward mode, and the shift integer is the Q index when the processing device is in the backward mode. The two-mode processing device is characterized in that the coefficient set to the part is equal to the Q mantissa part, and Q value = Q mantissa part * 2 ^ Q exponent part. 33. A compression factor is included, in a forward mode the Q factor is inversely proportional to the compression factor, and in the reverse mode the Q factor is proportional to the compression factor, whereby the device is a data compression / decompression device. 33. The bimodal processor of claim 32, which is functional. 34. A 4-bit storage register, a 12-bit storage register, and a 16-bit storage register, wherein a Q exponent part is stored in the 4-bit storage register,
34. The two-mode processing device according to claim 33, wherein a Q mantissa part is stored in the 12-bit storage register and an input integer is stored in the 16-bit storage register. 35. The Q value is premultiplied by 2 ^ N,
34. The bimodal processor of claim 33, wherein N bits are clipped from the multiplier output. 36. Two-mode processing according to claim 35, comprising three sets of 16-bit storage registers, wherein the Q value, the product, and the input integer are stored in the storage registers. apparatus. 37. The two-mode processor of claim 32, wherein the input integers form a generalized Chien transform coefficient in reverse mode. 38. The Q value in a forward mode is proportional to a psychological factor weighting coefficient, and the Q value in a reverse mode is proportional to a reverse psychological factor weighting coefficient. Mode processor. 39. The two-mode processing device according to claim 33, wherein the Q value is proportional to the debraling coefficient in the forward mode. 40. In a two-dimensional transformation method using a pipelined structure to perform a two-dimensional transformation, the two-dimensional transformation is divided into two consecutive one-dimensional transformations, wherein the two one-dimensional transformations are Each of the two steps is divided into a high speed step and a low speed step, the high speed step has a faster calculation time than the low speed step, and the two high speed steps of the two one-dimensional transformations are combined into a pipeline structure. A two-dimensional conversion method comprising the steps of: performing in two parts. 41. The two-dimensional conversion method according to claim 40, wherein each of the high-speed steps is executed by a network of adder circuit arrays. 42. The two-dimensional conversion method according to claim 40, wherein the two high-speed steps are successively executed by a network of substantially the same adder circuit array. 43. The two slow stages are algebraically integrated,
The two-dimensional conversion method according to claim 42, wherein the two-dimensional conversion method is executed as a single step. 44. The two-dimensional conversion method according to claim 43, wherein the one-dimensional conversion is a generalized Cheng transform that approximates a discrete cosine transform. 45. A two-dimensional conversion device having a pipelined structure for executing a two-dimensional conversion divided into two one-dimensional conversions, wherein a first processing device in the pipeline of the pipelined structure is used. And each of the one-dimensional transforms can be divided into a first part and a second part, the first processing device performing the first part of the one-dimensional transform, and a first set A vector in the pipeline of the pipelined structure for rearranging the vectors of the first set of vectors to generate the second set of vectors, the Nth vector of the Mth vector of the first set of vectors. The entry is the Mth entry of the Nth vector of the second set of vectors, and the second processor is pipelined to perform the second part of the one-dimensional transformation. Construction pipeline And a transfer system for introducing a third set of vectors into the first processing unit to generate the first set of vectors. Means for introducing the first set of vectors into the transfer device to generate the second set of vectors; and introducing the second set of vectors into the first processing device. And means for generating a vector of four sets, and means for introducing the vector of the fourth set to the second processing device to generate a two-dimensionally transformed vector set. A two-dimensional conversion device characterized by the above. 46. The two-dimensional conversion apparatus according to claim 45, wherein the set of the first vector, the second vector, the third vector, and the fourth vector is an M × 1 vector consisting of M elements. 47. The processing time of the first processor for generating the vectors of the first set and the fourth set is the processing time of the second processor for generating the set of transformed vectors. 46. The two-dimensional conversion device according to claim 45, which is not significantly larger. 48. The two-dimensional conversion device according to claim 47, wherein the first processing device comprises a network of adder circuit arrays. 49. The two-dimensional conversion apparatus according to claim 48, wherein the second processing device algebraically integrates the second parts of the two one-dimensional conversions. 50. The two-dimensional conversion apparatus according to claim 49, wherein the one-dimensional conversion comprises a generalized Cheng transform that approximates a discrete cosine transform. 51. Converting means for receiving an input pixel having a certain bit width and converting the input pixel in the horizontal direction or the vertical direction by using only the adder circuit array means in a time division configuration; Transferring memory means for rotating vertically converted pixels vertically or horizontally, means for the converting means to receive vertical or horizontal pixels, and vertical or horizontal pixels for the adder circuit array Means for transforming vertically or horizontally using means, and compression for receiving the transformed pixels and performing a single multiplication function on the transformed pixels to represent the input pixels. A device for compressing still image data, comprising a single multiplication circuit means for providing compressed pixel data. 52. A step of receiving an input pixel having a certain bit width in a time division configuration and converting the input pixel in a horizontal direction or a vertical direction using only an adder circuit array means; and the step of converting the converted pixel in a vertical direction. Or horizontally rotating, converting vertical or horizontal pixels using only the adder circuit array means, and performing a single multiplication function on the converted pixels to input the input. A method of compressing still image data, comprising: providing compressed pixel data representing a pixel. 53. Means for receiving input pixel data representing an image and generalized Chien conversion means for compressing said pixel data, said generalized Chien conversion means adding said image data. GCT adder circuit means for converting the pixel converted in the horizontal direction to the horizontal direction and a memory means for transfer for vertically rotating the pixel converted in the horizontal direction. The GCT adder circuit means uses only the adder circuit. Means for vertically converting vertical pixels into a vertical direction, and multiplication circuit means for performing a multiplication function on the converted vertical pixels to provide compressed pixel data representing the input pixels. The GCT adder circuit means includes a first GCT adder circuit network stage for converting the first half of the horizontal and vertical conversions and a second half of the horizontal and vertical conversions. A system for compressing still image data, comprising a second GCT adder circuit network stage for converting. 54. The still image data compression system of claim 53, wherein the first and second GCT summing circuit network stages transform the pixels horizontally and vertically in a time division configuration. 55. The still image data compression system of claim 54, wherein the multiplication circuit means includes zigzag ordering means. 56. A still image data compression system according to claim 55, wherein the multiplication circuit means includes rounding means. 57. A still image data compression system as set forth in claim 56, wherein the multiplication circuit means includes multiplication table means.