JPH0746136A - Acoustic or picture conversion processor, acoustic or picture data processor, acoustic or picture data processing method, arithmetic processor, and data processor - Google Patents

Abstract

PURPOSE:To increase the throughput of an acoustic or picture compression system. CONSTITUTION:The same devices as in a standard system are used for devices up to an NXN division unit 20 and devices following a unit 40, in a transformed image compression system. Outputs 25a and 25b of the NXN division unit 20 consist of NXN picture element blocks. The pair of adjacent picture element blocks 25a and 25b are coupled into a double vector 29 by a double vector generating unit 27, and this double vector 29 is transformed by a two-dimensional transformation unit 30 which adopts addition, subtraction, and shift to execute the GCU transformation. An output double vector 31 is decomposed to a standard numerical form by a number extracting unit 33 to obtain transformation coefficients 35. The transformation coefficients 35 are quantized by the quantizing unit 40 and are encoded by an encoder 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for compressing image data, and an apparatus and method for improving the throughput of a processor involving addition, subtraction and shift operations.

[0002]

BACKGROUND OF THE INVENTION This application is directed to U.S. Pat. No. 5,129,015, issued Jul. 7, 1992, which is hereby incorporated by reference.
Co-pending U.S. patent application Ser. No. 07 / 743,517, dated 199
Aug. 9, 1st, Title of the Invention: Apparatus and method for compressing still images) and US patent application Ser. No. 07/7
No. 43,517, a continuation-in-part application of pending US patent application Ser. No. 07 / 811,468 (receipt date: 19
December 19, 1991, Title of Invention: Apparatus and method for compressing still images). The details of these related patent applications are incorporated herein by reference.

However, aspects of the invention are not limited to such image compression systems. Rather, the present invention is directed to apparatus and methods for improving the throughput of general data signal processing systems, such as acoustic data compression systems.

In signal processing, it is often necessary to perform time-consuming calculations. Today's general purpose processors (eg Motorola 68020) typically have a 32-bit arithmetic data path, which is unnecessarily high for critical applications such as audio or image processing in connection with the present invention. It is precision. In an acoustic or image processing environment,
It would be desirable to be faster with less precision.

For example, the generalized Chen transform (Generalized Ch) described in the related patents and patent applications mentioned above.
en Transform, GCT) would use only add, subtract and shift operations, and finally add to approximate the discrete cosine transform (DCT). 32-bit precision is not required to obtain acceptable image quality. Therefore, the data of two 16-bit words are combined into one 32-bit word, and the two 16-bit words are processed in parallel by a 32-bit processor to extract the output data of the two 16-bit words. As a result, the throughput of GCT can be dramatically improved. According to this process, a single instruction, single data (SISD) machine can be used for single instruction, multiple data (SIM
D) It can be operated as a machine.

[0006]

SUMMARY OF THE INVENTION One object of the present invention is to provide an apparatus and method for compressing data, especially still image data.

It is a particular object of the present invention to provide an apparatus and method for compressing audio or still images and increasing throughput.

Another object of the present invention is to provide a method for improving throughput by operating a single instruction / single data machine as a single instruction / multiple data machine.

[0009]

According to the present invention, there is provided an apparatus and method for increasing the throughput of a data processing system, such as an audio or image compression system.
In this device or method, two sets of numbers are added or subtracted by combining these numbers into a "double vector" pair, adding or subtracting this double vector pair, and the resulting double vector Can be accomplished in parallel by separating and separating the values to obtain a value representing the result of the addition or subtraction on the original numbers. Similarly, multiple numbers left-shifted by combining them into a double vector, left-shifting this double vector, and retrieving multiple numbers that represent the left-shifted value of the original number. Can be accomplished.

[0010]

According to the apparatus or method of the present invention as described above,
By performing a linear transformation such as a generalized Cheng transformation using a double vector with addition, subtraction and shift, the calculation speed can be significantly increased.

For example, in the case of using a single instruction / single data general-purpose processor having a 32-bit arithmetic data path, two 16-bit word data are combined into one 32-bit word and two A 16-bit word can be processed in parallel by a processor and two 16-bit words of output data can be extracted to operate a single instruction / single data machine as a single instruction / multiple data machine. Therefore, the throughput of GCT or the like can be dramatically increased.

The features and advantages of the present invention other than those described above will be apparent from the following description.

[0013]

Before describing the embodiments of the present invention in detail, the related patents and related patent applications will be briefly described. However, as pointed out above, the present invention is not limited to such compression systems. Rather, the present invention reduces the number of "double vectors" by combining several input data quantities.
r) is obtained, the output double vector is obtained by performing an operation on the input double vector by the processor, and some output data amounts are extracted from the output double vector, and the number of output double vectors is Methods and apparatus are provided that are less than the number of quantities.

First, the transformed image compression (Transform Image)
(Compression). This conversion image compression is
The image is compressed by converting the values of the set of neighboring pixels into a set of transform coefficients. The advantage is that the correlation of the transform coefficients of the values tends to be smaller than the correlation of the corresponding pixel values.

Neighboring pixels in the image are usually of similar value, ie the "energy" distribution of the pixels is relatively uniform. This transform gives good energy compression when the coefficients of a transform are highly variable, ie uncorrelated. If the reproduced signal quality is the same,
Lossy quantization of the transform coefficients yields much better compression than lossy quantization of the original data.
(Alternatively, lossy quantization of transform coefficients can provide better reproduced signal quality than lossy quantization of original data if the amount of compression is the same.) A system for this transform image compression will be described. An example of a typical converted image compression system is shown in FIG. (Note that the JPEG still image compression standard baseline system is such a system.) In FIG. 6, the original color image 8 is converted by the color conversion unit 10 into the opposite color space such as YC _R C _B. To be done. Through the other parts of the system, only one color component is processed at a time. The color-converted image data 15 is
By the NxN division unit 20, the NxN block (J
In the case of PEG, it is divided into 8 × 8 blocks). This N
The opposite color block 25 of xN is converted by the two-dimensional conversion unit 30.

If the two-dimensional conversion can be executed by passing the one-dimensional conversion twice, the amount of calculation can be greatly reduced. In this case, the two-dimensional transformation is called a separable transformation. FIG. 7 shows the circuit elements for the calculation of this type of transformation. First, the 1D conversion unit 32 performs one-dimensional conversion on N rows of 1 × N image elements 25. The resulting conversion coefficient 31 is replaced by the replacement unit 34, and another N row of 1 × N coefficients 33 is converted by the 1D conversion unit 36 to obtain a set of two-dimensional conversion coefficients 35 subjected to two-dimensional conversion. To be

As shown in FIG. 6, the block of transform coefficients 35 is quantized in a quantization unit 40. The quantization is obtained by dividing each coefficient 35 by a known number. This reduces the number of bits required to encode the quantized coefficient 45. (During expansion, quantization is performed in the opposite direction by multiplying the coefficient by the same known number.) Note that the quantization is "lossy" due to the rounding error caused by integer division.
It should be noted that the exact transform value may not be restored after quantization, since it is (lossy). The quantized coefficient 45 is a lossless encoder 50,
It is encoded without loss by some kind of algorithm such as Huffman encoding to obtain a set of encoded transform coefficients 55.

When this system is realized by software using a general-purpose processor, the slowest part of the system is the conversion itself. To get good energy compression,
Complex transformations such as the Discrete Cosine Transform (DCT) are required. Arithmetic calculations are very processor time intensive. Since shifts and additions can be performed much faster than divisions, slower computations, especially multiplications, can be replaced by additions, subtractions and shifts to speed up computations.

The generalized Cheng transform, disclosed in US Pat. No. 5,129,015 and incorporated herein by reference, uses only addition and shifting in the transform. Since all multiplications required for the transformation are merged into the quantization multiplication, the quantization speed does not decrease, but the conversion speed increases significantly.

The present invention takes advantage of the significant addition and shift of transformations such as GCTs by transforming the two blocks of elements in parallel using one conventional general purpose processor.

One aspect of the present invention will be described below. Signal processing often requires time-consuming arithmetic operations. Today's general-purpose processors typically have a 32-bit arithmetic data path, which is more accurate than necessary for important applications such as audio or image processing in connection with the present invention. In such an acoustic or image processing environment, it may be desirable to be faster, though less accurate.

In the present invention, a plurality of numbers are converted into one 32-bit "
The above objective is achieved by packing (packing) into a double vector.

For example, 4 pieces of 8-bit data or 3 pieces
10-bit data (2 bits are reserved), or 2
16-bit data can be packed into a 32-bit double vector. The left shift results in a loss of precision, so the conversion process is preferably designed to limit the number of significant bits in each element to, for example, 14 bits, and a 32-bit double vector consists of two 16-bit numbers.

A preferred embodiment of the present invention using the double vector method for speeding up two-dimensional conversion will now be described with reference to FIG. In the transformed image compression system shown here, the devices up to the N × N division unit 20 and the devices after the quantization unit 40 are the same as those of the standard compression system of FIG.

As shown in FIG. 1, the outputs 25a and 25b of the NxN division unit 20 consist of NxN pixel blocks. A pair of adjacent pixel blocks 25a and 25b are combined in a double vector generation unit 27 to generate a double vector 29. This double vector 29 is transformed in a two-dimensional transformation unit 30 which performs GCT transformation using addition, subtraction and shift, as described in the aforementioned US patent. The output double vector 31 is decomposed by the number extraction unit 33 into a standard numerical form, whereby the conversion coefficient 35 is obtained. The transform coefficient 35 is quantized as described above and then encoded.

One object of the present invention is to perform a linear conversion such as the 8-element GCT conversion units 32 and 36 shown in FIG. 7 in a 32-bit type such as a Motorola MC68020.
It should be done at high speed on the processor. In one preferred embodiment, two standard numbers are combined in a 32-bit register. Thus, a SIMD (single instruction, single data) processor is effectively treated as a SIMD (single instruction, multiple data) machine. The linear transformation is
It consists of addition, subtraction and constant multiplication. This multiplication is addition,
Replaced by some combination of subtraction, shift left and shift right. Table lookups and multiplications are avoided.

Note that addition and subtraction move the significant bit to the left. For example, the effective bit is 6
Adding two numbers of bits may yield a number with 7 significant bits. For example

[0028]

[Equation 1]

Since the maximum is known at any point in the calculation of the transform, the design limits the maximum to prevent overflow. However, a negative sign bit may move to the lower bits of the upper number of the double vector. Depending on the size of the transform and the accuracy required, a right shift may be required for "re-center" of the data. Therefore,
Instead of multiplying by 5, it may be desirable to multiply the initial value by 2.5 and the "partner" value by 2.0 (these two values are, after some division, If you know that will eventually be multiplied).

According to the invention, the N-bit number A and the M-bit number B are combined to obtain an (N + M) -bit "double vector" number C. The relationship between this double vector C and the numbers of its elements, A and B, is expressed by the equation C = [A, B]. When the number of double vectors is obtained, the number of double vectors is subjected to a series of operations (most of which are simple arithmetic operations) to obtain a double vector output. And this double vector output is decomposed,
The number of elements is obtained. For example, the following addition X = A1 + A2 and Y = B1 + B2 produces the following double vectors C1 = [A1, B2] and C2 = [A2, B2], the addition of these two double vectors, ie Z = C1 + C2 = [X, Y], and the result X and Y from the double vector Z
Can be executed simultaneously by extracting Subtraction is performed in a similar way.

Similarly, two (mono vector, monovect
or) The n-bit left shifts of the numbers A and B define the following double vector C = [A, B] and perform a left shift on this C to output vector C ′ C ′ = C << n ("<<n" represents an n-bit left shift),
The right vector is padded with 0s and the double vector C'is decomposed into A'and B '(where C' = [A ', B'], A '= A << n,
By executing B '= B << n), it is possible to execute simultaneously.

The first double vector generation method is called a linear method. According to this linear method, the double vector C generated from the m-bit number A and the n-bit number B is defined by C = [A, B] = A * 2 ⁿ + B. The extraction of A and B from C is given by B = C-((C >> n) * ²ⁿ ) and A = (CB) / ²ⁿ . Here, ">>n" means shift n bits to the right and send the sign bit to the left. In the preferred embodiment, A and B are signed two's complement integers, C is a 32-bit double vector, and C = [A, B] = A * 2 ¹⁶ + B. The extraction is then given by B = C-((C >> 16) * 2 ¹⁶ and A = (C−B) / 2 ¹⁶ (or A = C >> 16, other equivalent arithmetic operations and booleans. It is given as a combination of operations.)
For example, when A = 0x0041 = 65 B = 0xFFF7 = -9, C = [A, B] = (65x2 ¹⁶ ) -9 = 0x0040 FFF7. Here, the number with 0x prefix is 16
It is expressed in hex.

Using the linear method, two 16-bit numbers 0
x0041 and 0x0041 and two 16-bit numbers 0x
To combine the additions of FF7 and 0xFFF7, add two 32-bit double vectors, ie

[0034]

[Equation 2]

The following may be executed.

By decomposing the sum thus obtained by the above method, the following sums 0x0081 = 129 and 0xFFEE = -18 are obtained.

Another method of generating a double vector is called a pack method. According to the pack method, (m + n)
From the m-bit number A and the n-bit number B, the bit double vector C is C = (A << n) || B where "||" means a logical OR operation.

Is generated by Therefore, A is placed in the high order part of C and B is placed in the least significant n bits of C. The inverse operations are A = C >> n and B = C && ( ^2n- 1). Here, "&&" means a logical AND operation.
In particular, in the preferred embodiment, A and B are 16-bit numbers, so C = (A << 16) || B, and its inverse operation is A = C >> 16 and B = C && FFFF. For example, A = 0x0041, B = 0xFFF7
Then, C = 0x0041 FFF7. Although the above A, B, and C are considered as numbers, the linear method and the pack method can be applied to an array or a matrix.

By the pack method, two 16-bit numbers 0
The addition of x0041 and 0x0041 and the addition of two 16-bit numbers 0xFF7 and 0xFF7 are two 32-bit double vectors 0x0041 FFF7 and 0x.
Converted to addition of FFF7, 0x0083
FFEE is obtained and decomposed into 0x0083 = 1
A sum of 31 and 0xFFEE = -18 is obtained. This example shows that the packed method sometimes causes errors in the least significant bits of the number placed in the upper part of the double vector. The linear method does not have this problem. However, the pack method is faster than the linear method because shifts, ORs, and ANDs are faster than multiplications and additions. FIG. 2 shows a comparison result of adding pairs of 4-bit numbers in an 8-bit double vector using the linear method and the pack method. Addition of the first two sets [(3 + 2) and (1 + 1), [(-3 + 2)
And (1 + 1)], correct results are obtained by both the linear method and the packed method. However, the last two sets of addition [(3 + 2) and (1 + (-1)), (3 + 2) and (1 + (-1))]
, The result of the linear method is correct, but the result of the packed method is incorrect. In general, negative numbers in the lower part of the double vector cause errors in the least significant bits of the higher part of the double vector. Usually, the number stored in the double vector is large, so such an error does not significantly affect the calculation. Another way is to adjust the numbers so that there is an extra digit to the right (to the right of the decimal point).

An outline of a circuit for performing addition or subtraction of double vectors is shown in FIG. Storage register array 80
Stores a 32-bit double vector generated by the linear method or the pack method. A 32-bit double vector pair selected from register array 80 depending on the nature of the calculation is sent to arithmetic logic unit (ALU) 82 on 32-bit lines 84 and 86. ALU82 is, for example, Motorola MC68020, or Intel 80
386 or 80486, or Sun SPARC family of processors. The output of the ALU 82 is a 64-bit number, which is sent on a 64-bit line 88 to one selected register in the register array 80. The number stored in this register is arranged into a 32-bit number (here, a double vector) by discarding the upper 32 bits.

The results of the left shift by the linear method and the pack method are shown in comparison with each other in FIG. The first example [(3 << 1) and (1 <<
1)], when the number in the lower part of the double vector is negative, the correct result can be obtained by both the linear method and the packed method. However, the second example [(3 << 1) and (-1 << 1)]
As described above, when the number in the lower part of the double vector is negative, an error occurs in the least significant bit of the number in the upper part of the double vector regardless of whether the linear method or the pack method is used. It should be noted that the left shift may invert the sine of the element of the double vector, as may the case of inverting the sine of the normal two's complement binary number. Typically,
The number stored in the m-bit register is a number of (m−k) bits, and the number of bits left-shifted does not exceed k bits in order to prevent overflow.

A right shift for a double vector is different than a left shift. This is because the number of sign bits in the lower part of the double vector must be preserved when the right shift is performed. Next two 16
Double vector C = 0 generated by the pack method from the number of bits A = 0x0040 = 64 B = 0xFFF7 = -9
Suppose you want to right shift x0040 FFF7 by 2 bits. Normal right-shifting of 32-bit data gives C >> 2 = 0x0010 3FFD, and the number of elements by the pack method is 16 and +16,38.
Although it is 1, if the number of elements is directly shifted right by 2 bits, 16 and -3 are obtained. Such discrepancies in signatures are unacceptable.

As shown in FIG. 5, the correct right shift of the double vector preserves the sign bit of each number element of the double vector by copying the sign bit of each number element. In this example, the number of high order bits (including the sign bit) in the lower part of the double vector must remain 1, and the correct result is 0x0010 FF.
It is FD.

For example, using the MC68000 instruction set, the following command sequence is required to perform a right shift of a double vector.

Asrw 2, C; swap C, a
srw 2, C swap C where the swap C command swaps the upper 16 bits and the lower 16 bits of the 32-bit double vector C. (Asrw 2, C)
The command is a 2-bit arithmetic right shift to the lower 16 bits of C. This sequence of operations preserves the sign of the lower 16 bits of the double vector. When a plurality of right shifts are performed on one double vector, only the first swap of each asrw / swap / asrw / swap sequence needs to be performed, and the last swap is required because the right shift is an odd number. This is the case when it is performed once.

A specific example will be described. Using the double vector method of the present invention, the linear transformation

[0047]

[Equation 3]

Is converted to

[0049]

[Equation 4]

Can be combined with and therefore the double vector p
= [X1, x2], q = [y1, y2], and calculate

[0051]

[Equation 5]

And p '= [x1', x2 '], q'
= [Y1 ', y2'], the solution x1 ', x2',
Extract y1 'and y2'.

For example, consider the following linear transformation matrix.

[0054]

[Equation 6]

Since the elements of the matrix M are simple rational numbers,
The matrix operation M on (x1, y1) ^T can be performed by a combination of addition, subtraction, left shift and right shift. That is,

[0056]

[Equation 7]

This transformation M is converted into a 1 × 2 matrix (x1, y1) ^T ,
When the calculation is performed at (x2, y2) ^T , the calculation time can be reduced by performing the following calculation and extracting several components of p'and q '.

[0058]

[Equation 8]

It should be noted that during double vector calculation, addressing of double vector components is not required until the final stage where the number of components is extracted. Each of the two components of ((p ', q') ^T includes a right shift once, but the value right-shifted is added to the value not right-shifted, so swap
Is not omitted).

Now, the use of the present invention for the conversion image coding will be described. Many useful transformations require irrational multiplication and cannot be decomposed into additions, subtractions and shifts.
However, G executed by the conversion units 32 and 36 of FIG.
Since the CT transform can be factored, these irrational number multiplications can be merged into the quantization operation in the quantization unit 40. This multiplication does not involve any additional computation. For N-dimensional transforms, these multiplications can coalesce, so their cost is 1 instead of N per point. Other components in the transformation matrix can be replaced by rational numbers without compromising the orthogonality of the transformation. As useful transforms having this property, there are a fast Hartley transform, a discrete sine transform, and a discrete cosine transform.

"JPEG" (Joint Photohraphic Ex
In the case of an important image compression standard known as perts Group), the values shown in Table 1 were used in place of the components of the transform matrix, as described in the above-referenced U.S. patents, to allow GCT transformation to It is possible to obtain an approximation of the discrete cosine transform, which is sufficient for medical applications.

[0062]

[Table 1]

Therefore, a useful transformation can be executed using a simple rational number. Since the multiplication can be implemented as addition and shift, the present invention can be applied. For example, GCT
Multiplication by 1 / sqr2 (= ~ 0.70711) required in ((sqr2) means the square root of 2 and "= ~"
Means approximately equal. ) It can be done by a table search, but using shift and addition, it can be done by 0.70711 * A = ~ ((A + A >>) >> 1) * (1 + >> 2) + A >> 4.

Table 2 lists the basic calculations and their costs for each of the standard method and the method of the present invention.

[0065]

[Table 2]

In accordance with the preferred embodiment of the present invention, for 32-bit double vectors, a number of additions, subtractions and left shifts of 16 bits or less is twice the throughput of standard addition, subtraction and left shifts. Done in. Shifting a double vector to the right requires one or more more operations than a normal number.

Double vector table lookup and multiplication is not used in the preferred embodiment of the present invention. If you want to multiply the double vector and search the table,
It takes the number of components of the double vector, operates on this number of components, and finally puts the number back into the double vector for further processing. (Note that a very large table (2 ³²
Entry) will be needed. Also, since the multiplication of two 16-bit numbers produces a result with 32 significant bits, direct multiplication of double vectors destroys the data. ) As shown in Table 3, the method of the present invention halves the number of additions, subtractions and left shifts for the GCT transform on an 8x8 pixel block.

[0068]

[Table 3]

In the preferred embodiment for the MC68020,
The pack method is used for the forward conversion process, and the linear method is used for the reverse conversion process. In the forward direction conversion operation, the 8-bit pixel component is converted into an 11-bit coefficient, so the error in the least significant digit has a magnitude of (1/2048). However, in the backward conversion operation, the 11-bit pixel component is converted into an 8-bit coefficient, so the error in the least significant digit has a magnitude of 1/256. Therefore, the accuracy of the forward conversion may be sacrificed to increase speed.

The error that occurs when performing the forward and backward conversions can be decomposed into an error that naturally occurs due to the constraint of the precision of integer arithmetic, a quantization error, and the above-mentioned error related to the pack operation. In the case of typical quantization, the magnitude of the quantization error is much larger than the other errors. Therefore, in practice, the method and apparatus described above prove to be effective.

After conversion of the double vector pixel data by the conversion units 32 and 35, the data is converted back to a standard number for processing by other parts of the compression system.

The above description of the preferred embodiments is merely for the purpose of explaining the present invention and is not intended to limit the present invention thereto, and many modifications and variations are made in light of the above embodiments. Is possible. Further, the present invention is based on JPEG (Joint Photograph Experts Group).
Is compatible with existing standards such as. The present invention can also be applied to signed binary numbers. The foregoing preferred embodiments have been chosen and described in order to explain the principles of the invention and its application, and those skilled in the art may utilize various modifications of the invention and its various embodiments to suit its particular application. To do so. Various other modifications are possible. For example, much of the above description was directed to calculations on double vectors, but it is possible to create vectors with more than two numbers.

(Note that the term "double vector" is
It is used for convenience. ) For example, DEC Alpha
Since the a series has 64-bit arithmetic operations, a vector of four numbers according to the present invention can be used. Although the invention has been described in terms of transforms for data compression, the invention is also useful for other types of transforms, such as spectral analysis. Although the invention has been described in terms of transformations, the invention can be used with other types of arithmetic operations. Although the example of the combination of the arithmetic operation and the Boolean operation for the linear method and the pack method has been shown, it may be replaced with a combination of other equivalent operations. Although two double vector methods have been detailed, other related methods can also be used.

[0074]

According to the present invention, in a data processing system such as an audio or image compression system, the addition or subtraction of two sets of numbers combines these numbers into a "double vector" pair, This is accomplished in parallel by adding or subtracting pairs of double vectors and separating the resulting double vectors to obtain a value representing the result of the addition or subtraction on the original numbers. Similarly, multiple numbers left-shifted by combining them into a double vector, left-shifting this double vector, and retrieving multiple numbers that represent the left-shifted value of the original number. Can be accomplished. For example, in the case of using a single instruction / single data general-purpose processor having a 32-bit arithmetic data path, two 16-bit word data are combined into one 32-bit word and two 16-bit words are combined. By processing words in parallel in a processor and extracting output data of two 16-bit words, a single instruction / single data machine can be operated as a single instruction / multiple data machine. Can be significantly increased. Therefore, the throughput of processing such as GCT for an audio or image compression system can be dramatically increased.

[Brief description of drawings]

FIG. 1 shows a block diagram of an image compression apparatus according to a preferred embodiment of the present invention.

FIG. 2 shows comparison results of addition using the linear method and the pack method according to the present invention.

FIG. 3 shows the results of left shift using the linear method and the pack method according to the present invention in contrast.

FIG. 4 shows an example of a circuit configuration for performing addition or subtraction of double vectors according to the present invention.

FIG. 5 shows an example of a right shift operation according to the present invention.

FIG. 6 shows a block diagram of the elements of a standard compressor.

FIG. 7 shows a block diagram of the elements of a separable 2D conversion unit.

[Explanation of symbols]

 8 original color image 10 color conversion unit 20 NxN division unit 27 double vector generation unit 29 double vector 30 two-dimensional (2D) conversion unit 32 one-dimensional (1D) conversion unit 33 number extraction unit 35 conversion coefficient 34 substitution unit 36 one-dimensional ( 1D) Transform unit 40 Quantization unit 50 Lossless encoder 55 Coding transform coefficient 80 Storage register array 82 Arithmetic logic unit (ALU) 84,86 32-bit line 88 64-bit line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04N 1/41 C 9070-5C B 9070-5C

Claims (26)

[Claims] 1. A first, second, and third register means having a high-order portion and a low-order portion, respectively, and the first and second plural-bit audio or image data numbers are combined to form the first register means. And means for entering into the second register means and for combining third and fourth sound or image data numbers into the second register means, wherein the first register means The register means and the second register means have more bit locations than any of the number of data, the first number of data being directed to the lower portion of the first register means, the second data The number is the first
Of said register means to said high order portion, said third data number to said lower portion of said second register means,
The fourth number of data is directed to the high order portion of the second register means, and the contents of the first register means and the second register means are added or subtracted, and the result is the third register result. Means for storing in the register means, a first output number from the lower part of the third register means, and a second from the higher order part of the third register means
And an audio or image conversion processor in an audio or image compression device. 2. The audio or image conversion processor according to claim 1, wherein the lower part and the upper part of the first, second and third register means are respectively the first part of the register means. An audio or image conversion processor, characterized in that it consists of one half and a second half. 3. A sound or image conversion processor according to claim 2, wherein the first, second and third register means have a length of 32 bits. 4. The sound or image conversion processor according to claim 3, wherein the number of data is 16 bits long. 5. The first and second register means and the first and second plural-bit data numbers are combined and placed in the first register means, and the third and fourth plural-bit data numbers are combined. Means for coupling into the second register means and the first register means has a number of bit locations greater than or equal to the sum of the first and second plurality of bit data numbers. The second register means has a number of bit locations that is greater than or equal to the sum of the third and fourth multi-bit data numbers, and has the first and second data numbers and the first and second data numbers. The third and fourth data numbers are set to 1 of the contents of the first and second register means.
A data processing device having means for adding by adding twice. 6. An audio or image compression apparatus comprising an audio or image conversion processor and first and second multi-bit data path register means, wherein the first and second multi-bit audio or image data numbers are:
Filling the first register means having a bit location of a number equal to or more than the sum thereof, and the number of audio or image data of third and fourth plural bits;
The step of filling the second register means having a bit location of a number equal to or more than the sum of them, and the sound or image added by adding the contents of the first and second register means in one addition operation. A method of processing audio or image data, the method comprising: generating data. 7. A function operation f () is performed on a first n-bit number A to obtain a first result X = f (A), and the function operation f () is a second m-bit number. Second run to B
A single-instruction single-data arithmetic processor for obtaining the result Y = f (B) of the above, wherein a double vector generation that creates an (n + m) -bit double vector C from the first number A and the second number B Means, an arithmetic logic unit for performing the function operation f () on the double vector C to obtain an output double vector Z = f (C), extracting a number from the output double vector Z, and the first result X and An arithmetic processor that acts as a single instruction multiple data machine by including means for obtaining the second result Y. 8. The arithmetic processor according to claim 7, wherein the functional operation is a left shift operation. 9. The arithmetic processor according to claim 7, wherein n = 16 and m = 16. 10. The arithmetic processor according to claim 7, wherein the double vector C is generated from the first number A and the second number B according to a relationship of C = A * 2 ⁿ + B. Arithmetic processor. 11. The arithmetic processor according to claim 10, wherein the first result X and the second result Y are Y = Z-((Z >> n) * 2 ⁿ ) and X = (Z−Y). ) / 2 ⁿ an arithmetic processor characterized in that it is taken from the output double vector Z. 12. The arithmetic processor according to claim 7, wherein the double vector C is generated from the first number A and the second number B according to the relation of C = (A << n) || B. Arithmetic processor characterized by that. 13. The arithmetic processor according to claim 12, wherein the first result X and the second result Y are the output double vector according to a relation of Y = Z && (2 ⁿ −1) and X = Z >> n. Arithmetic processor characterized by being taken from Z. 14. The function operation f () is calculated by a first n-bit number A.
The first result X = f (A1, A2) is obtained by executing the first and second n-bit numbers A2, and the function operation f ()
A single-instruction single-data arithmetic processor for performing a second result Y = f (B1, B2) by executing a third m-bit number B1 and a fourth m-bit number B2. From the number A1 of 1 and the third number B1 to the first (n + m)
A double vector generating means for generating a double vector C1 of bits, and generating a double vector C2 of the second (n + m) bits from the second number A2 and the fourth number B2; and the first double vector C1 and the double vector C1. An arithmetic logic unit for performing the function operation f () on the second double vector C2 to obtain an output double vector Z = f (C1, C2); and extracting a number from the output double vector Z and outputting the first result X And an arithmetic processor that acts as a single-instruction multiple-data machine by comprising means for obtaining the second result Y. 15. The arithmetic processor according to claim 14, wherein the functional operation f () is addition. 16. The arithmetic processor according to claim 14, wherein the functional operation f () is a subtraction. 17. The arithmetic processor according to claim 14, wherein n = 16 and m = 16. 18. The arithmetic processor according to claim 14, wherein the first double vector C1 is generated from the first number A1 and the third number B1 according to a relationship of C1 = A1 * 2 ⁿ + B1. An arithmetic processor, wherein the second double vector C2 is generated from the second number A2 and the fourth number B2 according to the relationship of C2 = A2 * 2 ⁿ + B2. 19. The arithmetic processor according to claim 18, wherein the first result X and the second result Y are Y = Z-((Z >> n) * 2 ⁿ ) and X = (Z- Y)
An arithmetic processor characterized in that the output double vector Z is taken out according to the relationship of / 2 ⁿ . 20. The arithmetic processor according to claim 14, wherein the first double vector C1 is derived from the first number A1 and the second number B1 according to the relationship of C1 = (A1 << n) || B1. An arithmetic processor, wherein the second double vector C2 is generated from the second number A2 and the fourth number B2 according to the relationship of C2 = (A2 << n) || B2. 21. The arithmetic processor according to claim 20, wherein the first result X and the second result Y are the output vectors according to the relationship of Y = Z && (2 ⁿ -1) and X = Z >> n. Arithmetic processor characterized by being taken from Z. 22. A first output data array is generated by performing a conversion calculation on a first input data array X1, and a second output data array is calculated by performing a conversion calculation on a second input data array X2. A data processor for generating an input double vector array Y from the first data array X1 and the second data array X2; and a calculation of the conversion for the input double vector array Y,
Means for obtaining an output double vector data array by performing a series of arithmetic operations and Boolean operations; and the first and the second from the output double vector data array.
And a means for retrieving the output data array of the. 23. The data processor of claim 22, wherein the series of operations includes addition, subtraction and shift, but not multiplication. 24. The data processor of claim 23, wherein the transform is a generalized Cheng transform. 25. The data processor according to claim 24, wherein the creating means creates the input double vector Y according to Y = X1 * 2 ⁿ + X2. 26. A data processor according to claim 24, wherein said creating means creates said input double vector Y according to Y = (X1 << n) || X2.