JPH08305684A - Butterfly operation device and inverse discrete cosine transformer - Google Patents

Abstract

PURPOSE: To provide the butterfly operation device and the inverse discrete cosine transformer which perform decoding in a short time. CONSTITUTION: x0 and x1 are dual input data, and y0 and y1 are dual output data, and c00 and c01 are butterfly operation coefficients of x0, and c10 and c11 are those of x1. A zero discrimination part 20 discriminates whether dual input data is zero or not and reports the result to each part. A multiplication input switching part 21 outputs the dual input in the case of x0=0 and x1=0 but sends it to a multiplication part 22 in the other case. An addition input switching part 23 outputs the output of the multiplication part 22 in the case of x0≠0 and x1=0 or x0=0 and x1≠0 and sends it to an addition part 24 in the case of x0≠0 and x1≠0. The multiplication part 22 operates x0×c00→y0 and x0×c01→y1 in the case of x0≠0 and x1=0 and operates x1×c10→y0 and x1×c11→y1 in the case of x0≠0 and x1≠0 and operates x0×c00→d00, x0×c01→d01, x1×c10→d10, and x1×c11→d11 in the other case. The addition part 24 operates d00+d10→y0 and d10+d11→y1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to decoding an image encoded by a method using a discrete cosine transform, and more particularly to a butterfly computing device and an inverse discrete cosine transform device.

[0002]

2. Description of the Related Art When transmitting an image having a huge amount of information, which has been increasing in recent years, various high-efficiency encoding methods have been conventionally proposed as encoding and decoding techniques used for compression for improving the efficiency. Has been done. One example is GIV
JPEG (ISO's Joint Photographic Expert Gr
Oup and CCITT SGVIII international standard encoding system for color still images). Fig. 1 shows a DCT (Discrete Cosine T) in encoding and decoding that employs this method.
ransform (discrete cosine transform) is shown below.

This system will be described below with reference to this figure. In the figure, 100 is an encoder, which comprises a discrete cosine transform unit 101, a quantization unit 102, and an entropy coding unit 103. A decoder 200 includes an entropy decoding unit 201, an inverse quantization unit 202, and an inverse discrete cosine transformation unit 203. Reference numeral 300 is an accumulator having a transmission line or a storage medium. Reference numeral 301 is an encoding table, and 302 is a quantization table. 401
Is an original image, and 402 is a reproduced image.

In the encoder 100, the original image 4 which is an input image
01 is divided into 8 × 8 pixel blocks, and each block is subjected to two-dimensional discrete cosine transform. 8 × by the discrete cosine transform unit 61
Eight (64) pixel data are converted into 8 × 8 (64) conversion coefficients. The 64 transform coefficients are quantized by the quantizer 102.
In the above, using the quantization table 302 that defines the quantization step size for each transform coefficient, linear quantization is performed with a different step size for each transform coefficient position. The quantized transform coefficient is entropy coded by the entropy coding unit 103 using the coding table 301, and coded data is output. At this time, the quantization table 302 and the coding table 301 used in the encoder 100 are used.
Is added as a parameter to the head part of the output code data to be used for decoding. Then, it is sent to the decoder 200 via the electric transmission path and the storage 300.

On the other hand, in the decoder 200, the coded data is entropy-decoded by the entropy decoding unit 201 using the coding table 301. The entropy-decoded data is stored in the quantization table 30 by the inverse quantization unit 202.
Inverse quantization is performed using 2 to obtain the transform coefficient for each 8 × 8 pixel block. Finally, the transform coefficient of the 8 × 8 pixel block is converted into pixel data by the two-dimensional inverse discrete cosine transform in each block in the inverse discrete cosine transform unit 203, and the reproduced image 4
02 is output. However, the above is, for example, CQ
Published by publisher "Interface" December 1991 issue 1
Pages 60 to 182, especially page 163, Nikkei Electronics October 15, 1990 issue (No. 511)
Since this is a so-called well-known technique described on pages 115 to 142, further description is omitted.

By the way, in a natural image as taken by a television camera, a smooth image is often formed by the above encoder and decoder. In that case, the transform coefficient of the discrete cosine transform tends to have a large low frequency component and conversely a small high frequency component. Further, when the quantization is applied, the transform coefficient corresponding to the high frequency component becomes zero, which is invalid. For this reason,
When the discrete cosine transform and the quantization are used, the high frequency component is cut and the amount of information is compressed, which enables efficient coding.

Since it is also related to the gist of the present invention, the reason therefor will be briefly described with reference to the drawings. Figure 2
Is an explanatory diagram therefor. In the figure, (1) indicates 8 × 8 pixels, and the numbers described only in each pixel in the leftmost column are analog values of the luminance of the pixel.
The description of the luminance is omitted for the other columns.
Now, the leftmost luminance is quantized. To make it easy to understand, rounding off the numbers after the decimal point gives the values shown in (2) of this figure. If this is graphed by taking the luminance in the horizontal direction, it becomes (3) in this figure. By the way, although the order of description may be reversed, image data has a strong correlation in brightness and color with pixels that are adjacent to each other in the case of a still image, and in the case of a moving image, it is even more temporally correlated. It is characterized by a strong correlation in brightness and color with the preceding and following pixels. To explain the reason for this by focusing on still images, firstly, each pixel is sufficiently small compared to the display surface or paper, and by extension is also small compared to the figure on the display surface or paper. , If one pixel occupies a part of a figure on the display surface, then there is a high probability that adjacent pixels also occupy a part of the vicinity of the same figure. Pay attention to areas where there are changes in brightness and color, and be relatively insensitive to other areas.

According to the above. Now, returning to the discussion, (3) in this figure has almost the same brightness. This is divided into the average value and the part that changes, as shown in (4) of this figure.
Is. Further, this changing portion is divided into the average value changing portion and (5) in this figure. In this way, the change in the luminance of the eight pixels is also divided into two relatively large average values and one small changing portion, and the other changing components are zero. The above is only for the leftmost column of 8 × 8 pixels, but even if 8 columns are taken and two-dimensionally changed, the same is true because the correlation between adjacent pixels is high. Become. (Note that in this case, a method usually called zigzag scanning is adopted, and
In the vertical direction, a one-dimensional ordering is done from low components to high components. ) Then, in actual encoding and decoding, mathematical processing such as discrete cosine transform is performed against the background of the above facts and principles. For this, for example, the above-mentioned "interface" (particularly 147 Since this is a well-known technique described in the vicinity of the page and FIG. 25, etc., which is the premise of the invention, a general description of this is omitted.

Now, returning to the original discrete cosine transform again, at this time,

[0010]

[Equation 1]

(However, from the second time onward, it will be referred to as "Equation 1" because of its complexity prevention and self-evidentness. The same applies to other mathematical expressions.)

[0012]

[Equation 2]

And

[0014]

(Equation 3)

Can be decomposed into the one-dimensional inverse discrete cosine transform shown in
Moreover, the amount of calculation is reduced. This is the one-dimensional inverse discrete cosine transform of the above “equation 2” is applied to all the columns of horizontal address v in the transform coefficient block, and the result is returned to the column of the same horizontal address v. Is to perform the one-dimensional inverse discrete cosine transform of "Equation 3" on the row of the vertical address u and return the result to the row of the same vertical address u. In the above three expressions, "f" is, for example, color data, and "F"
Is frequency data, and “C” is a coefficient for butterfly calculation.

Next, the Discrete Cosine Transform / Inverse Discrete Cosine Transform itself, there are some fast algorithms. As one of them, an algorithm which improves the fast Fourier transform (FFT) used for both of the above-mentioned transforms and has a smaller amount of calculation and higher speed is disclosed (for example, Document 1: W). .Chen, C.
H. Smith, and SCFralick, "A Fast Computational Al
gorithm for the Discrete Cosine Transform ", IEEE T
ransactions on Communications, Vol.COM-25, No.9, Se
p 1977, pp.1004-1009). A specific example of this algorithm will be shown later.

By the way, the algorithm described in the above-mentioned document 1 and other considerable algorithms are the same as the fast Fourier transform, and the butterfly operation (butterfly co) shown in FIG.
mputation) is the basis. Here, the butterfly operation is the DFT of an even-numbered term in the FFT operation.
It is based on the idea that the operation of adding the product of the odd-numbered term DFT and the twiddle factor is performed step by step. However, the butterfly operation itself is also described, for example, in "Electronic Communication Handbook (published in 1985)", edited by The Institute of Electronics and Communication Engineers, pp. 265, 266, and in the above-mentioned Nikkei Electronics, page 132, and the like. Since this is a well-known technique that is premised, a general description of itself is omitted.
By the way, in FIG. 3, the symbols attached to the arrows are butterfly operation coefficients when making a linear combination of butterfly operations. Also, in this figure, the white circles are nodes, the arrows flow data from the node at the start point along the arrow, multiply by the butterfly operation coefficient attached to the arrow, and join at the node at the end of the arrow. It is shown that the butterfly operation is performed by adding the data to be added.

FIG. 4 shows

[0019]

[Equation 4]

The one-dimensional inverse discrete cosine transform shown in FIG. It shows a data flow when the algorithm such as Chen is used. In this figure, when no arrow is attached, the butterfly operation coefficient is 1, and when a "-" sign is attached to the arrow, the butterfly operation coefficient is "-1". Next, various devices for further shortening the processing time of discrete cosine transform / inverse discrete cosine transform have been disclosed, focusing on this butterfly operation. As an example thereof, a "discrete cosine arithmetic unit" which minimizes the number of arithmetic steps by performing addition and subtraction of two data read at the same time by addition and subtraction means to perform a butterfly operation (JP-A-2-237372).
No.) or the multiplication value is linearly converted so that the output value of the butterfly operation becomes 21/2 times, and the value of the quantization table is multiplied by 2 ^m (where m is the number of linear conversions). There is "a two-dimensional data compression and decoding system using cosine transform and a conversion device used therefor" (Japanese Patent Laid-Open No. 3-273714) for increasing the speed.

In addition to the above, the circuit connection must be switched between the DCT calculation and the inverse DCT calculation, but a device has been devised to substantially eliminate this need (Nikkei Electronics, etc., cited above).

[0022]

However, in the above-mentioned conventional inverse discrete cosine transform device, not only is the result obvious but time-consuming multiplication with "+1" and "-1" is large, and the result is still Since multiplication and addition / subtraction with zero, which is trivial, cannot be avoided, useless calculation occurs when an image coded using the discrete cosine transform is subjected to the inverse discrete cosine transform and decoded. Moreover, not only invalid zero appears in the transform coefficient of the image input due to the inverse discrete cosine transform, but also the proportion of high frequency components becomes smaller as the compression rate of the image information becomes higher. Will appear more frequently. Since no consideration is given to the correlation between the compression rate and the appearance frequency of zero, sufficient performance cannot be obtained in decoding an image with a high compression rate.

The present invention has been made in view of the above problems, and provides an excellent butterfly computing device and inverse discrete cosine transform device capable of expanding a compressed image in a processing time proportional to the amount of information of the compressed image. It was made for the purpose of doing.

[0024]

In order to achieve the above-mentioned object, in the invention of claim 1, the multiplication result and the addition / subtraction result are avoided from being trivially calculated with zero, and it takes time "+".
The multiplication with "1" and "-1" is performed while avoiding the multiplication while paying attention to "+1" and "-1". Specifically, in a butterfly computing device having a dual input line, a dual output line, a multiplying means, and an adding means, it is determined at high speed whether or not both dual input data from the dual input line are zero, and the determination result When the both of the dual input data are zero in response to the determination result of the zero determining means composed of a comparator, an AND circuit, etc. for outputting to each section, the dual input line is connected to the dual output line. If the dual input data is directly used as the dual output data without multiplication, and if it is determined that the dual input data is not output, the dual input line is connected to the multiplying means by, for example, a multiplication input switching means for switching the line, and a normal multiplication mode. When it is determined by the operation of the DCT that the signal is returned to the above, and is designated by the separately inputted multiplication mode designating signal, it is inputted by the operation of the multiplication input switching means. When the product of the non-zero data in the dual input data and the butterfly operation coefficient corresponding to the non-zero data is output, and when switching to the sign operation mode is specified by the above multiplication mode specification signal, If the corresponding butterfly operation coefficient is positive, the multiplication of the butterfly operation coefficient of the value “+1” with the non-zero data is performed, and the sign of the input non-zero data is not inverted, and as a result, at high speed. If the corresponding butterfly operation coefficient is negative, the input operation is changed to multiplication of the butterfly operation coefficient of "-1" and the non-zero data, and "+" of the input non-zero data,
The sign of "-" is inverted, and consequently the multiplying means for outputting at high speed, the output data from the multiplying means and the determination result of the zero determining means are input, and only one of the dual input data is zero. When the determination result is that the other non-zero of the dual input data and the corresponding butterfly operation coefficient are multiplied, the output from the multiplying means is directly connected to the dual output line to obtain dual output data. When the determination result is that both of the dual input data are non-zero, the addition input switching means for outputting the input from the multiplication means to the addition means and the multiplication means input from the addition input switching means The present invention is characterized in that it has an addition means for adding four output data in pairs and outputting them as dual output data.

According to the second aspect of the present invention, in the inverse discrete cosine transform device provided with the butterfly computing device having the dual input line, the dual output line, the multiplying means and the adding means, the butterfly computing device is a dual input from the dual input line. For both input data, it is judged whether or not it is zero, and a zero judgment means for outputting the judgment result to each part, and when both of the dual input data are zero in response to the judgment result of the zero judgment means, the dual input Connect the line to the dual output line and use the dual input data as it is as the dual output data, and if it is determined that it is not, multiply input switching means for connecting the dual input line to the multiplying means and return to the normal multiplying mode. Is specified by a separately inputted multiplication mode designating signal, the non-zero data and the non-zero data among the dual input data inputted by the operation of the multiplication input switching means are inputted. Output as a product of the butterfly operation coefficient corresponding to the non-zero data, and if the multiplication mode specification signal specified above switches to the sign operation mode, the butterfly operation coefficient corresponding to the non-zero data must be positive. If the sign of the non-zero data is output as it is without being inverted, and if the corresponding butterfly operation coefficient is negative, the sign of "+" or "-" of the non-zero data is inverted and output, When the output data from the multiplication means and the determination result of the zero determination means are input and the determination result is that only one of the dual input data is zero, the other non-zero of the dual input data and that The output from the multiplication means, which has been multiplied by the corresponding butterfly operation coefficient, is directly connected to the dual output line to form dual output data, and both of the dual input data are non-zero. When there is a determination result, the addition input switching means for outputting the input from the multiplication means to the addition means and the four output data of the multiplication means input from the addition input switching means are paired and added. And adding means for outputting as dual output data, further connected to the dual input line and dual output line, storage means for storing dual input data and dual output data, connected to the multiplication means, Butterfly operation coefficient information generating means for generating a butterfly operation coefficient and a multiplication mode designating signal when the inverse discrete cosine transform control signal is in the butterfly operation mode, and the inverse discrete cosine transform control signal connected to the storage means. Address information for outputting the dual input data and the address for storing the dual output data when the is in the butterfly operation mode. Address information generating means for generating address information,
And a rearrangement unit which is connected to the storage unit and rearranges the data in the storage unit in the bit inversion order when the inverse discrete cosine transform control signal is in the rearrangement mode.

[0026]

With the above structure, in the invention of claim 1,
Now, x0 and x1 are dual input data to the butterfly computing device, y0 and y1 are dual output data from the butterfly computing device, c00 and c01 are butterfly computing coefficients corresponding to the input data x0, and c10 and c11 are corresponding to the input data x1. X0 = 0 and x1
If = 0, no calculation is performed and y0 ← x0 and y1 ← x1. When x0 ≠ 0 and x1 = 0, C00 is “+
1 ”and“ −1 ”, the corresponding multiplication mode designating signal designates the sign operation mode, and y0 ← x0, y0 ← −x
If 0 and C00 is a value other than ± 1, the corresponding multiplication mode designating signal designates the normal multiplication mode, and y0
← x0 × C00, and similarly, the value of C01 is “+1”,
"-1" and "values other than ± 1" respectively yield y1 ← x
0, y1 ← −x0, y1 ← x0 × C01.

When x0 = 0 and x1 ≠ 0, the value of C10 is y0 ← x0, y0 ← −x0, y0 ← x0 by "+1", "-1", and "value other than ± 1", respectively. × C10
And the value of C11 is y + 1 ← x1, y1 ← −x1, y1 depending on “+1”, “−1”, and “value other than ± 1”, respectively.
← Set to x1 × C11. Similarly, when x0 ≠ 0 and x1 ≠ 0, y0 ← x0 × C00 + x1 × C10, y1 ←
Multiplicands x0 and x in x0 × C01 + x1 × C11
Multiply 1 with multipliers C00, C10, C01, C11,
When the value of the multiplier is “+1”, “−1”, or “value other than ± 1”, the sign of the multiplicand is inverted and the multiplication of the multiplicand and the multiplier is performed while the value of the multiplicand is unchanged.

According to the second aspect of the present invention, a set of dual input data and a butterfly operation coefficient corresponding to each dual input data is continuously supplied to the butterfly operation device, thereby performing multidimensional inverse discrete cosine transform. To do. Moreover, at each butterfly operation stage, "+1", "-1"
Avoid multiplication with and arithmetic with zero.

[0029]

EXAMPLES The present invention will be described below based on examples. (First Embodiment) FIG. 5 is a block diagram of an embodiment of the butterfly computing device according to the present invention. In the figure, 10 is a dual input line for inputting dual input data to the butterfly computing device, 16 is a dual output line for outputting dual output data from the butterfly computing device, and 20 is zero for the dual input data. It is a zero determination unit that determines whether it is non-zero,
Reference numeral 22 denotes a multiplication unit for multiplying the dual input data by the butterfly operation coefficient or for performing a sign operation on the dual input data. Reference numeral 21 denotes a connection of the dual input line 10 to the dual output line 16 or an input line 12 to the multiplication unit 22. Is a multiplication input switching unit, 13 is a butterfly operation coefficient input line for inputting the butterfly operation coefficient stored in a ROM (not shown) as a so-called lookup table to the multiplication unit 22, and 17 is illustrated. A multiplication mode designation signal line for inputting the multiplication mode designation signal stored in the ROM, which is not stored in the ROM, to the multiplication unit 22, 24 is an addition unit for adding the output data from the multiplication unit 22, and 23 is a multiplication unit 2
Reference numeral 11 denotes an addition input switching unit that switches the connection of the output line 14 from 2 to the dual output line 16 or the input line 15 to the addition unit 24. Reference numeral 11 denotes the determination result of the zero determination unit 20 and the multiplication input switching unit 2
1 is a zero determination signal line that notifies the multiplication unit 22, the addition input switching unit 23, and the addition unit 24. Here, the contents of the butterfly operation coefficient and the multiplication mode designation signal are 1
It is determined by the dimensional inverse discrete cosine transform algorithm.

The determination of whether the input data is zero by the zero determination unit 20 is made at high speed by checking whether the value of each digit of the data is zero. The judgment table and circuit are shown in Fig. 2.
0 is shown. (1) of the figure shows that 0 is output only when the values of the two digits of X0 or X1 are both 0.
FIG. 2B shows the circuit configuration when both X0 and X1 are 4-bit signals.

Next, the operation of the butterfly computing device constructed as above will be described. Now, let x0 and x1 be dual input data, and y0 and y1 be dual output data. Also,
Let c00 and c01 be butterfly operation coefficients corresponding to the input data x0, and c10 and c11 be butterfly operation coefficients corresponding to the input data x1. Further, 4 bits are assigned to the multiplication mode designating signal, and each butterfly operation coefficient is associated with each bit of the multiplication mode designating signal. Specifically, the butterfly operation coefficient c00 has the first bit counted from the lower order, the butterfly operation coefficient c01 has the second bit counted from the lower order, and the butterfly operation coefficient c10 has the third bit counted from the lower order. The butterfly calculation coefficient c11
The 4th bit counted from the lower order is associated with each other. When the bit of the multiplication mode designating signal is 0, it means the normal multiplication mode, and when the bit of the multiplication mode designating signal is 1, it means the sign operation mode. One of the dual input data is represented by x, and the butterfly operation coefficient corresponding to x is represented by c. When the multiplication mode designating signal corresponding to the butterfly operation coefficient c indicates the normal multiplication mode, that is, when it is 0, the multiplication unit 22 performs multiplication of x × c. When the multiplication mode designating signal corresponding to the butterfly calculation coefficient c indicates the sign calculation mode, that is, when it is 1, the multiplication unit 22 executes the sign calculation sign (x, c). Here, the sign operation sign (x, c) is an operation in which the operation result is x if c is positive, and the operation result is -x if c is negative.

FIG. 6 is a table showing the contents of the operation of the zero decision unit 20. In this table, the determination result of the zero determination unit 20 is represented by a 2-bit binary number. As shown in this table,
The zero determination unit 20 receives the dual input data x0 and x1 from the dual input line 10, and if x0 = 0 and x1 = 0, the determination result is 00, and if x0 ≠ 0 and x1 = 0, the same determination is performed. As a result, 01 is obtained when x0 = 0 and x1 ≠ 0, and 10 is obtained when x0 ≠ 0 and x1 ≠ 0.
1 is sent to the zero determination signal line 11.

Next, the operation of the butterfly operation device when all the multiplication mode designating signals are set to the normal multiplication mode, that is, 0000 will be described. FIG.
The operation of the butterfly computing device when the determination result of the zero determination unit 20 is 00 is shown. As shown in the figure, the multiplication input switching unit 21 receives the determination result of the zero determination unit 20 via the zero determination signal line 11, and connects the dual input line 10 to the dual output line 16. As a result, the dual input data is sent to the dual output line 16 as it is as dual output data.

FIG. 8 is a diagram showing the operation of the butterfly computing device when the determination result of the zero determination unit 20 is 01. As shown in the figure, the multiplication input switching unit 21 is
The determination result of the zero determination unit 20 is received from 1, and the dual input line 10 is connected to the input line 12 to the multiplication unit 22. Multiplier 2
2 receives the input data x0 from the input line 12 to the multiplication unit 22, multiplies y0 ← x0 × c00 and y1 ← x0 × c01, and sends y0 and y1 to the input line 14 to the addition input switching unit. To do. The addition input switching unit 23 receives the determination result of the zero determination unit 20 from the zero determination signal line 11, and the multiplication unit 2
The output line 14 from 2 is connected to the dual output line 16. As a result, the multiplication results of the multiplication unit 22, y0 and y1, are sent to the dual output line 16 as dual output data.

FIG. 9 is a diagram showing the operation of the butterfly computing device when the determination result of the zero determination unit 20 is 10. As shown in the figure, the multiplication input switching unit 21 is
The determination result of the zero determination unit 20 is received from 1, and the dual input line 10 is connected to the input line 12 to the multiplication unit 22. Multiplier 2
2 receives the input data x1 from the input line 12 to the multiplication unit 22, multiplies y0 ← x1 × c10 and y1 ← x1 × c11, and sends y0 and y1 to the input line 14 to the addition input switching unit. To do. The addition input switching unit 23 receives the determination result of the zero determination unit 20 from the zero determination signal line 11, and the multiplication unit 22.
From the output line 14 to the dual output line 16. As a result, the multiplication results of the multiplication unit 22, y0 and y1, are sent to the dual output line 16 as dual output data.

In FIG. 10, the determination result of the zero determination unit 20 is 11
It is a figure which shows operation | movement of the butterfly arithmetic unit at the time of. As shown in the figure, the multiplication input switching unit 21 receives the determination result of the zero determination unit 20 from the zero determination signal line 11, and connects the dual input line 10 to the input line 12 to the multiplication unit 22. The multiplication unit 22 receives the dual input data x0 and x1 from the input line 12 to the multiplication unit 22, and d00 ← x0 × c00, d0
1 ← x0 × c01, d10 ← x1 × c10 and d11 ←
The multiplication of x1 × c11 is performed, and d00, d01, d10 and d11 are sent to the input line 14 to the addition input switching unit 23. The addition input switching unit 23 receives the determination result of the zero determination unit 20 from the zero determination signal line 11, and connects the output line 14 from the multiplication unit 22 to the input line 15 to the addition unit 24. The adder 24 receives d00, d01, d from the input line 15 to the adder.
10 and d11 are received, y0 ← d00 + d10 and y1 ← d10 + d11 are added, and y0 and y1 are sent to the dual output line 16 as dual output data.

Next, the operation of the butterfly computing device when all the multiplication mode designating signals are set to the sign computing mode, that is, 1111 will be described. Figure 11
FIG. 4 is a diagram showing an operation of the butterfly computing device when the determination result of the zero determination unit 20 is 00. As shown in this figure, the same operation as that in FIG. 7 in which all the multiplication mode designating signals are set to the normal multiplication mode is performed.

In FIG. 12, the determination result of the zero determination unit 20 is 01.
It is a figure which shows operation | movement of the butterfly arithmetic unit at the time of. As shown in this figure, the operation is the same as that of FIG. 8 except for the multiplication unit 22. The multiplication unit 22 receives the input data x0 from the input line 12 to the multiplication unit 22, and y0 ← sign (x0, c
00) and the sign of y1 ← sign (x0, c01) (si
gn) The calculation is performed at high speed, and y0 and y1 are sent to the input line 14 to the addition input switching unit.

In FIG. 13, the determination result of the zero determination unit 20 is 10
It is a figure which shows operation | movement of the butterfly arithmetic unit at the time of. As shown in this figure, the operation is the same as that of FIG. 9 except for the multiplication unit 22. The multiplication unit 22 receives the input data x1 from the input line 12 to the multiplication unit 22, and y0 ← sign (x1, c
10) and y1 ← sign (x1, c11) are sign-operated, and y0 and y1 are sent to the input line 14 to the addition input switching unit.

In FIG. 14, the determination result of the zero determination unit 20 is 11
It is a figure which shows operation | movement of the butterfly arithmetic unit at the time of. As shown in the figure, the operation is the same as that of FIG. 10 except for the multiplication unit 22. The multiplication unit 22 receives the dual input data x0 and x1 from the input line 12 to the multiplication unit 22, and d00 ← s
ign (x01, c00), d01 ← sign (x0,
c01), d10 ← sign (x1, c10) and d1
1 ← sign (x11, c11) is sign-operated, and d
00, d01, d10 and d11 are added to the input switching unit 2
3 is sent to the input line 14 to 3.

Based on the above, in the butterfly operation shown in FIG. 3, by changing the multiplication mode designating signal to the sign operation mode, the butterfly operation coefficients c00, c01,
The zero determination unit 20 that can replace the multiplication in the case where c10 and c11 are +1 or -1 with a faster code operation and determines whether the dual input data x0 and x1 is zero or nonzero.
The multiplication input switching unit 21, the multiplication unit 22, the addition input switching unit 23, and the addition unit 2 are provided according to the determination result of the zero determination unit 20.
By controlling the operation of 4, it is possible to avoid multiplication with zero and addition. (Second Embodiment) FIG. 15 is a block diagram of an embodiment of the inverse discrete cosine transform device according to the present invention. In this figure, 40
Is the butterfly computing device of the first embodiment,
In terms of hardware, it consists of an arithmetic unit. 41 is the dual input data to the butterfly computing device 40 and the butterfly computing device 40.
Is a storage unit including a register and a memory for storing the dual output data from. Reference numeral 42 is a butterfly operation coefficient information generating unit that generates a butterfly operation coefficient and a multiplication mode designating signal and sends the butterfly operation coefficient and the multiplication mode designating signal to the multiplication unit 22 of the butterfly computing device 40. Reference numeral 43 is an address information generation unit that causes the storage unit to output dual input data to the butterfly computing device 40 and to store dual output data from the butterfly computing device 40. Then, in order to exert this function, the butterfly operation coefficient information generating unit 42 operates integrally.
Reference numeral 44 is a bit inversion order rearrangement unit that rearranges the data stored in the storage unit 41 in the bit inversion order, and is composed of an arithmetic unit in terms of hardware. Also, 30 and 31 are CD-RO
It is a connection line with M, HD, an external communication circuit line, and the like.

The operation of the inverse discrete cosine transform device of this embodiment constructed as described above will be described below by taking an eight-point one-dimensional inverse discrete cosine transform as an example. FIG. 4 shows the above (Equation 4).
The eight-dimensional one-dimensional inverse discrete cosine transform shown in FIG. It is a figure which shows the data flow at the time of implementing using an algorithm, such as Chen. It is assumed that the storage unit 41 stores the conversion coefficients F (u) at eight points at addresses u = 0 to 7.

FIG. 16 shows the address information generating section 43 and the butterfly operation coefficient information generation shown in FIG. 15 when the inverse discrete cosine transform control signal for executing the algorithm shown in FIG. 4 specifies the butterfly operation mode. 6 is a table showing the contents of the operation of the unit 42. (Therefore, if other algorithms are used, the contents will be different, of course.) The address information generator 43 stores the address u of the dual input / output data of the butterfly computing device 40 in the memory 41.
0 and u1 are given. Based on the address information, the storage unit 41 sends the data F (u0) at the address u0 and the data F (u1) at the address u1 as dual input data to the butterfly computing device 40, and the butterfly computing device 4
The dual output data from 0 is stored in the addresses u0 and u1 respectively. The butterfly operation coefficient information generation unit 42 uses c00, c01, c which are butterfly operation coefficients.
10 and c11 and a multiplication mode designation signal are generated and sent to the multiplication unit 22 of the butterfly computing device 40.

FIG. 17 is a table showing the contents of the operation of the bit inversion order reordering section when the inverse discrete cosine transform control signal specifies the reordering mode. The address of the 8-point data can be represented by a 3-bit binary number (2 ³ = 8). Bit inversion of binary notation address 001 is binary 10
Since it is 0, the data at address 1 and the data at address 4 are exchanged. Since the bit inversion of the binary notation address 011 is 110 in binary, the data of address 3 and the data of address 6 are exchanged. The data of address 0, address 2, address 5 and address 7 do not need to be rearranged because they themselves match the bit inversion result. This is shown on the left side of FIG.

As described above, according to the inverse discrete cosine transform device of this embodiment, by using the butterfly computing device 40 of the first embodiment for the inverse discrete cosine transform, "+1" is set at each butterfly computing stage. , "-1" and addition with zero and multiplication can be avoided. FIG. 18 is a diagram showing the number of calculations for a non-zero conversion coefficient when non-zero conversion coefficients are sequentially packed from the beginning of the storage unit and the rest are zero conversion coefficients. According to this figure, when the number of non-zero conversion coefficients is small, multiplication,
It can be seen that the number of calculations of the sign calculation and the addition is small, and the excellent effect of shortening the processing time of the inverse discrete cosine transform can be obtained.

FIG. 19 is a basic block diagram of the color still image encoding system JPEG as a specific application example of the present invention. Note that, in this figure, the same reference numerals are given to those corresponding to the constituent elements in FIG.
In this application example, the point that the conventional inverse discrete cosine transform unit 66 is replaced with the inverse discrete cosine transform device 60 according to the present invention is shown in FIG.
And different. Therefore, the transform coefficient obtained by the inverse quantization unit 65 is inverse discrete cosine transformed by the inverse discrete cosine transform unit 60 to restore the image.

Although the one-dimensional discrete cosine transform has been described in the present embodiment, the address information generator 43 and the butterfly operation coefficient information generator 42 are equipped with an 8 × 8 register (storage unit). It is needless to say that the operation can be applied to a multidimensional inverse discrete transform that can be decomposed into a one-dimensional inverse discrete transform process by changing the operation of. Although the present invention has been described above based on the two embodiments, it goes without saying that the present invention is not limited to the above embodiments. That is, for example, (1) for the convenience of manufacturing, etc., one of the essential constituents (elements, requirements) of the present invention may be divided into a plurality of parts, conversely, a plurality of parts may be integrated, or these may be combined appropriately. You may.

(2) Even in the MPEG decoding for a moving image, the present invention is used for the first image called I-picca and the first image when the scene changes. (3) Further, in MPEG decoding, a pixel difference is taken in the time direction, which is called a P picture or B picture, and the image is further moved and compensated. In this case, however, the higher order component is 0. Therefore, the difference restoration and the motion compensation restoration may be performed after using the present invention.

Specifically, each image forming a moving image is decoded in the same manner as JPEG. At this time, for each image, only the difference image from the previous image is taken and For example, the same decoding as that of JPEG is performed, or the same decoding as that of JPEG is performed in consideration of compensation (prediction and the like) for the moving direction of the difference.

[0050]

As described above, according to the first aspect of the present invention, since it is possible to quickly determine whether the dual input data is zero or non-zero, zero determining means for determining this is provided. The operations of the multiplying input switching means, the multiplying means, the adding input switching means, and the adding means are controlled according to the determination result.
This avoids multiplication and addition with zero, and also "+
The multiplication with "1" and "-1" can be processed by the code calculation while paying attention to the codes of "+1" and "-1", and the butterfly calculation device is excellent.

According to the second aspect of the present invention, by using the butterfly operation device according to the first aspect of the present invention, it is possible to avoid addition and multiplication with zero in each butterfly operation stage. It becomes a cosine converter. Moreover, in the decoding of the coded image coded by the coding method using the discrete cosine transform, by applying the inverse discrete cosine transform device of the present invention, the processing proportional to the information amount of the compressed image (coded image) It becomes possible to expand (decode) in time.

[Brief description of drawings]

FIG. 1 is a basic system configuration diagram of a conventional color still image coding method JPEG.

FIG. 2 is a diagram for explaining the fact that high frequency components are generally small in image data.

FIG. 3 is a diagram showing a butterfly operation.

FIG. 4 is a diagram showing a data flow in a butterfly operation in the one-dimensional inverse discrete cosine transform.

FIG. 5 is a configuration diagram of an embodiment of a butterfly computing device according to the present invention.

FIG. 6 is a table showing the contents of the operation of the zero determination unit in the above embodiment.

FIG. 7 is a diagram showing an operation of the butterfly computing device when all the multiplication mode designating signals are set to the normal multiplication mode and both of the dual input data are zero in the above embodiment.

FIG. 8 shows the operation of the butterfly computing device when the multiplication mode designating signals are all set to the normal multiplication mode and the first data of the dual input data is non-zero and the second data is zero in the above embodiment. FIG.

FIG. 9 shows the operation of the butterfly computing device when the multiplication mode designating signals are all set to the normal multiplication mode and the first data of the dual input data is zero and the second data is non-zero in the above embodiment. FIG.

FIG. 10 is a diagram showing an operation of the butterfly computing device when all the multiplication mode designating signals are set to the normal multiplication mode and both of the dual input data are non-zero in the above embodiment.

FIG. 11 is a diagram showing an operation of the butterfly computing device when all the multiplication mode designating signals are set to the sign computing mode and both of the dual input data are zero in the above embodiment.

FIG. 12 shows the operation of the butterfly computing device when the multiplication mode designating signals are all set to the sign computation mode, the first data of the dual input data is non-zero, and the second data is zero in the above embodiment. FIG.

FIG. 13 is an operation of the butterfly computing device when the multiplication mode designating signals are all set to the sign computation mode, the first data of the dual input data is zero, and the second data is non-zero in the above embodiment. FIG.

FIG. 14 is a diagram showing an operation of the butterfly computing device when all the multiplication mode designating signals are set to the sign computing mode and both of the dual input data are non-zero in the above embodiment.

FIG. 15 is a configuration diagram of an embodiment of an inverse discrete cosine transform device according to the present invention.

FIG. 16 is a table showing contents of operations of an address information generation unit and a butterfly operation coefficient information generation unit in the inverse discrete cosine transform device in the above embodiment.

FIG. 17 is a table showing the contents of the operation of the bit inversion order rearrangement unit in the above embodiment.

FIG. 18 is a table showing the number of calculations in the above embodiment.

FIG. 19 is a basic system configuration diagram of a color still image coding method JPEG to which the inverse discrete cosine transform device of the above embodiment is applied.

20 is a diagram showing a main part of the zero determination unit shown in FIG.

[Explanation of symbols]

 10 Dual Input Line 11 Zero Judgment Signal Line 12 Input Line to Multiplier 22 13 Butterfly Operation Coefficient Input Line 14 Output Line from Multiplier 22 15 Input Line to Adder 24 16 Dual Output Line 17 Multiply Mode Designating Signal Line 20 Zero determination unit 21 Multiplication input switching unit 22 Multiplication unit 23 Addition input switching unit 24 Addition unit 30 Input line to storage unit 31 Output line from storage unit 40 Butterfly operation device 41 storage unit 42 Butterfly operation coefficient information Generating unit 43 Address information generating unit 44 Bit inversion order rearranging unit 60 Inverse discrete cosine transform device 100 of the present invention 100 Encoding unit 101 Discrete cosine transform unit 102 Quantization unit 103 Entropy encoding unit 201 Entropy decoding unit 202 Inverse quantization unit 203 Inverse Discrete Cosine Transform Unit 204 Inverse Discrete Cosine Transform Unit of this Embodiment

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[Procedure amendment]

[Submission date] September 1, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

FIG. 6 is a chart showing the contents of the operation of the zero determination unit in the above embodiment.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] Fig. 16

[Correction method] Change

[Correction content]

FIG. 16 is a table showing the contents of operations of the address information generating unit and the butterfly operation coefficient information generating unit in the inverse discrete cosine transform device in the above embodiment.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 17

[Correction method] Change

[Correction content]

FIG. 17 is a chart showing the contents of the operation of the bit inversion order rearrangement unit in the above embodiment.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 18

[Correction method] Change

[Correction content]

FIG. 18 is a chart showing the number of calculations in the above embodiment.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiteru Mino 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A butterfly computing device having a dual input line, a dual output line, a multiplication means and an addition means, it is determined whether or not both dual input data from the dual input line are zero, and the determination result is obtained by each unit. When the dual input data are both zero, the dual input data is connected to the dual output data as it is as the dual output data. ,
If not, the multiplication input switching means for connecting the dual input line to the multiplication means and the multiplication mode designating signal separately input to return to the normal multiplication mode are used for the multiplication operation. Output as a product of non-zero data of the dual input data input by the operation of the input switching means and a butterfly operation coefficient corresponding to the non-zero data, and specify switching to the sign operation mode by the multiplication mode specifying signal. If the butterfly operation coefficient corresponding to the non-zero data is positive, the sign of the non-zero data is output as it is without being inverted, while if the corresponding butterfly operation coefficient is negative, “+” of the non-zero data is output. ,
Multiplying means for inverting the sign of “−” and outputting the result, the output data from the multiplying means and the determination result of the zero determining means are input, and only one of the dual input data is zero. Sometimes, the output from the multiplication means, which is obtained by multiplying the other non-zero of the dual input data and the corresponding butterfly operation coefficient, is directly connected to the dual output line as dual output data to obtain the dual input data. When it is determined that both of the data are non-zero, the addition input switching unit that outputs the input from the multiplication unit to the addition unit and the multiplication unit that is input from the addition input switching unit
A butterfly computing device comprising: an addition unit configured to add a plurality of output data in pairs and output as dual output data. 2. An inverse discrete cosine transform device provided with a butterfly computing device having a dual input line, a dual output line, a multiplying means and an adding means, wherein the butterfly computing device is provided for both dual input data from the dual input line. A zero determination means for determining whether or not it is zero and outputting the determination result to each part, and when both of the dual input data are zero in response to the determination result of the zero determination means, the dual input line is changed to the dual output line. Connected to the dual input data as it is as dual output data,
If not, the multiplication input switching means for connecting the dual input line to the multiplication means and the multiplication mode designating signal separately input to return to the normal multiplication mode are used for the multiplication operation. Output as a product of non-zero data of the dual input data input by the operation of the input switching means and a butterfly operation coefficient corresponding to the non-zero data, and specify switching to the sign operation mode by the multiplication mode specifying signal. If the butterfly operation coefficient corresponding to the non-zero data is positive, the sign of the non-zero data is output as it is without being inverted, while if the corresponding butterfly operation coefficient is negative, “+” of the non-zero data is output. ,
Multiplying means for inverting the sign of “−” and outputting the result, the output data from the multiplying means and the determination result of the zero determining means are input, and only one of the dual input data is zero. Sometimes, the output from the multiplication means, which is obtained by multiplying the other non-zero of the dual input data and the corresponding butterfly operation coefficient, is directly connected to the dual output line as dual output data to obtain the dual input data. When it is determined that both of the data are non-zero, the addition input switching unit that outputs the input from the multiplication unit to the addition unit and the multiplication unit that is input from the addition input switching unit
A memory for storing the dual input data and the dual output data, which is connected to the dual input line and the dual output line. Means, a butterfly operation coefficient information generating means for generating a butterfly operation coefficient and a multiplication mode designating signal when the inverse discrete cosine transform control signal is in the butterfly operation mode, and the storage means Address information generation that is connected and generates address information for outputting the dual input data and address information for storing the dual output data when the inverse discrete cosine transform control signal is in the butterfly operation mode Means for connecting to the storage means and storing the means for storing the inverse discrete cosine transform control signal in the rearrangement mode. An inverse discrete cosine transform device having a rearrangement means for rearranging data in the order of bit inversion.