JPH04225554A - Resin package - Google Patents
Resin packageInfo
- Publication number
- JPH04225554A JPH04225554A JP2408521A JP40852190A JPH04225554A JP H04225554 A JPH04225554 A JP H04225554A JP 2408521 A JP2408521 A JP 2408521A JP 40852190 A JP40852190 A JP 40852190A JP H04225554 A JPH04225554 A JP H04225554A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- substrate
- package
- chip
- molded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 title claims abstract description 21
- 229920005989 resin Polymers 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000012212 insulator Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 5
- 230000008646 thermal stress Effects 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、樹脂パッケージに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to resin packages.
【０００２】0002
【従来の技術】従来、ＬＳＩやＩＣなどの半導体素子（
以下、チップという）は、組立・加工工程などにおける
気密封止性や耐熱性、機械的強度、化学的安定性などの
各種の要求性能を満たして素子の劣化防止や信頼性向上
を図るべくパッケージが施されるのが一般的である。
このパッケージには主材料としてセラミックと樹脂の２
種類があり、量産性がよく材料コストが安い樹脂パッケ
ージが多く使用されている。このような樹脂パッケージ
は、通常、図２に示すように、アイランドと称する金属
フレーム２上にＡｕメタライズなどののりで接着されて
搭載されたチップ１をワイヤ３を用いてリード線４にボ
ンディングした後、樹脂５で全体をモールドして構成さ
れている。[Prior Art] Conventionally, semiconductor devices such as LSIs and ICs (
Chips (hereinafter referred to as chips) are packaged to meet various performance requirements such as hermetic sealability, heat resistance, mechanical strength, and chemical stability during assembly and processing processes, and to prevent element deterioration and improve reliability. is generally applied. This package has two main materials: ceramic and resin.
There are many types of resin packages, and resin packages are often used because they are easy to mass produce and have low material costs. As shown in FIG. 2, such a resin package usually has a chip 1 mounted on a metal frame 2 called an island and bonded to lead wires 4 using wires 3. After that, the entire structure is molded with resin 5.
【０００３】ところで、図３に示すように、多端子化さ
れたたとえばＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａ
ｇｅ）などの樹脂パッケージの場合は、そのリード線４
と製品基板の接続の際にはんだ液にどぶ漬けするいわゆ
る全面はんだディップの採用の要請が高まっている。そ
の理由は、全面はんだディップにはリードへのはんだ付
けの簡易化や高速化あるいははんだ均一性などのメリッ
トがあるからである。By the way, as shown in FIG. 3, for example, a multi-terminal QFP (Quad Flat Packer)
In the case of a resin package such as ge), its lead wire 4
There is an increasing demand for the adoption of so-called full-surface soldering dip, which involves immersing products in solder liquid when connecting product boards. The reason for this is that full-surface solder dipping has advantages such as simplifying and speeding up soldering to leads, and improving solder uniformity.
【０００４】0004
【発明が解決しようとする課題】しかしながら、上記し
た全面はんだディップでたとえば６４ピン以上のＱＦＰ
を製造する場合は、２６０ ℃もの温度を有するはんだ
槽の熱衝撃により吸収されていた水分が膨張し、モール
ド内のチップの下部側にいわゆるパッケージクラックが
発生するという問題があり、技術的に相当の困難を伴っ
ていた。本発明は、このような課題を解決した樹脂パッ
ケージを提供することを目的とする。[Problems to be Solved by the Invention] However, when using the above-mentioned full-surface solder dip, for example, QFPs with 64 pins or more
When manufacturing, there is a problem that the absorbed water expands due to the thermal shock of the solder bath, which has a temperature of 260 degrees Celsius, and so-called package cracks occur on the lower side of the chip in the mold, which is technically equivalent. It was accompanied by difficulties. An object of the present invention is to provide a resin package that solves these problems.
【０００５】[0005]
【課題を解決するための手段】本発明は、金属フレーム
上に搭載された半導体素子をリード線にワイヤボンディ
ングした後樹脂で全体をモールドする樹脂パッケージに
おいて、前記半導体素子を所定の面積を有する金属基板
に搭載し、該基板の上端部に絶縁体を介して支持された
前記リード線をワイヤボンディングし、その後前記基板
の上部全体をモールドすることを特徴とする樹脂パッケ
ージである。[Means for Solving the Problems] The present invention provides a resin package in which a semiconductor element mounted on a metal frame is wire-bonded to lead wires and then the whole is molded with resin. The resin package is mounted on a substrate, the lead wires supported via an insulator are wire-bonded to the upper end of the substrate, and then the entire upper portion of the substrate is molded.
【０００６】[0006]
【作 用】本発明によれば、チップ（半導体素子）を
搭載する金属フレームにチップの熱膨張率と同程度の特
性を有する金属基板を用いて、その基板の上部のみをモ
ールドするようにしたので、どぶ漬け時の熱応力による
パッケージクラックを未然に防ぐことができる。また、
金属基板の下面を露出するようにしているので、チップ
の放熱効果を高めることができる。なお、ここで用いら
れる金属基板とする金属には半金属も含まれ、シリコン
，Ｆｅなどが好適である。[Operation] According to the present invention, a metal substrate having characteristics comparable to the coefficient of thermal expansion of the chip is used for the metal frame on which the chip (semiconductor element) is mounted, and only the upper part of the substrate is molded. Therefore, package cracks due to thermal stress during soaking can be prevented. Also,
Since the lower surface of the metal substrate is exposed, the heat dissipation effect of the chip can be enhanced. Note that the metal used for the metal substrate used here includes semimetals, and silicon, Fe, and the like are preferable.
【０００７】[0007]
【実施例】図１は本発明の実施例を示したもので、チッ
プ１はシリコン基板６上に搭載される。このシリコン基
板６の厚さｔはモールドされる樹脂５の厚さとほぼ同程
度とされる。また、リード線４はそのシリコン基板６の
上端部にたとえばポリイミドなどの絶縁物７を介して支
持され、ワイヤ３によってチップ１とボンディングされ
る。そして、プラスチックなどの樹脂５を用いてシリコ
ン基板６の上部全体を所定の厚さにモールドする。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, in which a chip 1 is mounted on a silicon substrate 6. As shown in FIG. The thickness t of this silicon substrate 6 is approximately the same as the thickness of the resin 5 to be molded. Further, the lead wire 4 is supported at the upper end of the silicon substrate 6 via an insulator 7 such as polyimide, and is bonded to the chip 1 by the wire 3. Then, the entire upper part of the silicon substrate 6 is molded to a predetermined thickness using a resin 5 such as plastic.
【０００８】このような樹脂パッケージを構成すること
により、パッケージクラックの発生の少ない多ピンのパ
ッケージあるいは全面はんだディップが可能なパッケー
ジを製造することができる。なお、シリコン基板６の下
面は露出した状態であるから、素子の発熱を速やかに放
出し得るという効果を上げることができる。By constructing such a resin package, it is possible to manufacture a multi-pin package or a package that can be soldered all over with less occurrence of package cracks. Note that since the lower surface of the silicon substrate 6 is exposed, it is possible to improve the effect that heat generated by the element can be quickly released.
【０００９】[0009]
【発明の効果】以上説明したように、本発明によれば、
チップを金属基板に搭載してその基板の上部のみをモー
ルドするようにしたので、どぶ漬け時の熱応力によるパ
ッケージクラックを未然に防ぐことができ、製品の品質
や歩留りの向上に寄与するというすぐれた効果を奏する
。[Effects of the Invention] As explained above, according to the present invention,
Since the chip is mounted on a metal substrate and only the upper part of the substrate is molded, it is possible to prevent the package from cracking due to thermal stress during soaking, which is an excellent feature that contributes to improving product quality and yield. It has a great effect.
【図１】本発明の実施例の構成を示す概要図である。FIG. 1 is a schematic diagram showing the configuration of an embodiment of the present invention.
【図２】従来例の構成を示す概要図である。FIG. 2 is a schematic diagram showing the configuration of a conventional example.
【図３】従来のフラットパッケージを示す平面図である
。FIG. 3 is a plan view showing a conventional flat package.
１ チップ（半導体素子） ３ ワイヤ ４ リード線 ５ 樹脂 ６ シリコン基板（金属基板） ７ 絶縁物 1 Chip (semiconductor element) 3 Wire 4 Lead wire 5 Resin 6 Silicon substrate (metal substrate) 7 Insulator
Claims (1)
子をリード線にワイヤボンディングした後樹脂で全体を
モールドする樹脂パッケージにおいて、前記半導体素子
を所定の面積を有する金属基板に搭載し、該基板の上端
部に絶縁体を介して支持された前記リード線をワイヤボ
ンディングし、その後前記基板の上部全体をモールドす
ることを特徴とする樹脂パッケージ。1. In a resin package in which a semiconductor element mounted on a metal frame is wire-bonded to lead wires and then the whole is molded with resin, the semiconductor element is mounted on a metal substrate having a predetermined area, and the semiconductor element is mounted on a metal substrate having a predetermined area. A resin package characterized in that the lead wires supported at the upper end portion via an insulator are wire-bonded, and then the entire upper portion of the substrate is molded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2408521A JPH04225554A (en) | 1990-12-27 | 1990-12-27 | Resin package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2408521A JPH04225554A (en) | 1990-12-27 | 1990-12-27 | Resin package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04225554A true JPH04225554A (en) | 1992-08-14 |
Family
ID=18517963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2408521A Pending JPH04225554A (en) | 1990-12-27 | 1990-12-27 | Resin package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04225554A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818105A (en) * | 1994-07-22 | 1998-10-06 | Nec Corporation | Semiconductor device with plastic material covering a semiconductor chip mounted on a substrate of the device |
-
1990
- 1990-12-27 JP JP2408521A patent/JPH04225554A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818105A (en) * | 1994-07-22 | 1998-10-06 | Nec Corporation | Semiconductor device with plastic material covering a semiconductor chip mounted on a substrate of the device |
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