JPH01227462A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH01227462A
JPH01227462A JP5425188A JP5425188A JPH01227462A JP H01227462 A JPH01227462 A JP H01227462A JP 5425188 A JP5425188 A JP 5425188A JP 5425188 A JP5425188 A JP 5425188A JP H01227462 A JPH01227462 A JP H01227462A
Authority
JP
Japan
Prior art keywords
die pad
slits
lead frame
resin
cross
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5425188A
Other languages
Japanese (ja)
Inventor
Masayoshi Achinami
阿知波 正義
Koji Nose
幸之 野世
Shinji Mitsui
三井 真司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP5425188A priority Critical patent/JPH01227462A/en
Publication of JPH01227462A publication Critical patent/JPH01227462A/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce stress applied to a sealing resin and a die pad, and to load a large-sized semiconductor chip onto a resin seal type package 111 the same size as conventional packages by providing a slit to the die pad. CONSTITUTION:A lead frame has a die pad 2, to which slits 10 are formed, so that all cross sections of the arbitrary cross section in the direction of the long side, arbitrary surface in the direction of short side and diagonal cross section of a die pad 2 for the lead frame used for a resin seal type semiconductor package are crossed on at least one position of slits 10. The slits 10 are shaped so as to mutually run parallel up to the center at right angles with sides from one positions of each opposite side of the long sides and short sides of the end sections of the die pad 2. When there is the possibility of the lowering of the strength of the die pad 2 on die bonding and wire bonding by shaping the slits up to sections near the center from the end sections of the die pad 2, the slits 10 from the end sections of the die pad 2 are shortened, and slits 101 are formed insularly in the die pad 2.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路装置に用いる樹脂封止形パッ
ケージのリードフレームに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a lead frame for a resin-sealed package used in a semiconductor integrated circuit device.

従来の技術 電子機器の小形、軽量化が進む中で、当然のことながら
、これに用いる電子部品の小形化が強く要望されている
。この電子部品はプリント基板に装着されて用いられ・
るが、最近はより実装密度を上げるために、プリント基
板の両面に半田により固着して使用するいわゆる表面実
装がとり入れられている。
BACKGROUND OF THE INVENTION As electronic devices become smaller and lighter, there is naturally a strong demand for smaller electronic components used in these devices. This electronic component is mounted on a printed circuit board and used.
However, recently, so-called surface mounting, which uses solder to adhere to both sides of a printed circuit board, has been adopted in order to further increase the packaging density.

ところでこの電子部品の中核をなす半導体集積回路装置
は、樹脂封止形半導体パッケージを用いることが多い。
Incidentally, a semiconductor integrated circuit device, which forms the core of this electronic component, often uses a resin-sealed semiconductor package.

これに用いるリードフレームを第3図に、表面実装用の
樹脂封止形パッケージの代表例として、小形で1字形の
外部リードのパッケージ(S  OJ (Small 
 0utline  ”J” Lead  Packa
ge)1を第4図に示し、これらを参照して説明する。
The lead frame used for this is shown in Figure 3, and is a typical example of a resin-sealed package for surface mounting.
0utline “J” Lead Packa
ge) 1 is shown in FIG. 4 and will be explained with reference to these.

第3図は樹脂封止形半導体パッケージに用いられるリー
ドフレームの平面図であり、リードフレームlは、厚さ
0.2mm程度の鉄ニツケル合金や銅をプレス加工ある
いは化学エツチング加工により成形したものである。こ
のリードフレーム1は、半導体チップを載置するダイパ
ッド2と内部リード3と外部リード4とタイバー5およ
びダイパッド2をささえる吊りリード6で構成されてい
る。このリードフレームを用いたSOJパッケージの斜
視図を第4図に示す。このSOJパッケージ8はダイパ
ッドに半導体チップが載置されたリードフレームを樹脂
7で封止し、外部リード4を”J“字状に成形したもの
である。
Figure 3 is a plan view of a lead frame used in a resin-sealed semiconductor package.The lead frame l is made of iron-nickel alloy or copper with a thickness of about 0.2 mm by pressing or chemical etching. be. This lead frame 1 includes a die pad 2 on which a semiconductor chip is placed, internal leads 3, external leads 4, tie bars 5, and hanging leads 6 that support the die pad 2. FIG. 4 shows a perspective view of an SOJ package using this lead frame. This SOJ package 8 has a lead frame with a semiconductor chip mounted on a die pad sealed with resin 7, and external leads 4 formed into a "J" shape.

発明が解決しようとする課題 しかしながら、近年、超LSIとも呼ばれる素子数が大
規模な半導体集積回路装置が製造されており、一つの半
導体チップの大きさが、100m1−にも及ぶものがあ
るのも希ではない。しかもこれらの大きな半導体チップ
は、機器の小形化のために従来と同じ大きさの樹脂封止
形半導体パッケージに収められている。
Problems to be Solved by the Invention However, in recent years, semiconductor integrated circuit devices with a large number of elements, also called VLSIs, have been manufactured, and the size of a single semiconductor chip can reach up to 100 m1. Not rare. Moreover, these large semiconductor chips are housed in resin-sealed semiconductor packages of the same size as conventional ones in order to downsize devices.

ところが、表面実装では、半導体集積回路装置がプリン
ト基板上に仮止めされ、半田槽中を通すデイツプ方式や
、赤外線で加熱し半田付けを行ういわゆるリフロ一方式
により接着されるが、この工程の温度は、約240℃の
高温にもなる。このため、半導体集積回路装置の封止樹
脂にクラックが発生し、品質上の重大な問題をひきおこ
すことがある。この原因は封止樹脂の熱膨脹係数と封止
られた半導体チップやダイパッドの熱膨脹係数の差にも
とづく応力のためである。特に大形の半導体チップを封
止すると、これを載せるダイパッドも太き(なり、封止
樹脂に加わる応力が増加するとともに、ダイパッドや半
導体チップを覆う封止樹脂の厚さが薄(なり、封止樹脂
が熱による応力に力学的に抗し切れないためである。
However, in surface mounting, a semiconductor integrated circuit device is temporarily attached to a printed circuit board and bonded by a dip method in which it is passed through a solder bath, or a so-called reflow method in which soldering is performed by heating with infrared rays, but the temperature of this process is reaches a high temperature of about 240°C. As a result, cracks may occur in the sealing resin of the semiconductor integrated circuit device, causing serious quality problems. This is caused by stress due to the difference between the coefficient of thermal expansion of the sealing resin and the coefficient of thermal expansion of the encapsulated semiconductor chip or die pad. In particular, when a large semiconductor chip is encapsulated, the die pad on which it is placed also becomes thicker (which increases the stress applied to the encapsulating resin), and the thickness of the encapsulating resin that covers the die pad and semiconductor chip becomes thinner (which increases the stress applied to the encapsulating resin). This is because the stopper resin cannot mechanically resist stress caused by heat.

課題を解決するための手段 この課題を解決するための、本発明のリードフレームは
半導体チップを積載するダイパッドの長辺方向及び短辺
方向の任意の個所での断面や対角線方向の断面が少くと
も、1個所はスリットを横切るようにダイパッドが形成
されたものである。
Means for Solving the Problem In order to solve this problem, the lead frame of the present invention has a die pad on which a semiconductor chip is mounted, with a cross section at any point in the long side direction and short side direction, or a cross section in the diagonal direction at least. , one place has a die pad formed across the slit.

作用 本発明のリードフレームによれば、ダイパッドに形成さ
れたスリットは熱膨脹係数の異なる物質、即ち、封止樹
脂とダイパッドを長い距離にわたり接することがないよ
うに分断するため、封止樹脂にかかる最大応力を減小さ
せるとともに、応力を分散させることができる。また、
ダイパッドの体積が小さくなる分だけ樹脂の量が多くな
るため樹脂の抗力が増大する。
According to the lead frame of the present invention, the slit formed in the die pad separates materials with different coefficients of thermal expansion, that is, the sealing resin and the die pad, so that they do not come into contact over a long distance, so that the maximum applied to the sealing resin is It is possible to reduce stress and to disperse stress. Also,
As the volume of the die pad decreases, the amount of resin increases, so the drag force of the resin increases.

実施例 本発明のリードフレームの実施例を第1図に示したダイ
パッドの平面図を参照して説明する。このリードフレー
ムは厚さが0.2m程度の鉄ニツケル合金や銅で形成さ
れ、リードフレームのダイパッド2の端部の長辺および
短辺のそれぞれの相対辺より1個所ずつから辺に直角に
中央まで互いに平行になるようにスリット10を設けた
ものである。なお辺からのスリットの形成はこれに限ら
れたものではなく、ようはダイパッドの長辺方向及び短
辺方向の任意の個所での断面や対角線方向の断面が少(
とも1個所はスリット10を横切るように入れたもので
あればよい。この結果、広い範囲で熱膨脹係数の異なる
封止樹脂とダイパッドが接することがないようにするこ
とができる。
Embodiment An embodiment of the lead frame of the present invention will be described with reference to the plan view of the die pad shown in FIG. This lead frame is made of iron-nickel alloy or copper with a thickness of about 0.2 m, and is formed from one point on each of the long and short sides of the end of the die pad 2 of the lead frame at right angles to the center. The slits 10 are provided so as to be parallel to each other. Note that the formation of slits from the sides is not limited to this, and the cross section at any point in the long side direction and short side direction of the die pad or the cross section in the diagonal direction is small (
It suffices if one of the holes is inserted across the slit 10. As a result, it is possible to prevent the die pad from coming into contact with sealing resins having different coefficients of thermal expansion over a wide range.

また、本発明の他の実施例としてスリットをダイパッド
2の端部より中央あたりまで入れることにより、ダイス
ボンドやワイヤボンド時に、ダイパッド2の力学的強度
の低下が懸念される場合には、第2図に示すようにグイ
パッド2の端部がらのスリットIOは短か(して、ダイ
パッド2の中にスリット101を島状に形成し、ダイパ
ッドの長辺方向および短辺方向の任意の個所での断面や
対角線方向の断面が少な(とも1個所はスリット10と
101を横切るようにする。なお、リードフレームのダ
イパッド2以外の部分は第3図に示したものと同じであ
る。
In addition, as another embodiment of the present invention, by inserting a slit from the end of the die pad 2 to the center, if there is a concern that the mechanical strength of the die pad 2 will decrease during die bonding or wire bonding, the second As shown in the figure, the slit IO at the end of the die pad 2 is short (so that the slit 101 is formed in the shape of an island in the die pad 2, and the slit 101 is formed in the shape of an island in the die pad 2, and the slit 101 is formed at an arbitrary point in the long side direction and the short side direction of the die pad 2. The cross section and the cross section in the diagonal direction are small (at least one cross section crosses the slits 10 and 101. The parts of the lead frame other than the die pad 2 are the same as those shown in FIG. 3).

次に、本発明のリードフレームを用いたSOJパッケー
ジの組み立てを説明する。なお、このとき第3図と第4
図も参照する。ダイパッド2の上に、半導体チップを例
えば銀ペーストと呼ばれる樹脂により固着した後、半導
体チップ上に形成されたポンディングパッドと内部リー
ド3を金の細線により接続する。しかる後、封止金型を
用いて、半導体チップが固着されたダイパッド2と内部
リード3を樹脂7で封止をする。このときダイパッドの
スリットにも樹脂が充填され、ダイパッドと樹脂の接触
が分断される。この後、外部り−ド4を結ぶダイパー5
や吊りリード6を落した後、第4図に示すように、外部
リード4を内側へJ”字形に成形しSOJパッケージ8
が完成する。
Next, assembly of an SOJ package using the lead frame of the present invention will be explained. At this time, Figures 3 and 4
See also figure. After a semiconductor chip is fixed onto the die pad 2 using a resin called silver paste, for example, the bonding pads formed on the semiconductor chip and the internal leads 3 are connected using thin gold wires. Thereafter, the die pad 2 to which the semiconductor chip is fixed and the internal leads 3 are sealed with resin 7 using a sealing mold. At this time, the slit of the die pad is also filled with resin, and the contact between the die pad and the resin is severed. After this, the diameter 5 which connects the outer wire 4 is
After dropping the suspension leads 6, the external leads 4 are formed inward into a J" shape as shown in FIG. 4, and the SOJ package 8 is assembled.
is completed.

発明の効果 本発明のリードフレームによれば、ダイパッドにスリッ
トを設けることにより封止樹脂とダイパッドにかかる応
力を減少させることができるため、大形の半導体チップ
を従来と同じ大きさの樹脂封止形パッケージに搭載する
ことができる。この結果、工程の標準化と機器の小形化
に役立ち、その工業的価値は大きい。
Effects of the Invention According to the lead frame of the present invention, the stress applied to the sealing resin and the die pad can be reduced by providing a slit in the die pad, so that a large semiconductor chip can be sealed with resin of the same size as before. It can be installed in a shaped package. As a result, it helps standardize processes and downsize equipment, and has great industrial value.

用いる本発明のリードフレームを説明するためのダイパ
ッドの平面図、第3図は従来のリードフレームの平面図
、第4図は表面実装用半導体パッケージであるSOJの
斜視図である。
FIG. 3 is a plan view of a die pad for explaining the lead frame of the present invention used, FIG. 3 is a plan view of a conventional lead frame, and FIG. 4 is a perspective view of an SOJ which is a surface mounting semiconductor package.

2・・・・・・ダイパッド、10,101・・・・・・
スリット。
2...Die pad, 10,101...
slit.

代理人の氏名 弁理士 中尾敏男 ほか1名?−−−タ
゛イパッド 第1111
Name of agent: Patent attorney Toshio Nakao and one other person? ---Tiepad No. 1111

Claims (1)

【特許請求の範囲】[Claims]  樹脂封止形半導体パッケージに用いるリードフレーム
のダイパッドの長辺方向の任意断面と短辺方向の任意断
面および対角線断面のいづれの断面も、スリットを少く
とも1個所は横切るように前記スリットが形成されたダ
イパッドを有するリードフレーム。
The slit is formed so as to cross at least one slit in any cross section in the long side direction, short side direction, and diagonal cross section of a die pad of a lead frame used in a resin-sealed semiconductor package. A lead frame with a die pad.
JP5425188A 1988-03-08 1988-03-08 Lead frame Pending JPH01227462A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5425188A JPH01227462A (en) 1988-03-08 1988-03-08 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5425188A JPH01227462A (en) 1988-03-08 1988-03-08 Lead frame

Publications (1)

Publication Number Publication Date
JPH01227462A true JPH01227462A (en) 1989-09-11

Family

ID=12965330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5425188A Pending JPH01227462A (en) 1988-03-08 1988-03-08 Lead frame

Country Status (1)

Country Link
JP (1) JPH01227462A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204106A (en) * 1995-01-25 1996-08-09 Nec Corp Resin sealed semiconductor device
JP2015106609A (en) * 2013-11-29 2015-06-08 サンケン電気株式会社 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204106A (en) * 1995-01-25 1996-08-09 Nec Corp Resin sealed semiconductor device
JP2015106609A (en) * 2013-11-29 2015-06-08 サンケン電気株式会社 Semiconductor device

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