JPH04225178A - Measuring device for semiconductor - Google Patents

Measuring device for semiconductor

Info

Publication number
JPH04225178A
JPH04225178A JP40763090A JP40763090A JPH04225178A JP H04225178 A JPH04225178 A JP H04225178A JP 40763090 A JP40763090 A JP 40763090A JP 40763090 A JP40763090 A JP 40763090A JP H04225178 A JPH04225178 A JP H04225178A
Authority
JP
Japan
Prior art keywords
pretest
contact
dut
position regulation
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP40763090A
Other languages
Japanese (ja)
Inventor
Takaaki Tanaka
孝明 田中
Hidehiko Tomota
友田 英彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP40763090A priority Critical patent/JPH04225178A/en
Publication of JPH04225178A publication Critical patent/JPH04225178A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To reduce a failure by position regulation and shorten a test time by making first the position regulation, there after carrying out a pretest and making this result the feedback to a handler or water probe in the case of defective. CONSTITUTION:First, a test object (DUT) is loaded onto a carrier system and position regulation is made. Nest, contact is made on and a start signal is sent to a tester. The pretest laying stress on the contact check is made and that quality is judged by the tester. In the case of defective, the contact is made off and the pretest result is made feedback to a handler or wafer probe. Again, the position regulation is carried out and the pretest is made. These operations are repeated N times till the pretest is passed. The DUT not passed even where the pretest is repeated N times is made defective. On the other hand, a main test is carried out to the DUT passed and the contact is made off after the end, the test result is received and the DUT is unloaded.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、被テスト対象と測定系
とのコンタクト精度を、プリテスト結果をフィードバッ
クすることによって向上させることのできる機能を持っ
た半導体測定装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor measuring device having a function of improving the contact accuracy between an object to be tested and a measuring system by feeding back pretest results.

【0002】0002

【従来の技術】以下、従来の半導体測定装置について説
明する。図2は従来の半導体測定装置のフローチャート
である。図2において、まず、ステップ1で搬送系に被
テスト対象(以下DUTという)をロードし、ステップ
2で位置規制を行う。次にステップ3でコンタクトをO
Nにし、ステップ4でテスターにスタート信号を送る。 ステップ5でテスターによるテストを行い、ステップ6
でテスト終了信号をもらった後、ステップ7でコンタク
トをOFFし、ステップ8でテスト結果を受けとり、最
後にステップ9でDUTをアンロードする。
2. Description of the Related Art A conventional semiconductor measuring device will be explained below. FIG. 2 is a flowchart of a conventional semiconductor measuring device. In FIG. 2, first, in step 1, an object to be tested (hereinafter referred to as DUT) is loaded onto the transport system, and in step 2, position regulation is performed. Next, in step 3, turn the contact
Set to N and send a start signal to the tester in step 4. In step 5, a test is performed by a tester, and in step 6
After receiving a test completion signal, the contact is turned off in step 7, the test result is received in step 8, and finally the DUT is unloaded in step 9.

【0003】0003

【発明が解決しようとする課題】しかしながら上記従来
の構成では、位置規制を失敗するとテストを不良として
判断してしまうので、不良再検の扱い数が増加し、結果
としてテスト時間を長くしてしまうという問題があった
[Problems to be Solved by the Invention] However, in the conventional configuration described above, if the position regulation fails, the test is determined to be defective, which increases the number of defective re-examinations and, as a result, lengthens the test time. There was a problem.

【0004】本発明は上記従来の問題を解決するもので
、位置規制による失敗を少なくし、テスト時間を短かく
することのできる半導体規定装置を提供することを目的
とするものである。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a semiconductor specifying device that can reduce failures due to position regulation and shorten test time.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に本発明の半導体測定装置は、最初位置規制を行った後
、まず、コンタクトチェックを中心としたプリテストを
実施し、不良判定が出た場合、このプリテスト結果をハ
ンドラまたはウェハプローブにフィードバックして、再
度位置規制を行わせる手段を設けたものである。
[Means for Solving the Problems] In order to solve the above problems, the semiconductor measuring device of the present invention first performs position regulation, and then first performs a pre-test centered on contact checks, and detects defects. In this case, a means is provided for feeding back this pretest result to the handler or wafer probe to have the position regulation performed again.

【0006】[0006]

【作用】上記構成により、プリテスト結果をハンドラま
たはウェハプローブにフィードバックすることによって
、一度位置規制に失敗したDUTを再度位置規制させる
ことができるため、結果的にコンタクト精度を高めるこ
とができ、再検扱い数が減少する分テスト時間を全体と
して短縮できる。しかも、もともと行っているコンタク
トチェックをプリテスト側に移して行うため、プリテス
トによるテスト時間の増加はほとんどない。
[Operation] With the above configuration, by feeding back the pretest results to the handler or wafer probe, it is possible to re-regulate the position of a DUT that once failed in position regulation, resulting in improved contact accuracy and re-inspection. As the number decreases, the overall test time can be shortened. Moreover, since the contact check that is originally performed is moved to the pretest side, there is almost no increase in test time due to the pretest.

【0007】[0007]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。図1は本発明の一実施例における
半導体測定装置のフローチャートを示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a flowchart of a semiconductor measuring device according to an embodiment of the present invention.

【0008】図1において、まず、ステップ11で搬送
系にDUTをロードし、ステップ12で位置規制を行う
。次にステップ13でコンタクトをONにし、ステップ
14でテスターにスタート信号を送る。テスターでは、
まずステップ15でコンタクトチェックを中心としたプ
リテストを実施し、ステップ16でその良否を判定する
。もし不良の場合はステップ17でコンタクトをOFF
してプリテスト結果をハンドラまたはウェハプローブに
フィードバックし、ステップ12に戻って再度、位置規
制を実施し、プリテストを行う。この操作をプリテスト
がパスするまでステップ18でN回繰り返す。N回繰り
返してもパスしないDUTに対しては、不良とする。一
方、プリテストをパスしたDUTに対しては、ステップ
19でメインテストを実施し、ステップ20で終了後、
ステップ21コンタクトをOFFし、ステップ22でテ
スト結果を受けとり、アンロードする。
In FIG. 1, first, in step 11, the DUT is loaded onto the transport system, and in step 12, the position is regulated. Next, in step 13, the contact is turned on, and in step 14, a start signal is sent to the tester. In the tester,
First, in step 15, a pretest centered on a contact check is carried out, and in step 16, the quality of the pretest is determined. If it is defective, turn off the contact in step 17.
Then, the pretest result is fed back to the handler or wafer probe, and the process returns to step 12 to perform position regulation again and perform the pretest. This operation is repeated N times in step 18 until the pretest passes. A DUT that does not pass even after repeating N times is determined to be defective. On the other hand, for the DUT that passed the pretest, the main test is carried out in step 19, and after finishing in step 20,
In step 21, the contact is turned off, and in step 22, the test result is received and unloaded.

【0009】[0009]

【発明の効果】以上のように本発明によれば、プリテス
トの結果をハンドラまたはウェハプローブにフィードバ
ックすることにより、DUTの位置規制によるコンタク
ト精度を向上させることができ、再検扱い数が減少する
分、テスト時間を全体として短縮できる。
As described above, according to the present invention, by feeding back the pretest results to the handler or wafer probe, it is possible to improve the contact accuracy by regulating the position of the DUT, and the number of retests is reduced. , the overall test time can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例における半導体測定装置のフ
ローチャートである。
FIG. 1 is a flowchart of a semiconductor measuring device according to an embodiment of the present invention.

【図2】従来の半導体測定装置のフローチャートである
FIG. 2 is a flowchart of a conventional semiconductor measuring device.

【符号の説明】[Explanation of symbols]

15    コンタクトチェックを中心としてプリテス
トのステップ
15 Pretest steps focusing on contact check

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  テスターのプリテスト結果をハンドラ
またはウェハプローバにフィードバックして、角度位置
規則を行わせる手段を設けた半導体測定装置。
1. A semiconductor measuring device comprising means for feeding back pretest results of a tester to a handler or a wafer prober to perform angular position regulation.
JP40763090A 1990-12-27 1990-12-27 Measuring device for semiconductor Pending JPH04225178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP40763090A JPH04225178A (en) 1990-12-27 1990-12-27 Measuring device for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40763090A JPH04225178A (en) 1990-12-27 1990-12-27 Measuring device for semiconductor

Publications (1)

Publication Number Publication Date
JPH04225178A true JPH04225178A (en) 1992-08-14

Family

ID=18517196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP40763090A Pending JPH04225178A (en) 1990-12-27 1990-12-27 Measuring device for semiconductor

Country Status (1)

Country Link
JP (1) JPH04225178A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574383A (en) * 1994-02-08 1996-11-12 Sony Corporation IC tester and measuring method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574383A (en) * 1994-02-08 1996-11-12 Sony Corporation IC tester and measuring method

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