JPH04221711A - Signal take in circuit - Google Patents

Abstract

PURPOSE:To surely take in a narrow positive pulse-like portion produced when an input signal is in the negative ramp state. CONSTITUTION:In a signal take-in circuit in which output of a sample hold circuit 15 and an input signal are compared by a ramp detector 21, when the input signal is larger, a positive peak detection circuit 12 is connected to the sample hold circuit 15, and when the input signal is smaller, a negative peak detection circuit 13 is connected to the sample hold circuit 15, the output of the positive peak detection circuit 12 is differentiated by a differentiating circuit 35, and when the differentiated output pulse is more than a designated level, a pulse signal detection circuit 37 detects the existence of a positive pulse-like portion in the input signal, and the positive peak detection circuit is connected to the sample hold circuit 15 according to the output regardless of the output state of the ramp detector 21.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is used, for example, in a spectrum analyzer to periodically sample and hold a waveform signal of a detection output, convert the sample-and-hold value into a digital signal, take it in, and digitally process it. The present invention relates to a signal acquisition circuit that is also capable of capturing pulse-like portions of signals that occur during sample-and-hold periods.

0002

2. Description of the Related Art FIG. 3 shows a conventional signal acquisition circuit. For example, a detection output from a spectrum analyzer is supplied as an input signal from an input terminal 11 to a positive peak detection circuit 12 and a negative peak detection circuit 13.
The output of either one of 2 and 13 is supplied to a sample and hold circuit 15 through a switch 14. The input of the sample-and-hold circuit 15 is sampled by a constant periodic pulse outputted from the pulse generation circuit 16, and its value is held. The output pulse of the pulse generation circuit 16 is transmitted to the delay circuit 17.
The detected peak values of the positive peak detection circuit 12 and the negative peak detection circuit 13 are cleared by the delayed pulse. The output of the sample hold circuit 15 is AD
The signal is converted into a digital signal by a converter 18, and the digital signal is processed, for example, by a signal digital processing circuit 19, and further displayed if necessary.

The output of the sample and hold circuit 15 and the input signal of the input terminal 11 are compared by a slope detector 21, and the comparison result of the slope detector 21 is outputted from a delay circuit 17 and taken into a D-type flip-flop 22. . The output of the D-type flip-flop 22 is supplied to the switch 14 as a switching control signal through an OR circuit 23. When the input signal is larger than the output of the sample-and-hold circuit 15, the output of the slope detector 21 becomes a high level, that is, the input signal is detected to have a positive slope, and this high level is applied to the D-type flip-flop 22. The switch 14 is switched to the positive peak detection circuit 12 side. Sample hold circuit 15
If the input signal is smaller than the output of the tilt detector 21
output becomes low level, the input signal is detected to have a negative slope, this low level is taken into the D-type flip-flop 22, and the switch 14 is switched to the negative peak detection circuit 13 side.

In this manner, when the input signal is in a rising state, the positive peak value of the input signal during each sampling period is taken into the sample hold circuit 15, and when the input signal is in a falling state, the negative peak value of the input signal during each sampling period is taken into the sample hold circuit 15. The peak value of is taken into the sample hold circuit 15. As shown in FIG. 4, for each sampling pulse (A), the output of the tilt detector 21 changes as shown in FIG. When the peak detection circuit 12 side is switched and connected to the negative peak detection circuit 13 side with a low level L output, and the input signal changes as shown in FIG.
In the middle of the process, the input signal changes from rising to falling. Therefore, in the next sampling period section T2, the input signal is smaller than the output level L1 of the sample and hold circuit 15, and the sample and hold circuit 15
Switched to side 3. In this interval T2, the input signal is in a falling state, but if there is a positive pulse-like portion 24 on the way, the signal of this pulse-like portion 24 is lost.

For this reason, conventionally, as shown in FIG. 3, the input signal and the output of the positive peak detection circuit 12 are compared by a voltage comparator 25, and if a positive pulse-like portion 24 is present in the input signal, the input signal is compared with the output of the positive peak detection circuit 12. As shown in FIG. 4E, the output of the voltage comparator 25 is inverted to a high level, and the flip-flop 26 is set at the rise of the high level, and the Q output of the flip-flop 26 is output from the delay circuit 17 and is set to a D-type flip-flop. The high level output of the D-type flip-flop 27 is supplied as a control signal to the switch 14 through the OR circuit 23, and the switch 14 is input to the positive peak detection circuit 1.
Forced to switch to side 2. At this time, the output of the OR circuit 23 is slightly delayed by the delay circuit 28 and supplied to the switch 14 as a control signal, and is also supplied to the gate 29 and the inverter 31 without passing through the delay circuit 28, and the output of the inverter 31 is 32, gate 2
9 and 32, the positive peak detection circuit 12 and the negative peak detection circuit 13 are cleared by the output pulse of the delay circuit 17, that is, only the peak detection circuit on the side whose peak value is sampled and held in the sample and hold circuit 15 is cleared. be made to be done.

Therefore, as shown in FIG. 4, in interval T2, the output of the negative peak detection circuit 13 is sampled and held, and the negative peak detection circuit 13 is cleared, but the positive peak detection circuit 12 is not cleared, and the pulse shape of the input signal is The peak value L2 of the pulse-shaped portion 24 is held, and in the next interval T3, the sample-and-hold circuit 15 is connected to the positive peak detection circuit 12 side by the output of the D-type flip-flop 27, so that the peak value L2 of the pulse-shaped portion 24 is held. The peak value L2 is sampled and held. In this way, the signal of the positive pulsed portion 24 that occurs during the falling state of the input signal is not lost. After the output of the flip-flop 26 is taken into the D-type flip-flop 27, it is reset through the delay circuit 33.

[0007]

Problem to be Solved by the Invention When the input signal changes in a pulse-like manner faster than the response speed of the voltage comparator 25,
Since the output of the voltage comparator 25 does not invert to a high level at this pulse-like portion, the signal of this pulse-like portion cannot be taken in. For example, for pulse modulated waves such as radar, 200
This is a pulse signal with a width of n seconds, and in order to capture such a pulse signal, it is necessary to increase the response speed of the voltage comparator 25. However, if the response speed of the voltage comparator 25 is increased, it will also respond to small-level whisker-like noise, making it difficult to correctly capture the signal.

[0008]

[Means for Solving the Problems] According to the present invention, the output of the positive peak detection circuit is also supplied to a differentiation circuit, and when the differentiation output is above a predetermined level, it is detected as a pulse signal by the pulse signal detection circuit, The detection output controls a switch so as to connect the sample and hold circuit to the positive peak detection circuit side regardless of the output of the slope detector.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. 3 are given the same reference numerals. In this invention, the output of the positive peak detection circuit 12 is also branched and supplied to the differentiating circuit 35. The output of the differentiating circuit 35 is sent to the amplifier 3 as necessary.
6 and supplied to the pulse signal detection circuit 37, which outputs a high level when the level of the rising differential output in the differentiation circuit 35 exceeds a predetermined value, and is composed of a voltage comparator. , the output of this pulse signal detection circuit 37 is supplied to the flip-flop 26.

In this configuration, when a positive pulse-like portion 24 is included in the input signal in a certain sampling period section T as shown in FIG. stand up and maintain that position. The sudden rise of the output of the positive peak detection circuit 12 is differentiated by the differentiating circuit 35 to generate a positive pulse, and when the peak level of the positive pulse is higher than a predetermined value, the output of the pulse signal detection circuit 37 rises, and this The flip-flop 26 is set by the rising edge. Therefore, the operation thereafter is the same as the conventional circuit shown in FIG.
The peak value of the pulsed portion 24 is sampled and held in this section.

When the input signal rises slowly as shown in FIG. 2B, the output of the positive peak detection circuit 12 rises slowly in response to this, and the output of the differentiator 35 is at almost zero level, so that the pulse signal cannot be detected. The output of the circuit 37 never rises. Even if pulse-like noise is superimposed on the input signal, its peak value is small, so the step width of the step-like rise of the output of the positive peak detection circuit 12 due to the noise is small, and the peak of the output pulse of the differentiating circuit 35 is small. The value is small, and there is no risk that the output of the pulse signal detection circuit 37 will be inverted to a high level due to noise. In order to ensure the distinction between this noise and the pulsed part 24 of the signal, a differentiating circuit 3
It is preferable to provide an amplifier 36 or to provide a gain to the differentiating circuit 35 so as to increase the level difference between the differential pulse due to the signal being outputted by the amplifier 5 and the differential pulse due to noise.

If the discharge time constant of the differentiating circuit 35 is made relatively large, the width of the output differential pulse of the differentiating circuit 35 will be widened, so that even if the voltage comparator used in the pulse signal detecting circuit 37 has a slow response speed, Fully usable.

[0013]

As described above, according to the present invention, the output of the positive peak detection circuit 12 is differentiated, and when the differentiated pulse is above a predetermined level, it is detected as a pulse-like signal. Even when the pulse width is narrow, it can be detected, and only the signal can be detected correctly without being affected by noise, and the signal can be reliably captured without being lost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention.

FIG. 2 is a waveform diagram of each part for explaining detection of a pulsed signal in the embodiment of FIG. 1;

FIG. 3 is a block diagram showing a conventional signal acquisition circuit.

FIG. 4 is a diagram showing waveforms of various parts for explaining the acquisition of a pulsed signal in a conventional signal acquisition circuit.

Claims (1)

[Claims] Claim 1: An input signal is supplied to a positive peak detection circuit and a negative peak detection circuit, each output of these positive peak detection circuit and negative peak detection circuit is switched by a switch and supplied to a sample hold circuit, and the sample hold circuit de1
The input is sampled and held at regular intervals, and the sample of the peak detection circuit is cleared.The output of the sample and hold circuit is compared with the input signal using a slope detector, and the comparison output is used to determine the input signal. When the input signal is larger, the sample and hold circuit is connected to the positive peak detection circuit side, and when the input signal is smaller, the switch is controlled so that it is connected to the negative peak detection circuit side, and the output of the sample and hold circuit is In the signal acquisition circuit that converts the input signal into a digital signal using an AD converter and receives the input signal, there is a differentiating circuit to which the output of the positive peak detection circuit is supplied, and an output of the differentiating circuit is supplied, and the output signal is means for controlling the switch so that the pulse signal detection circuit to be detected and the detection output of the pulse signal detection circuit connect the sample and hold circuit to the positive peak detection circuit side regardless of the output of the slope detector; A signal acquisition circuit characterized by being provided with.