JPH04221498A - Decoder - Google Patents

Abstract

PURPOSE:To highly integrate a decoder by commonly using two of three N- channel type transistors connected in series at a ground side for both NAND dates. CONSTITUTION:Three P-channel type MOS transistors P11, P12, P13 and two P-channel type MOS transistors P14, P15 are connected in parallel, and address data A1, A2 and B1 are input to the gates of the transistors P11, P12, P13 and P14, P15. Three N-channel type MOS transistors N11, N12, N13 are connected to a ground side. 2-input NAND gates are formed of the transistors N12, N13 and the transistors P14, P15, and 3-input NAND gates are formed of the transistors P11, P12, P13 and the transistors N11, N12, N13.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a CMOS-configured NAN
This invention relates to a D-type or NOR-type decoding circuit.

0002

[Prior Art] Mask RO with small memory cell size
In a read-only memory such as M, the arrangement pitch of memory cells is narrow, so it is desired to reduce the pattern area of an address decoding circuit that specifies addresses of memory cells. Particularly, in a memory where the number of addresses has increased as the memory capacity has increased, a decoding circuit that specifies addresses step by step in units of predetermined blocks is employed. This decoding circuit is configured to select and activate memory cells in units of blocks and designate a specific memory cell within the selected block, and is made up of, for example, a combination of a plurality of logic gates that receive address data.

FIG. 4 is a logic circuit diagram showing a part of the above-mentioned decoding circuit, and shows a NAND type case. In this figure, 2+1 bits of address data A1, A2 and B
1 (or B2), two decode outputs D1,
It is configured to output D2.

[0004] Two-bit address data A1 and A2 are input to the first NAND gate (1), and a decode output D1 for selecting memory cells in blocks is produced. Each memory cell block is further divided into a plurality of regions, and each divided region has a first NAND gate (1
) are mapped. By applying the common address data A1 and A2 to the inputs of the first NAND gates (1) corresponding to the divided regions within the same block, each divided region within the same block is simultaneously activated. become.

On the other hand, the second NAND gate (2) has
Address data A1, A2 and this address data A1
, A2 and 1 bit of address data B1 and B2, which are different from each other, are input, and a decode output D2 that specifies one of the divided areas within the same block is created. This second NAND
Although the address data B1 and B2 given to the gate (2) are shown as 2 bits to simplify the drawing, they actually consist of the number of bits corresponding to the number of divided areas in the memory cell block. According to this, each NAND gate (1
)(2) is also provided. Therefore, first and second NAND gates (1) and (2) are provided corresponding to each divided area, and the divided areas within the same block are connected to the first NAND gate.
After being activated based on the decode output D1 of the gate (1), the decode output D2 of the second NAND gate (2)
A specific divided area will be selected according to the following.

FIG. 5 shows the first and second NAND gates (
1) This is a specific circuit diagram of (2), and shows the case of a CMOS configuration.

The first NAND gate (1) with two inputs is as follows:
Two P-channel type MOS transistors (P1) (P
2) and two N-channel MOS transistors (N
1) (N2), with a P-type transistor (P
1) (P2) are connected in parallel, and N-type transistors (N1) (N2) are connected in series to the ground side, and 2 bits are connected to the gates of each transistor (P1) (P2) and (N1) (N2). address data A1 and A2 are input, and a decode output D1 is output from the connection point between the P-type transistors (P1) (P2) and the N-type transistor (N1). Similarly, the second NAND gate (2) with 3 inputs has 3 inputs.
Two P-channel MOS transistors (P3) (P4
) (P5) and three N-channel type MOS transistors (N3) (N4) (N5), with P-type transistors (P3) (P4) (P5) connected in parallel on the power supply side and N-type transistors on the ground side. Transistor (N3) (N4) (N5)
are connected in series to form P-type transistors (P3) (P4)
(P5) and the N-type transistor (N3) are configured so that the decode output D2 is output from the connection point.

[0008]

[Problems to be Solved by the Invention] In the above decoding circuit, the first NAND gate (1) and the second NAND gate (1)
Since the D gates (2) are provided in pairs, the decoding circuit is constructed as one unit of a circuit consisting of five P-type and five N-type transistors as shown in FIG. However, in such a circuit, the address data A1 and A2 are input to the gates of many (4) transistors, so the input load becomes large.
This has the problem of slow operation speed. In particular, due to the increase in the number of addresses, NAN, which constitutes a decoding circuit,
When the number of inputs to the D gate increases, the number of transistors receiving address data increases, so the influence of an increase in input load increases. Furthermore, since the number of transistors constituting the circuit increases, the pattern area of the decoding circuit increases, which is disadvantageous for increasing the capacity of the memory.

Therefore, the present invention aims to reduce the input load, and
The purpose of the present invention is to reduce the number of elements (transistors) constituting the circuit and reduce the pattern area, thereby providing a decoding circuit that is effective for use in large-capacity memories.

0010

[Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems, and the first feature is that n P-channel transistors are connected in parallel on the power supply side. and a first NAND gate in which n N-channel type transistors are connected in series on the ground side to receive n-bit digital data, and m (m>n) on the power supply side.
a second NAND gate in which P-channel transistors are connected in parallel and m N-channel transistors are connected in series on the ground side to receive m-bit digital data including the n-bit digital data; In a NAND type decoding circuit consisting of a combination of
Among the m N-channel transistors of the second NAND gate, n ground-side transistors are commonly used as the n N-channel transistors of the first NAND gate.

The second feature is that n P-channel transistors are connected in series on the power supply side, and n N-channel transistors are connected in parallel on the ground side, so that n-bit digital data can be processed. m (m>n) P-channel transistors are connected in series on the power supply side and m N-channel transistors are connected in parallel on the ground side.
and a second NOR gate that receives m bits of digital data including bits of digital data, the power supply side of the m P-channel transistors of the second NOR gate The n transistors are commonly used as the n P-channel transistors of the first NOR gate.

0012

[Operation] According to the present invention, in a decoding circuit that combines a logic gate having an n-bit input and a logic gate having an m-bit input, a portion of the transistors constituting each logic gate is shared. It becomes possible to reduce n transistors. Therefore, the pattern area is reduced by reducing the number of elements constituting the circuit, and the number of transistors receiving address data is reduced, thereby reducing the input load.

[0013]

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention.
Similar to Figure 5, a 2-input NAND gate and a 3-input NAN
A case of combination with D gate is shown.

[0014] On the power supply side, three P-channel type MOS
Transistors (P11) (P12) (P13) and two P-channel MOS transistors (P14) (P15)
) are connected in parallel, and each P-type transistor (
P11) (P12) (P13) and (P14) (P15
) address data A1, A2, and B1 are input to the gates of the address data A1, A2, and B1. In addition, on the ground side, there are three N-channel type MO
S transistors (N11) (N12) (N13) are connected in series, and each P-type transistor (N11) (N12)
Address data A1, A2 and B are applied to the gate of (N13).
1 is input respectively. And an N-type transistor (
A P-type transistor (P
14) The drain of (P15) is connected, and the first decode output D1 according to address data A1, A2 is output from this connection point. Furthermore, an N-type transistor (N11
) P-type transistors (P11) (P12) at the drains of
(P13) is connected, and a second decode output D2 according to address data A1, A2, and B1 is output from this connection point.

In the decoding circuit as shown in FIG.
Two P-type transistors (P14) (P15) and two N-type transistors (N12) (N13) constitute a two-input NAND gate that receives address data A1, A2, and three P-type transistors (P11) (P12).
(P13) and three N-type transistors (N11) (N
12) (N13) constitutes a three-input NAND gate that receives address data A1, A2, and B1. Regarding the operation of the two-input NAND gate, since either the P-type transistor (P11) or the N-type transistor (N11) is always turned off by the address data B1, the decode output D
2 is obtained. Therefore, decode outputs D1 and D2 matching the logic of FIG. 4 are output in response to input address data A1, A2 and B1.

According to the above configuration, address data A1
, A2 are reduced by one each compared to the case of FIG. 5, and the number of N-type transistors forming the circuit is reduced from five to three. Therefore, the input load is reduced, the operating speed is improved, and the number of circuit elements is reduced to reduce the pattern area.

FIG. 2 is a circuit diagram showing another embodiment of the present invention, in which a 2-input NOR gate and a 3-input NOR gate are combined.

[0018] On the power supply side, three P-channel type MOS
Transistors (P21) (P22) (P23) are connected in series, and the ground side has three N-channel type MOS transistors (N21) (N22) (N23) and two N-channel MOS transistors (N21) (N22) (N23).
Channel type transistors (N24) (N25) are each connected in parallel. Address data A1, A2, and B1 are input to the gates of the P-type and N-type transistors, and the P-type transistors (P21) and (P2
2) N-type transistors (N24) (N25) for connection with
The drain of P2 is connected and the P-type transistor (P2
1) N-type transistors (N21) (N22
) (N23) is connected. Therefore, two P-type transistors (P22) (P23) and two N-type transistors (N24) (N25) constitute a two-input NOR gate that receives address data A1, A2. decode output D1 of
is output, and similarly three P-type transistors (P21)
(P22) (P23) and three N-type transistors (N2
1) Address data A1,
A three-input NOR gate receiving A2 and A3 is configured to output a second decoded output. In such a decoding circuit as well, as in the case of FIG.
One of the type transistors (N21) is always turned off, and the decoded output D2 is output according to the address data A1 and A2 regardless of the address data B1.

In the above embodiment, a case where a two-input logic gate and a three-input logic gate are combined is illustrated, but even in the case of other combinations, in the NAND type, the N-type transistor on the ground side is shared, In the case of the NOR type, the number of transistors in the decoding circuit can be reduced by configuring the circuit so that the P-type transistor on the power supply side is shared. For example, in the case of a combination of a 2-input NAND gate and a 4-input NAND gate, four P-channel MOS transistors (
P31) (P32) (P33) (P34) and two P channel type MOS transistors (P35) (P36) are connected in parallel to the power supply side, respectively, and four N channel type MOS transistors (N31) (N32) (N3
3) Connect (N34) in series to the ground side, and connect the drains of P-type transistors (P35) and (P36) to the connection point of N-type transistors (N32) and (N33) to generate the first decode output D1. and N-type transistor (N3
1) P-type transistors (P31) (P32
) (P33) (P34) to obtain the second decoded output D2, a 4-input NAND
Decode outputs D1 and D2 can be output according to the same logic as when the gate and the two-input NAND gate are configured independently.

[0020]

According to the present invention, in a decoding circuit configured by combining two logic gates, the number of transistors receiving address data is reduced, so the input load is reduced and the operating speed is improved. , the pattern area is reduced due to the reduction in the number of circuit elements. Therefore, the present invention can be used as an address decoding circuit for a large-capacity read-only memory with a narrow arrangement pitch of memory cells, and is effective for high integration. Further, by reducing the input load, it is possible to set the drive capability of the address generation circuit to be low, and in addition to reducing power consumption, it is possible to reduce the circuit scale of peripheral circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a logic circuit diagram of a conventional decoding circuit.

FIG. 5 is a circuit diagram of a conventional decoding circuit.

[Explanation of symbols]

1, 2 NAND gate

Claims (2)

[Claims] 1. A first NAND gate having n P-channel transistors connected in parallel on the power supply side and n N-channel transistors connected in series on the ground side to receive n-bit digital data; m on the power supply side
(m>n) P-channel type transistors are connected in parallel, and m N-channel type transistors are connected in series on the ground side to receive m-bit digital data including the above-mentioned n-bit digital data. In a NAND type decoding circuit formed by combining a NAND gate, n of the m N-channel type transistors of the second NAND gate are connected to the ground side n of the n N-channel transistors of the first NAND gate. A decoding circuit characterized in that it is commonly used as a type transistor. 2. A first NOR gate having n P-channel transistors connected in series on the power supply side and n N-channel transistors connected in parallel on the ground side and receiving n-bit digital data; m (
a second NOR in which m>n) P-channel transistors are connected in series and m N-channel transistors are connected in parallel on the ground side to receive m-bit digital data including the above-mentioned n-bit digital data; In a NOR type decoding circuit comprising a combination of a gate and A decoding circuit characterized in that it is commonly used as a transistor.