JPH04220773A - Memory simulation method - Google Patents

Abstract

PURPOSE:To detect an access exceeding the usable number of words when a memory is to be used within the maximum number of words usable. CONSTITUTION:The case where the memory is accessed with an address and the operation of the memory is simulated, is exemplified. In this case, when the memory is to be used with words below the maximum number of words usable for the address, the address is checked by a means provided for detecting from the address the fact that the maximum number of words usable is exceeded, and a bus fight output is generated when such fact is detected. When the address is 3 bits, for example, up to 8 words are available, and when 7 words are usable as the maximum usable words, the bus fight signal is outputted when 8 words exceeding the 7 words are detected. Thus, whether an error is a conventional error or an access error exceeding the usable number of words, can be distinguished.

Description

[Detailed description of the invention]

(Table of Contents) Industrial Application Fields Conventional Technology Problems that the invention aims to solve Means to solve problems (Figure 1) action Example (a) Description of the first embodiment (Figure 2) (b) Description of the second embodiment (Fig. 3) (c) Description of the third embodiment (Fig. 4) (d) Description of other embodiments Effect of the invention

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating a memory used with less than the maximum number of words.

Semiconductor memories are widely used in data processing devices, including ROM (read only memory),
Various types of memory are used, such as RAM (Random Access Memory) and dual-port RAM. When designing a circuit for such a memory, a program simulation is performed using a computer in order to verify its operation.

[0004] For this reason, a memory simulation model (circuit diagram) is created, inputted into a computer, and simulated on the computer to verify its operation.

[0005] In such a memory, there is a demand for using an address with a number of words less than the maximum number of words, and a simulation method for this purpose is required.

[0006]

2. Description of the Related Art Conventional memory simulation models have only models with a maximum number of words. For example, if the number of addresses is 3, there are 8 words, and there is no simulation model for 5 to 7 words.

[0007]

By the way, when using a memory, it is not always necessary to use it with the maximum number of words, but there is also a demand to use it with less than the maximum number of words depending on the convenience of use.

[0008] In such a case, if a simulation is performed using a conventional simulation model with the maximum number of words, a system error will occur for an access that exceeds the number of words used. The problem was that it was impossible to tell the difference.

Accordingly, an object of the present invention is to provide a memory simulation method capable of detecting accesses exceeding the number of used words.

0010

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle of the present invention.

According to a first aspect of the present invention, there is provided a memory simulation method for simulating memory operation by accessing a memory by an address, which includes: inspecting the address; detecting that the address exceeds the maximum number of words to be used; It is characterized by emitting bass fight output.

[0012] Claim 2 of the present invention provides the following in claim 1:
The memory is a RAM, and upon detecting that the address exceeds the maximum word usage, undefined data is input to the RAM.

[0013] Claim 3 of the present invention provides the following in claim 1:
The memory is a dual port RAM, and the bus fight output is generated upon detecting that two ports access the same address at the same time and that one is writing and the other is reading. .

[0014]

According to claim 1 of the present invention, since it is detected from the address that the maximum number of words used is exceeded and a bus fight output is issued, it is possible to distinguish and detect that the number of words used is exceeded. Therefore, it is possible to clarify the verification results of memory used with less than the maximum number of words used.

[0015] In claim 2 of the present invention, when the memory is a RAM, by inputting the undefined data, the undefined data is outputted from the memory, thereby preventing malfunction of the memory and preventing erroneous errors in simulation. Prevent the consequences.

According to claim 3 of the present invention, when the memory is a dual port RAM, simultaneous accesses of two ports are detected, so simultaneous accesses of both ports can also be detected separately.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (a) Description of the first embodiment FIG. 2 is an explanatory diagram of the first embodiment of the present invention, showing an example in which a RAM is used as the memory and the number of words after the maximum word is 7 words.

In the figure, 1 is a RAM, which has 3 address bits (A0 to A2), 3 data bits (D0 to D2), and R
AM enable RE and write enable WE are given, 2 is a word detection unit, and addresses A0 to A2
, and detects that it is 8 words exceeding the maximum word (7 words), and outputs a low level output. 3 is an undefined data generation unit, and an undefined output is generated by the low level output of the word detection unit 3. The one that outputs XXX, 4 is a bus fight generation section, which outputs Z01 (high level) and Z02 (low level) from drivers D1 and D2 by the low level output of the word detection section 3, and the high level is output by double AND gate AND. 5 is a data selector section that generates a level bus fight output, and word detection section 3
It has an AND gate A which cuts the input data D0 to D2 by the low level output of the AND gate A, and an OR gate R which takes the OR of the output of the AND gate A and the indefinite output XXX of the indefinite data generating section 3.

To explain the operation of this embodiment, at addresses of 1 to 7 words, the output of the word detection section 2 is high level, the output of the bus fight generation section 4 is low level, and undefined data is generated. Section 3 emits a low level output.

Therefore, the AND gate A of the data selector section 5 opens, and the input data D0 to D2 pass through the AND gate A and the OR gate R of the data selector section 5 and are sent to the RAM.
You can input to 1. Therefore, according to addresses A0-A2,
Read/write access to RAM1 is performed.

On the other hand, at an address of 8 words, the output of the word detection section 2 is at a low level (the number of words used has been exceeded).
Therefore, the output of the bus fight generation section 4 becomes a high level (bus fight signal), and the indefinite data generation section 3 issues an indefinite data output.

Therefore, the AND gate A of the data selector section 5 is closed, and the input data D0 to D2 are passed through the AND gate A and the OR gate R of the data selector section 5 to the RAM1.
Input to is prohibited, and undefined data is input to RAM1.

Therefore, at an address of 8 words, a bus fight signal is generated, undefined data is input to RAM1, and undefined data is output from RAM1.

(b) Explanation of the second embodiment FIG. 3 is an explanatory diagram of the second embodiment of the present invention, showing an example in which two single-port RAMs are used as memories and applied as a dual-port RAM. There is.

In the figure, the same parts as shown in FIG.
They are shown with the same symbols, and 1a and 1b are single-port RAMs, each of which has 7 words and 1 bit, common to I and J ports, and 6 is a RAM input control circuit, with RAM enable on the I port side. REIA, write enable WEI, RAM enable REJA on the J port side
, write enable WEJ, address IA on the I port side
0 to IA2, those that receive addresses JB0 to JB2 on the J port side, perform input control, and control RAM1a and 1b.
Reference numerals 7a and 7b each represent an output control circuit, which controls the output of the RAMs 1a and 1b in accordance with a control signal from the RAM input control circuit 6.

The word detection unit 2 performs an AND operation on the addresses IA0 to IA2 on the I port side, ANDs the AND gate A2 for detecting 8 words on the I port side, and the addresses JB0 to JB2 on the J port side. In addition to AND gate A3 that detects 8 words on the port side, R on the I port side
OR gate R1 performs read detection by ORing AM enable REIA and RAM enable REJA on the J port side, ANDs write enable WEI on the I port side and write enable WEJ on the J port side to detect write duplication. AND gate A1, addresses IA0 to IA2 on the I port side, and address JB on the J port side, respectively.
E-OR circuits E1, E2, and E3, which perform exclusive OR with 0 to JB2 and detect address matching, and OR gate R.
1, AND gate A1, E-OR circuit E1, E2, E3
It has an AND gate A4 which takes the AND of the output of the AND gate A4, and an OR gate R2 which takes the OR of the AND gate A4, the AND gate A2, and the AND gate A3, and generates an access abnormal output.

Therefore, the word detection unit 2 uses the AND gate A2 and the AND gate A3 to detect the 8
When a word is detected, an access error output is generated, and if the addresses on the I and J ports match according to the outputs of the E-OR circuits E1, E2, and E3, and both I and J ports are written according to the AND gate A1, an access error occurs. emits an output, I
, the addresses on the J port side match, and the AND gate A1,
OR gate R1 generates an access abnormality output if one of the I and J ports is a write and the other is a read.

The data selector unit 5 receives the I port side write pulse, the access abnormality output of the word detector 2, and
AND gates A5 and A6 which take the AND with the I port side data I0 and the J port side data J0, the respective J port side write pulses, the access abnormal output of the word detection unit 2, the I port side data I0 and the J port side AND gates A7 and A8 take an AND with data J0, AND gates A5 and A6 take an OR of the output of the undefined data generator 3,
It has an OR gate R3 that outputs data to the RAM 1a, and an OR gate R4 that takes the OR of AND gates A7, A8 and the output of the undefined data generating section 3, and outputs the data to the RAM 1b.

Therefore, if the word detection section 2 does not issue a low level access abnormal output, the AND gate A5
~A8 is opened in response to the I port side write pulse and the J port side write pulse, and the I port side data I0 and the J port side data J0 are given to the RAMs 1a and 1b.

On the other hand, when detecting 8 words on the I and J ports,
When the addresses on the I and J ports match and both I and J ports are written, when the addresses on the I and J ports match and at least one of the I and J ports is written, or when one writes and the other reads , the word detection unit 2 issues an access abnormality output.

As a result, the bus fight generation section 4 outputs a bus fight signal, and the undefined data generation section 3 outputs undefined data. For this reason, AND gate A5
~A8 inhibits data input of I port side data I0 and J port side data J0 to RAMs 1a and 1b, and undefined data is input from OR gates R3 and R4 to RAMs 1a and 1b.

In this way, even in the case of a dual-port RAM, the 8 words on the I and J ports are detected, the bus fight signal is output, undefined data is output, and the addresses on the I and J ports are matched. However, if both the I and J ports are writing, the addresses of the I and J ports match, and at least one of the I and J ports is writing, or one is writing and the other is reading.

(c) Description of the third embodiment FIG. 4 is an explanatory diagram of the third embodiment of the present invention, in which two single-port RAMs are used as memories, a dual-port RAM is used, and I,
An example of a J port independent type is shown.

In the figures, the same parts as those shown in FIGS. 2 and 3 are indicated by the same symbols.

Since this example is a dual port RAM with independent I and J ports, two OR gates, R2 on the I side and R5 on the J side, are provided for generating an access abnormal output of the word detection unit 2. According to this, an undefined data generating section 3a on the I side and 3b on the J side are provided, and the bus fight generating section 4 is
An AND gate A9 is provided which takes the AND of the outputs of the OR gates R2 and R5.

Then, the access abnormal output of the I-side OR gate R2 is input to the AND gates A5 and A7 of the data selector section 5, the access abnormal output of the J-side OR gate R5 is input to the AND gates A6 and A8, and the access abnormal output of the J-side OR gate R5 is input to the AND gates A5 and A7. The output of the I-side undefined data generating section 3a is inputted to the I-side undefined data generating section 3a, and the output of the J-side undefined data generating section 3b is inputted to the OR gate R4.

Therefore, the difference from the second embodiment shown in FIG.
Even if the I or J port is for 8 word access, if the J or I port is for 1 to 7 word access, the port for 1 to 7 word access is allowed to access, and the rest is the second embodiment in FIG. There is no difference.

(d) Description of other embodiments In addition to the embodiments described above, the present invention can be modified as follows.

① Although RAM and dual port RAM have been described as examples, the present invention can also be applied to ROM, EPROM, etc.

(2) In the case of ROM and EPROM, since writing is not performed, an indefinite data generation section and a data selector section are not necessary.

(2) Although the memory is configured by a program, it may be an actual hardware memory.

■The maximum number of words was explained using 8 words, but
Other word counts may also be used.

The present invention has been explained above using examples, but
Various modifications are possible within the scope of the present invention, and these are not excluded from the scope of the present invention.

[0044]

[Effects of the Invention] As explained above, according to the present invention,
It has the following effects.

(2) It is detected from the address that the maximum number of words used is exceeded, and a bus fight output is issued, so that it is possible to distinguish and detect that the number of words used is exceeded in simulation. Therefore, it is possible to clarify the verification results of memory used with less than the maximum number of words used.

(2) Since the user does not need to be aware of extra addresses, system errors etc. during simulation can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is an explanatory diagram of a first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a third embodiment of the present invention.

[Explanation of symbols]

1 Memory 2 Word detection section 3 Undefined data generation part 4. Bus fight occurrence area 5 Data selector section

Claims (3)

[Claims] Claim 1: In a memory simulation method for simulating memory operation by accessing memory by an address, the method includes inspecting the address, detecting that the address exceeds the maximum number of words used, and generating a bus fight output. A memory simulation method featuring: 2. The memory is a RAM, and upon detecting that the address exceeds the maximum word usage, the R
Claim 1 characterized in that indefinite data is input to AM.
A memory simulation control method. 3. The memory is a dual-port RAM, and the bus fight output is generated by detecting that two ports access the same address at the same time and that one is writing simultaneously or one is reading and the other is writing. The memory simulation method according to claim 1, characterized in that: