JPH04220031A - Serial data transmitting system and serial data receiving system - Google Patents

Abstract

PURPOSE:To simplify a controller by utilizing the conversion and reverse conversion of a synchronous code as well as of the fixed pieces unit of bit information to positive and negative extreme values. CONSTITUTION:When the fixed pieces of bit information are transmitted, the extreme value of the bit information is reversed and the bit information and a reversed bit information are made to a pair. This pair of indicated as a bit pair by a conversion rule. The synchronous code of a bit pair sequence is not appeared at the time when the fixed pieces of the bit information is required to convert. But the synchronous code is transmitted by this system and each of the bit pairs is transmitted in a predetermined order following the transmission of the synchronous code. Thus, the transmitter is simplified.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transmission system and a serial data reception system that can transmit and receive data without requiring complicated control. In data transmission, in addition to the transmission of normal information data, it is necessary to transmit control data and the like. Unlike normal information data, the latter data transmission may be a predetermined number depending on the system, device, etc. Even in such a case, it is not necessarily necessary to transmit control data and the like using the same data transmission method as that for information data. In this case as well, it is not a good idea to adopt a data transmission method for information data in which the amount of data is variable.

0002

2. Description of the Related Art Conventional data transmission methods for transmitting information data include a start-stop synchronization method, a synchronous synchronization method, a flag synchronization method, and the like. These information data transmission methods are under firmware control. The synchronous type uses a code of 16 or 32 in hexadecimal for synchronous control, and the flag synchronous type uses a predetermined pattern (for example, 7E in hexadecimal) for synchronous control. be.

0003

The conventional data transmission method described above requires control by firmware. Therefore, it is possible to easily cope with changes in the amount of data, but on the other hand, the transmission system or device itself becomes complicated and expensive. Therefore, data transmission is expensive. The present invention was created in view of such problems, and provides a serial data transmission method and serial data reception that can transmit data at low cost while simplifying control of data transmission with a simple hardware configuration. Its purpose is to provide a method.

0004

Means for Solving the Problems FIG. 1 is an explanatory diagram of the invention according to claims 1 and 2. In the invention according to claim 1, when transmitting a certain number of bit information, the polarity of the bit information is inverted, the bit information and the inverted bit information of the bit information are paired, and the polarity is expressed by the conversion rule. transmitting a synchronization code of bit pairs, the bit pair sequence not appearing when converting the fixed number of bit information, and transmitting each of the bit pairs in a predetermined order subsequent to the transmission of the synchronization code; It is characterized by

The invention according to claim 2 detects a synchronization code of a bit pair sequence that does not appear when a certain number of bit information is converted, which is a bit pair of bit information and inverted bit information of the bit information, In response to the detection of the synchronization code, a fixed number of bit pairs represented by positive and negative polarities following the synchronization code are extracted in the same order as the transmission order, and each bit pair correspondence is extracted from the extracted fixed number of bit pairs. It is characterized by receiving bit information of.

[0006]

[Operation] When transmitting a certain number of bit information, each of those bit information is converted into a bit pair of the bit information and the inverted bit information of the bit information. The bit pairs are then transmitted in a predetermined order after the synchronization code is transmitted. Also, when receiving a certain number of bits of information transmitted in this way, first the synchronization code is detected. In response to this detection, each bit pair following the synchronization code is extracted in the same order as the transmission order, and each of the bit pairs is received as bit information prearranged between the transmitting side and the receiving side. .

As described above, in transmitting and receiving a certain number of bit information, each bit information is converted into a bit pair corresponding to each bit information, and a synchronization code and the converted bits are sent in a predetermined order. The fixed number of bits of information can be transmitted by simply controlling the pair of transmissions. In addition, upon receiving the synchronization code and the fixed number of bit pairs transmitted in this way, the detection of the synchronization code, the extraction of the fixed number of bit pairs in response to the detection, and the extraction of the fixed number of bit pairs are performed. The fixed number of bit information can be received by simply controlling the reception of bit information corresponding to each bit pair from the number of bit pairs. Therefore, simple hardware is sufficient for both transmitting the fixed number of bit information and receiving the fixed number of bit information. This means that its control can also be simple. In other words, this contributes to the simplification of the circuit configuration or the simplification of the firmware when the present invention is constructed using firmware, and also reduces the burden on the control device. Therefore, information transmission costs can be gradually reduced.

[0008]

Embodiment FIG. 2 shows an embodiment of the invention according to claim 1. FIG. 3 shows an embodiment of the invention according to claim 2. In these embodiments, the controller 22 connects to the remotely controlled device 2 via a first signal line 24 and a second signal line 26.
8, and the control device 22 is connected to the first signal line 2.
This is an example in which the controlled device 28 is controlled through step 4 and the state of the controlled device 28 is monitored.

The control device 22 has a 3-bit counter (CN
T) 30, synchronous code output section 32, driver gate circuit 34, data registers (SDR0 to SDR4) 36 to 44, driver gate circuits 46 to 54, transmission data register 66, transmission shift register 68, and clock pulse generator 76 Become. The 3-bit counter 30 is
A clock pulse P1 having a period of 833×10 μs is supplied. The count value from the counter 32 is supplied to the driver gate circuit 34 and the data registers 36 to 44. Data registers 36-44 are supplied with control bit information from a control processor (not shown) of controller 22. The data registers 36 to 44
outputs bit pairs represented by positive and negative polarities for each control bit information, as shown in FIG. 4, respectively. According to claim 1, changing the control bit information in this way
This corresponds to the "conversion rule for converting into a bit pair represented by positive and negative polarities according to the value of bit information" described in claim 2. By doing so, it is possible to prevent more than three signals having the same signal level from being transmitted. Each of these outputs is input to a transmit data register 66 via a corresponding driver gate circuit 46-54. This transmission data register 66 also includes the driver gate circuit 3.
4, a synchronization code 0F (value expressed in hexadecimal) is input. The bit pair sequence of this synchronization code 0F (value expressed in hexadecimal) is a bit pair expressed by the above-mentioned conversion rule, and contains a certain number of bit information shown in (1), (3), etc. in FIG. This is a bit pair sequence that does not appear when converted, and the conversion rule is used to obtain this bit pair sequence. The output of transmit data register 66 is provided to the input of data bit section 72 of transmit shift register 68 . The transmission shift register 68 has a start bit section 70 and a stop bit section 74. The transmission shift register 68 receives a clock pulse P2 having a period of 833 μs from the clock pulse generator 76.

The controlled device 28 includes a receiving shift register 8
0, clock pulse generator 88, 3-bit counter (C
NT) 92, a synchronization code output section 94, a comparison circuit 96, and bit output registers (RDR0 to RDR4) 98 to 106. The reception shift register 80 receives a clock pulse P3 having a period of 833 μs from the clock pulse generator 88 (the period of the clock pulse P3 is the same as that of the clock pattern P2). The 3-bit counter 92 receives a clock pulse P4 with a period of 833 × 10 μs (the period of the clock pulse P4 is
It has the same period as the clock pattern P1. ). Comparison circuit 96 and bit output registers 98 to 106 are supplied with the count value from counter 92. Counter 92 operates in response to a match output from comparison circuit 96. Bit output registers 98-10
6 is configured as shown in FIG. Its output is
For data reception, only one is used. However, both are used to check received data. Each output of the bit output registers 98 to 106 is output to the controlled device 2.
It is connected to the controlled target section of 8.

The transmission and reception operations of the present invention under the configuration in which data is transmitted from the control device 22 to the controlled device 28 described above will be explained below. For convenience of explanation, control device 2
As an example of controlling the controlled device 28 by the control device 22,
As the control bit information transmitted from
r OFF ) instruction [abbreviation POF ], power on (Po
wer ON) instruction [abbreviation PON], EPO instruction [
[Abbreviation EPO], Connection instruction [Abbreviation SEL], Voltage margin instruction (Upper) [Abbreviation VMGNU], and Voltage margin instruction (Lower) [Abbreviation VMGNL]
shall be.

Each control bit information mentioned above is transmitted to the control device 22.
When transmitting data from the control device 22 to the controlled device 28,
It is assumed that the data registers 36 and 40 are set from the control processing device (see SDR0, SDR1, etc. in FIG. 8). Since the configurations of the data registers 36 and 40 are as explained with reference to FIG. 4, the signal states appearing at the outputs of the data registers 36 and 40 are as shown in (1) in FIG.
and (3). data register 38,
The outputs of 42 and 44 have no meaning as far as this example is concerned. The sets of control bit information set in the data registers 36 to 44 are referred to as transmission data #0 to #5. Those transmission data (SD) are the numbers in parentheses (0) in Figure 7.
Corresponds to (5). Note that this relationship also applies to the case of transmission from the controlled device 28 to the control device 22, and these transmission data are indicated by the numbers in parentheses (10
) to (15).

The counter 30 counts up in response to the first clock pulse P1 after this set is completed. The clock pulse P1 has a transmission rate of 1200 on the second signal line 24 and the second signal line 26.
bps, it is a pulse with a period of 833×10 μs. The all-0 value of the counter 30 first enables the driver gate circuit 34 to output the synchronization code from the synchronization code output section 32 (the first
(receiving the th clock pulse P1) is set in the transmission data register 66. Then, at the first clock pulse P1, the synchronization code of the transmission data register 66 is set in the data bit section 72 of the transmission shift register 68, while at the first clock pulse P1, the value of the counter 30 is " It is counted up to 1”.

When the output contents of the data register 36 are set in the transmission data register 66, the synchronization code set in the data bit section 72 of the transmission shift register 68 is stored in the start bit section 70 and the stop bit section 74. As mentioned above, the set start bit is the clock pulse P2 with a period of 833 μs.
After being shifted out, the bits at each bit position are sequentially shifted out using the clock pulse P2 described above (see (1) and (2) in Figure 8), and after the synchronization code is shifted out, the stop bit is also shifted out. It is shifted out with the clock pulse P2 and transmitted to the controlled device 28 (see (1) in FIG. 8).

When all the bits of this transmission shift register 68 have been shifted out, that is, when the first data transmission period T0 ends, the second clock pulse P1 to the counter 30 is generated. , the counter 30 counts up to "2". This second clock pulse P1 is the first clock pulse P1.
The value “1” of the counter 30 counted up by
However, this is enabled in the driver gate circuit 46 and the data shown in (1) in FIG. do. In this way, the transmission operation of the data set in the transmission data register 66 to the controlled device 28 (the transmission operation within the second data transmission period T1) is the same as that described for the synchronization code. Then, the next data transmission period T2 is an invalid data transmission period in this embodiment (see (2) in FIG. 7). Data transmission period T
In this embodiment, the transmission data in step 3 is as shown in (3) in FIG. The transmission operation for this data is also the same as described above. The data transmission period T4 and the data transmission period T5 are (4) in FIG.
As shown in (5) and (5), this is an invalid data transmission period in this embodiment. From the controller 22 to the controlled device 28 as described above.
The operation of receiving data transmitted to the controlled device 28 by the controlled device 28 will be explained.

The bit-serial transmission data (see (1) and (4) in FIG. 9) received by the controlled device 28 is sent to the first clock pulse generation circuit (BCNT) 88 as reception data (RD). clock pulse P from
3 (The period is the same as clock pulse P2.)
(See (2) in FIG. 9), the signals are sequentially shifted into the reception shift register 80. The transmitted bits are sampled at every sampling time (8/16) during the shift-in (see (2) and (3) in FIG. 9).

Detection of a start bit by the start bit detection section 79 (see (3) in FIG. 9) causes the start bit and each bit of the control bit information following it to be shifted into the data bit section 84. (See (4) and (5) in Figure 9). Start bit detection section 7
Upon detection of the start bit by 9, the data bit section 84
The data (synchronization code) [see (0) in FIG.
is the same as ) is generated within the data reception period T0. The data set in the reception parallel register 90 and the synchronization code from the synchronization code output section 94 are
A comparison circuit 96 compares the signals. This comparator circuit 96 is supplied with all 0 values from the counter 92. That is, comparison circuit 96 is enabled (addressed) to perform a comparison operation. When a match is obtained between the two, a match signal DETOF is sent to the comparator circuit 96.
is output from. In response to the coincidence signal DETOF, the counter 92 starts counting up every clock pulse P4.

During the data reception period T1 following the data reception period T0, the next data, ie, (2) in FIG.
) data is received. This data is invalid data considering the above. Since this is a matter determined in the design of the transmission/reception system of the controlled device 28, the controlled device 28 performs invalidation processing on the received data.

In the next data reception period T2, valid data is received. The data is (3) in FIG. 7, and its receiving operation is exactly the same as the synchronization code receiving operation described above. Thereafter, the operation of receiving each data is repeated in the same manner. The reception status is shown in (8) to (15) in FIG. Each piece of data in the above example is shaded and corresponds to OF and #0 to #5. #6 and #7 are not used in the above example, so they are not shaded.

In contrast to the control bit information transmitted to the controlled device 28 as described above, the monitoring bit information as described above is transmitted from the controlled device 28 to the control device 22 via the second signal line 26. The sending and receiving operations in this case are also carried out in the same manner as described above. Its hardware configuration includes the aforementioned control device 22 and controlled device 28.
A configuration is used in which the transmitting device is the receiving device and the receiving device is the transmitting device. An example of the monitoring bit information is shown below. Further, as shown in FIG. 6, the monitoring bit information returned from the controlled device 28 in response to the control bit information sent from the control device 22 to the controlled device 28 includes fan abnormality (FAN Alarm) [abbreviation FANAL]
, Connection completed [abbreviation CNCT], Terminal status [abbreviation LCL]
], Power abnormality (Power Alarm) [abbreviation PO
WAL ], Power Ready
) [abbreviation RDY], controlled device error [abbreviation SERR]
, Panel Enable [abbreviation PENBL], Control system error (A-B Control Error)
) [abbreviation DERR], and the transmission data in this example is shown in (10) to (15) in FIG. If you refer to the above explanation in which (10) to (15) in FIG. 7 correspond to (0) to (5) in FIG. 7, it will become obvious, so a detailed explanation thereof will be omitted. .

Note that the first signal line 2 in the above embodiment
4 and the second signal line 26 are merely examples, and the number of constituent bits and the number of information of the synchronization code that can be included in one transmission period and one reception period are also the same. Furthermore, the structure of the synchronization code is not necessarily limited to the above-mentioned bit structure (however,
Excludes 00 and FF in hexadecimal display. ), will also be clear to those skilled in the art. Furthermore, the conversion of information bits into positive and negative polarities and the inverse conversion thereof do not have to be the configurations shown in FIGS. 4 and 5.

[0022]

[Effects of the Invention] As explained above, according to the present invention, since the conversion of a synchronization code and a certain number of information bits into positive and negative polarities, and the inverse conversion thereof, This contributes to the simplification of firmware and reduces the burden on control equipment. Therefore, information transmission costs can be gradually reduced.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the invention according to claims 1 and 2.

FIG. 2 is a diagram showing an embodiment of the invention according to claim 1.

FIG. 3 is a diagram showing an embodiment of the invention according to claim 2.

FIG. 4 is a diagram showing a data register.

FIG. 5 is a diagram showing a bit output register.

FIG. 6 is a diagram showing an example of control bit information and monitoring bit information.

FIG. 7 is a diagram showing a specific configuration example of control bit information and monitoring bit information.

FIG. 8 is a diagram showing an example of a transmission timing chart.

FIG. 9 is a diagram showing an example of a reception timing chart.

FIG. 10 is a diagram showing an example of a reception timing chart.

[Explanation of symbols]

22 Control device 28 Controlled device 30 3-bit counter 32 Synchronization code output unit 34 Driver gate circuits 36 to 44 Data registers 46 to 54 Driver driver gate circuit 66
Transmission data register 68 Transmission shift register 76 Clock pulse generator 88 Clock pulse generator 90 Reception parallel register 92 3-bit counter 94 Synchronization code output section 96 Comparison circuit

Claims (2)

[Claims] [Claim 1] When transmitting a certain number of bits of information,
The polarity of the bit information is inverted, the bit information and the inverted bit information of the bit information are paired, and a bit pair (1) is formed, which is the bit pair that appears when the certain number of bit information is converted. transmitting (2) a synchronization code of a sequence of bit pairs with no sequence of bits, and transmitting each of said bit pairs in a predetermined order subsequent to the transmission of said synchronization code (
3) A serial data transmission method characterized by the following. 2. Detecting a synchronization code of a bit pair sequence that is a bit pair of bit information and inverted bit information of the bit information and that does not appear when a certain number of bit information is converted (4), In response to the detection of the synchronization code, a fixed number of bit pairs represented by positive and negative polarities following the synchronization code are extracted in the same order as the transmission order (5), and each bit pair correspondence is extracted from the extracted fixed number of bit pairs. (6) A serial data reception method characterized by receiving bit information of (6).