JP3216145B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system for performing high-speed data transfer (also called transmission) using a signal line.

[0002]

2. Description of the Related Art Data transfer is generally performed over long distances, and wiring costs occupy the largest weight. Therefore, even if other costs are incurred for reducing the number of wirings, the cost is often reduced. 2. Description of the Related Art Conventionally, there are the following methods as a data transfer device for transferring data through one or two signal lines.

The first method is called a start-stop synchronization method. In this transmission method, a start bit is added at the beginning of each character and a stop bit is added at the end, and bit synchronization is performed for each character. Data can be transferred using one signal line. FIG. 10 exemplifies a state of a signal line when data transfer is performed in a start-stop synchronization system. In this figure, a start bit is transmitted from a transmission side to a reception side to start transmission of data bits on the transmission side. The sampling start timing of the data bits on the receiving side is adjusted. In this case, it is necessary to adjust the sending clock of the data bits on the transmitting side and the sampling clock (for example, a clock having a cycle 16 times the transmission speed) on the receiving side to have the same frequency. To transmit 8-bit data, the start bit is 1 bit,
It requires a total of 10 clocks, 8 bits for data bits and 1 bit for stop bits. As described above, two bits of the start bit and the stop bit are added before and after the transmission of an n-bit length character, and the time required to transmit one character is equal to the case where the actual character is transmitted. Longer than Therefore, the effective transmission speed becomes slower, but only one signal line is required.

[0004] A second method is a non-synchronization confirmation method in which two signal lines, a data line and a control line, are used to simultaneously output a data signal and a clock signal. FIG. 11 is a diagram showing a state of a signal line when data transfer is performed by this method. In this example, one signal line is used for transmitting a data signal, and the other signal line is used for transmitting a clock signal. The receiving side receives data by sampling the data signal in accordance with a given clock. To transfer 8-bit data in this manner, eight clocks are required.

[0005]

However, in such a conventional data transfer apparatus, the first method (start-stop synchronization type) requires only one signal line, but the transmission side and the reception side have a single signal line. Since the data bits cannot be transferred accurately unless they are exactly adjusted, it is necessary to have a high-precision clock on both the transmitting side and the receiving side. In the second method, although no clock is required on the receiving side,
One signal line is used as a control signal line dedicated to a clock, and there is a problem that efficiency is deteriorated when data is transferred through about two signal lines. That is, in order to transfer data at high speed with one signal line, the frequency of the transfer clock may be increased in the start-stop synchronization method, but there is an upper limit of the frequency due to the characteristics of the signal line. To transfer data even faster than this upper limit, the number of signal lines must be two. If the above-mentioned second method is used when two signal lines are used, one signal line is used exclusively for the clock. As is clear from the example, the speed improvement is only about 10 to 8. However, if the number of data signal lines is further increased, the ratio of the clock signal to the entire signal is relatively reduced, so that the transfer efficiency is improved.

As described above, the start-stop synchronous method has a great merit that the cost for transmission is low because only one signal line is required, but it is difficult to increase the transmission speed. At present, it is impossible to improve the transmission speed so much even with two signal lines. This is considered to be due to the fact that the transmission method of the conventional data transfer method using the clock signal and the data signal is approaching the limit in principle. Thus, instead of simply transmitting a clock signal and a data signal using two signal lines, if these signals are changed to a predetermined signal state and then transmitted, two signal lines are used. It is clear that faster data transmission can be achieved by using. It is an object of the present invention to enable higher-speed data transfer using two signal lines connecting a transmitting side and a receiving side.

[0007]

The means of the present invention are as follows. (1) Two signal lines connecting the transmitting side and the receiving side are used, and four types of states can be expressed by combining ON and OFF of the two signal lines, and four types of states by the combination of ON and OFF. Data is transferred by changing the signal line to three types of states other than the current state. For example,
The combination of "1" and "0" of two signal lines is (0,0)
(0,1) (1,0) (1,1) Four types of states can be expressed. Here, if the state of the signal line always changes in each clock for transferring data, the receiving side monitors the two signal lines, and captures the data at the timing when a change in any one of the signal lines is detected. In this case, an independent clock signal is not required. (2) By associating the changes to the three types of states except the current state with the values displayed in ternary numbers, one change in the state of the signal line represents one digit of the ternary number. I do. For example, the state of the signal line is always changed to three of the four states except the current state.
By associating “0”, “1”, and “2” with the state of the type, information of one digit of a ternary number can be expressed by one change.

[0008]

The operation of the means of the present invention is as follows. On the transmitting side, a set of binary data (for example, 16 bits or 8 bits) to be transferred is first converted into a ternary number, and the state of the signal line is changed according to each digit value (0 to 2) of the ternary number. In this way, the receiving side waits for a change in the state of the signal line, and when a change is detected, receives information of one digit of a ternary number (0 to 2) from the relationship between the state before and after the change and receives 1 When a ternary number having the number of digits corresponding to the set of data is received, it is converted to a binary number. Therefore, higher-speed data transfer can be performed using two signal lines.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS.
You.Principle explanation  First, the basic principle of the data transfer method will be described. Figure 1 to Figure
FIG. 3 is a state diagram for explaining details of the data transfer method.
You. FIG. 1 shows four types of states that can be represented by two signal lines.
In the figure, “0” and “1” represent the logical values of the signals.
are doing. With the combination of "1" and "0" of two signal lines
(0,0) (0,1) (1,0) (1,1)
State can be expressed. In this case, transfer the data
The state of the signal line always changes at each clock
If so, the receiving side monitors the two signal lines and either
Data is captured at the timing when the change of the signal line of
The need for an independent clock signal
Focusing on, the state of the signal line
Be sure to change to the three states except the state,
If you associate "0" "1" "2" with the state, one change
Can represent information of one digit of a ternary number.

FIG. 2 is a diagram for explaining how transfer data is expressed using the above four types of states. Here, point A in FIG. 2 indicates the state of the signal line at a certain point in time.
"0", "1" and "2" correspond to each other in a counterclockwise direction as shown in FIG. Express information. That is, data to be transferred is represented by a change in the state of the signal line. The numerical values that can be expressed here are three values of “0”, “1”, and “2”, so that one digit of a ternary number is transferred by one state change. In addition, since the information is expressed by changing the signal line to a state other than the current state, the receiving side monitors the two signal lines and captures the data at a timing when a change in any one of the signal lines is detected. What should I do? In this data transfer method, based on these ideas, the binary data to be transferred on the transmitting side is converted into a ternary number, the data is transferred by the above-described method, and the received ternary number is changed to a binary number on the receiving side. Thus, data transfer is performed.

FIG. 3 is a diagram for explaining an example of data transfer, in which black circles indicate the state of signal lines. FIG.
In FIG. 7, the initial state is (0, 0), and the state changes when data is output in order from the upper digit of the ternary number. Now, the transfer data is represented by an 8-digit binary number (11000
001) ₂ . When this is changed to a ternary number, the transfer data becomes (021011) ₃ . In this case, the number of digits of the ternary number is set to 6 digits so that a 1-byte integer (up to 255) can be represented.

An embodiment will be described below based on the above basic principle. FIG.
9 show an embodiment of the data transfer method. First, the configuration will be described. FIG. 4 is an overall configuration diagram of the data transfer device. In this figure, reference numeral 11 denotes two signal lines D1,
A transmitting circuit 12 for changing the state of D2, and signal lines D1, D
And a receiving circuit 13 for converting a ternary number having the number of digits corresponding to a set of data received into a binary number based on the change in the state of 2. The transmission circuit 12 includes a binary register 21 for storing 1-byte transmission data SD, and a binary / ternary conversion circuit 22 for converting binary data to ternary data.
And a ternary register 23 for storing the converted ternary data
A current value register 24 for holding the current state of the signal lines D1 and D2;
A data transmission unit 25 for transmitting transmission data to the signal lines D1 and D2 in accordance with the value of one digit of the radix;
The circuit 13 includes a binary / ternary conversion circuit 22 and a transmission control section 26 for controlling the data transmission section 25 in accordance with the write signal. Value register 27 that holds
A data receiving unit 28 that detects a change in the signal lines D1 and D2 based on the output of the current value register 27 and the state of the signal lines D1 and D2 and receives ternary received data, and stores the received ternary data A ternary register 29, a ternary / binary conversion circuit 30 for converting ternary data into binary data, and storing the converted binary data and outputting it as received data.
It comprises a binary register 31 and a receiving unit 32 that controls the data receiving unit 28 and the ternary / binary conversion circuit 30 according to the Reset signal and the Read signal.

The binary / ternary conversion circuit 22 of the transmission circuit (transmission unit) 12 is for converting the value of the binary register 21 storing the 1-byte transmission data SD into a ternary number. , And the conversion result is stored in the ternary register 23. The current value register 24 holds the current state of the signal lines D1 and D2. Further, the data transmission unit 25 sequentially extracts the value of each digit of the ternary number stored in the ternary register 23, and changes the state of the next signal line according to the value of the current value register 24 and the value of one digit of the ternary number. The value is output to the signal lines D1 and D2, and the value of the current value register 24 is updated.
The transmission control unit 26 controls the entire transmission unit. The transmission control unit 26 initializes each unit of the transmission circuit 12, and sets a reset signal for resetting the value of the current value register 24 to an initial value. A Write signal for instructing the start of transmission of the transmission data SD is input, and the transmission control unit 26 outputs the TxRdy signal indicating that the data transmission instructed by the Write signal ends and the next transmission is possible. You. On the other hand, the current value register 27 of the receiving circuit (receiving unit) 13 stores the signal lines D1,
The state of D2 is maintained. The data receiving unit 28 obtains one-digit ternary received data according to the value of the current value register 27 and the value of the signal line after the change, and updates the value of the current value register 27. The ternary register 29 is for sequentially storing the received one-digit ternary number, and the ternary / binary conversion circuit 30 converts the ternary number corresponding to one byte stored in the ternary register 29 into a binary number. And the result of the conversion is stored in the binary register 31. The reception control unit 32 controls the entire reception unit. A Reset signal input to the reception control unit 32 initializes each unit of the reception unit and sets the value of the current value register 27 to an initial value. The RxRdy signal output from the receiving side control unit 32 is a signal indicating that 1-byte data has been received,
Indicates that the received data RD is valid. Also, Rea
The d signal is a signal for notifying the circuit that the reception data RD has been read, and the RxRdy signal is
FF is performed.

Next, the operation of this embodiment will be described. Data Transmission Operation FIG. 5 is a flowchart of the data transmission operation of the transmission circuit 12, in which Sn (n = 1, 2,...) Indicates each step of the flow. First, in step S1, a Reset signal is input to the transmission control unit 26 to initialize the transmission circuit 12, and in step S2, it indicates that the previous data transmission indicated by the Write signal has been completed and the next transmission is possible. It is determined whether or not the TxRdy signal is ON. If the TxRdy signal is ON, one byte of transmission data SD is set in the binary register 21 in step S3. Next, in step S4, the transmission control unit 26 controls the data transmission unit 25 with a Write signal instructing the start of transmission of the transmission data SD to activate data transmission. Next, in step S5, it is determined whether or not the transfer data has ended. If the transfer data has ended, the transfer data setting process ends. If the transfer data has not ended, the process returns to step S2 and the next TxRdy signal is turned on. Wait until

When the data transmission section 25 is started by the Write signal in step S4, the transmission circuit 12 executes the transmission start processing shown in steps S11 to S19. When the transmission start process starts, step S1
In step 1, the TxRdy signal is turned off, and step S12 is performed.
Then, the value of the binary register 21 is converted into a ternary number by the binary / ternary conversion circuit 22, and the conversion result is set in the ternary register 23. Next, in step S13, the value of the upper two bits of the ternary number stored in the ternary register 23 is taken out and set to W, and in step S14, the value of the ternary register 23 is shifted upward by 2 bits. That is, as shown in FIG.
The hexadecimal number is converted into a 6-digit ternary number and stored in the ternary register 23. Each bit of the ternary register 23 is 2
bit by the third ternary ^5, 3 ^{4, 3} 3, 3 ^2, 3 ^1, 3 corresponding to each digit of ^0. The upper one digit of each digit of the ternary number is stored as a register value W in a work register (not shown), and thereafter the value of the ternary register 23 is shifted upward by 2 bits in order to sequentially retrieve the value of each digit. Shift. Then
In step S15, the register value W for one digit of the ternary number is added to the value of the current value register 24 and stored in the current value register 24 (current value register ← current value register +
W) to determine the state of the next signal line. Then
In step S16, the value of the current value register 24 is incremented (current value register ← current value register + 1), and in step S17, the current value register 2 indicating the state of the next signal line
The value of 4 is output to the signal lines D1 and D2 (see FIG. 6). Next, at step S18, it is determined whether or not all the digits (that is, six digits) of the ternary register 23 have been completed. The states of the signal lines D1 and D2 are changed for all the digits of the ternary register 23. 6
When all the digits have been completed, it is determined that the data transmission indicated by the Write signal has been completed and the next transmission is possible, and the TxRdy signal is turned on in step S19 to terminate the transmission process for one byte.

The data receiving operation Figure 7 is a flowchart of a data receiving operation of the receiving circuit 13, the received data reading process shown in step S21 to S25, the reception indicated by the read completion process and steps S41~S51 shown in step S31 It consists of a start process. First, in step S21, the reception control unit 32
The reset signal is input to initialize the receiving circuit 13, and it is determined in step S22 whether the RxRdy signal indicating that one byte of data has been received is ON. Here, the RxRdy signal is turned on after the reception of one byte of data is completed in step S51 described later. When the RxRdy signal is turned on, the received data SD is continuously supplied from the data receiving unit 28 in step S23, and completion of data reading is notified by a Read signal for transmitting reading of the received data SD in step S24. Next, in step S25, it is determined whether or not the transfer data is completed. If the transfer data is completed, the reception processing of the transfer data is completed. If the transfer data is not completed, the process returns to step S22 to return to the next RxRdy signal. Wait until is turned ON. On the other hand, when the Read signal is notified to the reception control unit 32 in step S24, it is determined that the reading of the predetermined reception data RD has been completed, and in step S31 the Rx
The Rdy signal is turned off and the process ends.

On the other hand, the reception start process includes steps S41 to S41.
51 is executed. The receiving side waits for a change in the state of the signal lines D1 and D2.
2 is detected, and the values of the signal lines D1 and D2 are stored in the work register in step S42. Note that the signal lines D1,
The process of detecting a change in D2 will be described later with reference to FIG. Next, in step S43, the value W of the work register is transferred to the register WS (WS ← W), and in step S44, the previous data reception from the value W of the work register in which the current values of the signal lines D1, D2 are stored. The current value register 27 holding the states of the signal lines D1 and D2 at the time is subtracted and the subtracted value is stored in the work register W (W ← W-current value register). Next, in step S45, the value W of the work register is decremented (W ← W−1). That is,
As shown in FIG. 8, the value of the current value register 27 and the signal line D
1 and D2 are compared with each other to detect a change in the signal lines D1 and D2.
And the value of the signal line after the change stored in the register W, the received data of one digit ternary number is obtained. Then
In step S46, the value of the ternary register 29 is shifted upward by 2 bits.
The value of the register W is set in the lower two bits of the register WS, and the value of the register WS is transferred to the current value register 27 in step S48 (current value register ← WS). Next, step S4
9 to determine whether all six digits have been completed. If the six digits have been completed, it is determined that a ternary number having the number of digits corresponding to one set of data has been received. The value is converted to a binary number and set in the binary register 31.
That is, as shown in FIG. 8, when a change in the state of the signal lines D1 and D2 is detected, data of one digit of a ternary number (0 to 2) is stored in the ternary register 29 based on the state before and after the change. When a ternary number having the number of digits corresponding to one set of data to be sequentially stored and received is received, the ternary numbers 3 ⁵ , 3 ⁴ , 3 ³ , 3 corresponding to one byte received by the ternary / binary conversion circuit 30 are received. ² ,
3 ¹ and 3 ⁰ are converted to binary numbers, and the conversion result is stored in a binary register 3
1 is stored. Next, at step S51, R
The xRdy signal is turned on, and the process returns to step S41.

FIG. 9 is a flowchart showing an operation of detecting a change in the signal lines D1 and D2 by the receiving circuit 13. This flow corresponds to step S41 in FIG. First, in step S61, the values of the signal lines D1 and D2 are stored in the work register W. In step S62, the value W is stored in the current value register 27 which holds the state of the signal lines D1 and D2 at the time of the previous data reception. It is determined whether the value is equal to the value (W = current value register). If W is equal to the value of the current value register 27, it is determined that there is no change in the signal lines D1 and D2, and step S is executed.
Returning to step 61, when W is not equal to the value of the current value register 27, it is determined that the state of the signal lines D1 and D2 has changed, and a predetermined delay is given to the data received in step S63. That is, to avoid malfunction due to noise,
In order to avoid receiving erroneous data due to a minute shift in the timing at which the two signal lines change, DELA is used.
Y is used. Next, the values of the signal lines D1 and D2 after the delay is given in step S64 are stored in the work register W.
At step S65, it is determined whether or not this value W is equal to the value of the current value register 27 holding the state of the signal lines D1 and D2 at the time of the previous data reception (W = current value register). I do. When W is equal to the value of the current value register 27, it is determined that the signal lines D1 and D2 have not changed, and the process returns to step S61. When W and the value of the current value register 27 are not equal, the signal lines D1 and D2 It is determined that a state change has been detected, and the processing of this flow ends.

As described above, in this embodiment, the combination of "1" and "0" of the two signal lines D1 and D2 is (0,0).
The four states of (0,1) (1,0) (1,1) are expressed, and the states of the signal lines D1 and D2 are changed to the three states excluding the current state among the above four states. Be sure to change this 3
By associating “0”, “1”, and “2” with the types of states, one change represents one digit of a ternary number, and the transmission circuit 12 transmits a set of binary data to be transferred. Is converted to a ternary number, and the state of the signal line is changed according to the value of each digit of the ternary number (0 to 2).
Waits for a change in the state of the signal lines D1 and D2, and when a change is detected, receives one digit of ternary digit information (0 to 2) from the relationship between the state before and after the change, and receives a set of When a ternary number having the number of digits corresponding to the data is received, the data is transferred by converting it into a binary number, so that an independent clock signal is not required, and a conventional method using a clock signal and a data signal is used. The data transfer speed is greatly improved even if the frequency at which "1" and "0" are switched between the two signal lines is the same as compared with the above. That is, the data transfer method of the above embodiment converts an 8-digit binary number into a 6-digit ternary number and performs data transfer by changing the signal state six times. In this case, a clock signal and a data signal are used. In the conventional method of performing data transfer by using the conventional method, the time required for eight clocks is required, but the data can be transferred in the time required for six clocks, and the speed can be increased by 25%. Also, every time data is transmitted, the signal line D
1, because the state of D2 changes and the receiving side captures data by detecting the state change, there is no need to adjust the transfer clock between the receiving side and the transmitting side as in the start-stop synchronization type, and the cost is reduced. Reduction can be achieved.

In this embodiment, an 8-digit binary number is converted into a 6-digit ternary number, and data transfer is performed by changing the signal state six times. However, the present invention is not limited to this. 16-digit binary number equivalent to minute data is converted to 11-digit 3
The data may be converted into a base number and the data transfer may be performed in 11 signal state changes. In this way, the conventional method of performing data transfer using a clock signal and a data signal requires 16 clocks, but data can be transferred in 11 clocks.
Speed up. In this embodiment, two signal lines are used as signal lines connecting the transmitting side and the receiving side. However, the number of signal lines is not necessarily two, and even if more signal lines are used. It goes without saying that it is good. In this case, since the number of combinations of ON and OFF can be further increased, a data transfer method similar to that of the present embodiment can be performed using, for example, a quaternary number or a quinary number.

[0021]

According to the present invention, ON of two signal lines,
Of the four states of the OFF combination, data is transferred by constantly changing the signal lines to three states other than the current state, so that two signal lines are used to achieve higher speed. Data transfer can be performed.

[Brief description of the drawings]

FIG. 1 can be represented by two signal lines of a data transfer method.
It is a figure which shows the state of a kind.

FIG. 2 is a diagram showing that transfer data of a data transfer method can be expressed in four types of states.

FIG. 3 is a diagram for explaining a data transfer side of a data transfer method.

FIG. 4 is an overall configuration diagram of a data transfer method.

FIG. 5 is a flowchart of a data transmission operation of the data transfer method.

FIG. 6 is a diagram for explaining a data transmission operation of the data transfer method.

FIG. 7 is a flowchart of a data receiving operation of the data transfer method.

FIG. 8 is a diagram for explaining a data receiving operation of the data transfer method.

FIG. 9 is a flowchart illustrating an operation of detecting a change in a signal line of the data transfer method.

FIG. 10 is a timing chart for explaining a conventional start-stop synchronization type data transfer method.

FIG. 11 is a timing chart for explaining a conventional data transfer method for simultaneously outputting a data signal and a clock signal using two signal lines.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 data transfer device 12 transmission circuit (transmission side) 13 reception circuit (reception side) 21, 31 binary register 22 binary / ternary conversion circuit 23, 29 ternary register 24, 27 current value register 25 data transmission unit 26 transmission Control unit 28 data reception unit 30 ternary / binary conversion circuit 32 reception control unit D1, D2 signal lines

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 29/00 H03M 5/14 H04L 25/02

Claims (1)

(57) [Claims] 1. Two types of signal lines connecting a transmitting side and a receiving side are used, and ON and OFF of the two signal lines are combined so that four types of states can be expressed. A data transfer method in which data is transferred by changing a signal line to three types other than the current state among the four types of states. One change of the state of the signal line represents one digit of a ternary number by making it correspond to the value displayed in the radix, and the transmitting side converts a set of binary data to be transferred into a ternary number. And the states of the two signal lines are changed according to the value of each digit of the ternary number. When the change in the state of the signal lines is detected, the receiving side performs a change before and after the change. One digit ternary information based on signal line status A data transfer method for receiving a report and converting a ternary number having a number of digits corresponding to a set of data to be received into a binary number.