JPH04212442A - Performance-reinforced ic packaging structure body - Google Patents

Abstract

PURPOSE: To provide a cooling method for efficiently diffusing heat generated from an IC chip. CONSTITUTION: In an IC package composed of a performance-reinforced element 66 for a semiconductor die in a package 60, the cover of this package is formed of a Peltier device. As an example of execution, a cold plate 64 of the Peltier device forms this cover and a Peltier effect semiconductor and on the other hand, a hot plate 68 are attached to a cold plate outside this package. As the other example of execution, the hot plate forms a cover, and the Peltier effect semiconductor and the cold plate are placed inside the package. In both examples of execution, the semiconductor die is directly coupled to the cold plate, achieving efficient Peltier heat conduction. Further, a frame member is added between the cover and the remaining section of the package, the latter is thermally insulated and a heat gain between a circuit board and the package cover is decreased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to computer performance enhancement devices and, more particularly, to integrated circuit packages containing integrated performance enhancement elements for cooling computer components.

[0002] The present invention is also disclosed in US Pat.
No. 12,733, the contents of which are incorporated herein by reference and constitute a part thereof.

0003

SUMMARY OF THE INVENTION As integrated circuit designs become more complex, their power requirements increase. Therefore, a cooling method is needed to dissipate the heat generated from chips of such designs. One method of cooling IC chips is to couple one or more chips to a performance enhancement device. For example, one type of performance enhancement device, a Peltier device, is coupled to an IC chip to reduce the operating temperature of the chip. Lowering the operating temperature increases the circuit operating speed of the IC chip.

Peltier device cooling techniques are described in US Pat. No. 4,812,733, cited above. FIG. 1 of the present application depicts a temperature-controlled peripheral device 10 according to this patent and including a Peltier device. The Peltier device includes at least one Peltier effect semiconductor 30 sandwiched between a cold plate 26 and a hot plate 32. The combination of these three layers is called a Peltier device. Peltier effect semiconductors generate heat at one connection point and absorb heat at another connection point in response to an electric current. In this manner, when a current is applied to the Peltier semiconductor device, the adjacent hot plate is heated and the adjacent cold plate is cooled.

The Peltier device is contained within enclosure 12 adjacent performance critical computer elements 20, 22 and 24. In particular, cold plate 26 is adjacent computer components 20, 22, and 24. Each element 20,
22 and 24 are conventional mounted computer elements having ceramic cases or the like. Temperature sensor 28 is connected to cold plate 26 to create a current proportional to the sensed temperature. An environmental control circuit (not shown) receives a signal current from temperature sensor 28 and compares this signal to a signal corresponding to a particular temperature set point. When the sensed temperature is above the set point, current is fed back to the Peltier effect semiconductor 30 to generate a cooling flow to the cooling plate 26. This cools the element.

Traditionally, Peltier devices have been coupled to ceramic packages of computer components to cool them, thereby enhancing performance. Conventional computer device packages themselves (eg, ceramics containing IC semiconductors) are not known to contain performance-enhancing elements. The cooling efficiency of an assembly with a Peltier effect semiconductor depends on the Peltier semiconductor properties, the distance of the Peltier semiconductor from the heat source being cooled, and intervening objects (e.g. ceramic cooling plates, IC package covers, bonding agents, etc.)
It is desirable to minimize the distance between the Peltier effect semiconductor and the heat source to be cooled, while maximizing the thermal conductivity between the two.

A problem with the implementation of Peltier devices for cooling computer devices is that, in order to minimize Peltier power requirements and prevent condensation, a circuit board connected to the computer device is placed within the cooled computer device and the Peltier device. This means that it is necessary to control the heat gain from the If this is not properly controlled, condensation can form on the pins of cooled computer components, corroding the pins and shorting the signal path. Thermal gain is the input of thermal energy (eg, heat) into the device. Accordingly, there is a need for a method and apparatus for cooling computer components that prevents the formation of condensation and minimizes power requirements.

[0008]

SUMMARY OF THE INVENTION In accordance with the present invention, an IC semiconductor die is packaged in a performance-enhancing structure to improve heat transfer properties, increase the Peltier semiconductor effect, and increase thermal gain and Peltier semiconductor effects. Reduces power requirements and prevents condensation.

According to one feature of the invention, the IC package includes a Peltier device as an integral part thereof. A Peltier device forms the cover of an IC chip, and the semiconductor die of the chip is directly coupled to the Peltier device. Such tight coupling between the semiconductor die and the Peltier device reduces the heat path and improves heat transfer between the two. Therefore, the power consumption required by the Peltier device to achieve the desired cooling effect is reduced. According to one embodiment of the invention, the cooling plate of the Peltier device forms a package cover to which the die is mounted inside the package. The Peltier effect semiconductor and, if possible, the hot plate of the Peltier device are coupled to the cold plate outside the package. According to yet another embodiment, the hot plate of the Peltier device forms the IC package cover, while the cold plate and the Peltier effect semiconductor are located within the package. The dice are mounted on a cold plate within the package.

According to another feature of the invention, a heat sink or other heat removal device is formed on an electrically insulating surface adjacent to the Peltier semiconductor to directly absorb the heat generated by the Peltier effect semiconductor. As a result, the conventional ceramic hot plate can be omitted. According to another feature of the invention, a frame member is disposed between the package cover and the circuit board of the package to increase the thermal path between the package cover and the circuit board to which the package is coupled. Such frame members reduce heat gain from the circuit board to the package cover. As a result, the temperature difference between the circuit board and the cover increases, and condensation on the circuit board can be avoided.

(Embodiment) A commercially available integrated circuit (IC) chip that makes the conventional IC package structure more complex.
Packages include pin grid array ("PGA") and leaded chip corner ("LCC") packages. Both PGA and LCC packages are characterized by having thin wires attached to a frame member and consisting of a semiconductor die packed within a ceramic package. Pins or leads for each chip are formed on the frame member and connected to the semiconductor die by thin wires.

Referring to FIG. 2, a PGA package 40 includes a semiconductor die 42, a circuit wiring board 46, a frame member 48, a bottom cap 50, a cover 52 and pins 54.
including. The bottom cap 50 is made of conventional "ceramic" material (
It is generally made of Al 2 O 3 ), while the cover 52 is made of a conventional material such as "Kovar." The size of a PGA package is approximately 1.75 x 1.75 inches for a typical 168-pin package.
This dimension can be changed. As shown, pins 54 are located in concentric squares near the chip periphery. Each pin 54
is approximately 18-20 MIL in diameter and 3/16 inch long.

Although the size of the LCC package is variable, a typical 144-lead package is approximately 1.2
It is 5 x 1.25 inches. Leads extend outward L
It emerges from the side of the CC package, curves downward, and finally curves outward. The final bend outwards allows soldering,
or otherwise create a flat surface for mounting the chip to a circuit board. The thickness of each lead is approximately 5.5MIL, width 10M
Provide approximately 10 MIL spacing between each lead at IL.

PGA and LCC package structures represent many of today's VLSIIC devices. Such structures are modified in accordance with the present invention to create performance-enhancing packaging structures.

IC Package According to First Embodiment FIG. 3 shows an IC package according to a first preferred embodiment of the present invention.
A GA-type packaging structure 60 is shown. A package 60 surrounds a semiconductor die 70 and includes a Peltier device 62.
, a frame member 72, a circuit wiring board 78, a frame member 80, a bottom cap 82 and a pin 74.

Dice 70 embodies a particular integrated circuit design and includes contacts for electrically coupling to external circuitry. Pins 74, circuit board 78 and thin wires 81 form such electrical connections between the die contacts and external circuitry. 1
To make a 68-pin package, the die must be 16
It will have 8 contact points. Thus, 168 thin wires are included, each connecting a respective contact to a respective pin 74.

Comparing the enhanced performance package 60 to the conventional package 40, the cover 52 of the package 40 is replaced by a Peltier device 62 and a frame member 72. The Peltier device 62 includes a cooling plate 64 , at least one Peltier effect semiconductor 66 and a hot plate 68 . Cold plate 64, hot plate 68, and frame member 72 are made of conventional "ceramic" materials used in chip packaging, such as Al 2 O 3 . Prior to assembly of the Peltier device 62, a grid pattern is formed on both the cold plate and the hot plate to which the Peltier effect semiconductors are mounted. The Peltier effect semiconductors are then soldered to appropriate locations on the cold plate 64 and the hot plate 68, respectively.

As shown in FIG. 3, the cooling plate 64 is connected to the chamber 76.
A cover of the package 60 surrounding the semiconductor die 70 inside is formed. The chamber 76 includes the cooling plate 64 and the frame members 72 and 8.
0, formed of a circuit wiring board 78 and a bottom cap 82. A Peltier effect semiconductor 66 is mounted on the surface of the cooling plate 64 facing the chamber 76, and a hot plate 68 is mounted on the side of the Peltier effect semiconductor 66 facing the cooling plate 64.

Peltier device 62 cools semiconductor die 70 . Without the Peltier device, the heat generated by die 70 would dissipate into the peripheral area of package 60. Excessive heating can damage the package and the circuit board to which it is attached. Thus, the Peltier device serves to eliminate damage to the electrical environment of the package 60. Furthermore, the Peltier device 62 can increase the operating speed of the die by inducing a reduced operating temperature in the die 70. This reduced operating temperature will be significantly lower than the temperature of the surrounding area of the package. The temperature in the area around the package can reach as high as 85°C. Lowering operating temperature is 0~
Any temperature within the temperature range of 85°C or less may be used. The lower limit of this temperature range depends on the Peltier semiconductor properties and can be below zero if desired. The Peltier device therefore serves to cool the die 70 and/or improve its performance.

As shown in FIG. 3, die 70 is mounted directly to cold plate 64 without any intermediate layer (other than adhesive). Special layers such as cover 52 in FIG. 2 are therefore eliminated, resulting in a shorter thermal path. In this way, the conduction of thermal energy from the dice 70 is more effective. This improvement effect can be achieved by using Peltier effect semiconductors.
to the desired temperature and reduce its power consumption. Therefore, Peltier efficiency improves.

To maximize heat transfer between die 70 and cold plate 64, die 70 is mounted on cold plate 64 with a thermally conductive solder or resin material. These materials are dice 7
A high degree of molecular contact occurs between the zero surface and the cold plate, allowing effective heat transfer. As previously mentioned, package 60 also includes an additional frame member 72 that was missing from conventional package 40. Additional frame member 72 serves to reduce heat gain between cold plate 64 and the circuit board to which package 60 is attached. The reduction in heat gain is accomplished by increasing the gap between the cold plate 64 and the circuit board and reducing the surface area of frame members in contact with the cold plate 64. The increased gap between the cooling plate 64 and the circuit board to which the package 60 is joined provides a longer thermal distance;
and create greater thermal insulation. The reduced frame member surface area reduces the thermal conductivity of the heat transfer path between the cold plate and the circuit board. These factors collectively reduce heat gain. Thus, by reducing the thermal gain, the chance of condensation accumulating near the package 60 is reduced. However, in order to further reduce the heat gain, the exposed area of the cooling plate 64 may be provided with a humidity-sealed case (not shown) using a heat-insulating, moisture-proof material.

The additional frame member 72 also includes the die 70.
It serves to reduce the heat gain between the heat exchanger and the external environment. Heat gain from the surrounding environment to an object is the flow of thermal energy from an environment at a first temperature to an object at a second temperature less than or equal to the first temperature (ie, heat flow to the object). Increasing the distance between the package cover and the wiring board 46 increases the air volume surrounding the die. The increased air volume creates greater thermal insulation around the die and reduces heat gain. This air volume forms chamber 76. Chamber 76 can be evacuated or replaced with dry inert gas to improve the thermal insulation properties of its volume. Once evacuated, the pressure in chamber 76 can be reduced to less than 100 Torr. In the case of replacement, the chamber 76 is maintained at atmospheric pressure even when filled with inert gas. When chamber 76 is evacuated or appropriately evacuated, the degree of heat transfer by conduction or convection is limited by the reduction in molecular momentum, thereby reducing the number of collisions of molecules within chamber 76.

The beneficial cooling properties of Peltier device 62 have been described above. However, the Peltier device 62 cools on one surface and dissipates heat on the other surface. To absorb this dissipated thermal energy, a heat sink or other heat removal device is bonded to the hot plate 68 with thermally conductive grease or cement (ie, epoxy).

Details of the operation of Peltier device 62 are described in the above-cited US Pat. No. 4,812,733, which is incorporated herein by reference in its entirety. Accordingly, a temperature sensor (not shown) is coupled directly to the cold plate and a signal lead is connected directly to the Peltier effect semiconductor 66.

FIG. 4 shows a modified Peltier device 62' for use in the embodiment of FIGS. 3-5. This Peltier device 62' includes a cooling plate 64 forming the cover of the package 60 of the device shown in FIG. The Peltier device 62' also includes a plurality of vertically disposed Peltier effect semiconductors 90. However, the Peltier device 62'
When compared with the former, the hot plate 68 in FIG. 3 is missing. Instead, the heat absorber 92 is the Peltier effect semiconductor 9
0 directly or otherwise coupled.

The heat absorber 92 according to this embodiment is formed of a plurality of fins 94 and a bonding substrate 96. Aluminum surface 97 is formed on the bottom surface of substrate 96, preferably of an electrically insulating material such as aluminum oxide or silicon oxide. The grid pattern previously described for hot plate 68 is now formed on insulating surface 97. A Peltier effect semiconductor 90 is soldered to this surface 97 in a grid pattern.

By omitting the heat plate 68 and attaching the heat absorber 92 directly to the Peltier effect semiconductor 90, the heat absorber 9
Thermal conductivity to 2 is improved.

IC Package According to Second Embodiment FIG. 5 shows a performance-enhanced ICPGA according to a second embodiment of the present invention.
- type package structure 100 is shown. The performance enhancement package 100 includes a Peltier device 102 provided on the cover of the package 100 as in the first embodiment. However,
According to this embodiment, the cover of the package 100 is
It is the hot plate 108 of the Peltier device 102 rather than the cold plate 64 in embodiment 60.

By providing a cover with hot plate 108, no cooling surfaces are exposed to the outer areas of the package. Therefore,
The heat gain between the circuit board and the cover and between the die and the outer regions of the package 100 is low. As a result, there are fewer sources of condensation. Thus, exposed cover surfaces do not need to be surrounded by moisture-resistant material.

As shown, the package 100 includes a Peltier device 102, a semiconductor die 110, and a frame member 112.
, a circuit wiring board 114, a frame member 116, a bottom cap 118, and a pin 120. semiconductor dice 11
0 is thermally bonded to the cooling plate 104 using thermally conductive epoxy as described above. The thin wire 122 is attached to the die 1 on the circuit wiring board 114.
10 are electrically coupled. Dice 110, cooling plate 104
The Peltier effect semiconductor 106 is housed within a chamber 124 formed by the hot plate 108, the frame structure 112, the circuit wiring board 114, the frame member 116, and the bottom cap 118. Chamber 124 is evacuated or replaced with dry inert gas as previously described for the first embodiment.

[0031] Generally, the heat sink is located adjacent to the heat plate 108. By using the heat plate 108 as a package cover, the surface contact area with the heat absorber is increased and thermal conductivity to the heat absorber is improved. The heat sink can be attached to the hot plate using an intervening layer of thermally conductive grease or cement, which further increases the thermal conductivity to the heat sink.

The operation of the Peltier device 102 is as quoted above.
No. 4,812,733, which is incorporated herein by reference in its entirety. Accordingly, a temperature sensor (not shown) is coupled directly to the cold plate and a signal lead is coupled directly to the Peltier effect semiconductor 66. The Peltier effect semiconductor 106 is a package 100
Since the lead that leads to this is located inside pin 12
Connected to 0. Similarly, leads are connected to appropriate pins 120 to couple the temperature sensor to the cold plate 104. Alternatively, the leads of the sensor may be connected to the frame member 11.
Penetrate to 2.

According to another embodiment, package 100
The hot plate 108 forming the cover can be omitted as described above with respect to FIG. As a result, the cover of the package 100 is formed by directly bonding or attaching the heat absorber 92 to the Peltier effect semiconductor 106.

Moisture-resistant Pin Connector FIG. 6 shows a pin connector 130 into which an IC chip (eg, package) is inserted. Pin connector 13
0 includes a housing 132 through which a long pin 134 extends. Housing 132 defines a chamber 136 filled with foam potting material. Elongated pin 134 includes a female end that receives a pin of a performance enhancement package 60, 100 or other package structure. At the end opposite the female end, insert the long pin 1
34 may be coupled to a circuit board (not shown) to which the package is connected.

Housing 132 is made of a low thermal conductivity thermoplastic material. The foam potting is sealed within the housing 132 to prevent moisture and eliminate heat leakage paths. Although the preferred embodiments of the present invention have been described above, various alternatives and modifications may be used. For example, although only one semiconductor die is described in the embodiments disclosed above, multiple dice may be included within the same package. Additionally, the temperature and voltage control circuitry described in referenced US Pat. No. 4,812,733 can be mounted on the cold plate 104 or 64 adjacent to each semiconductor die. Alternatively, such temperature and voltage control circuitry can be mounted within the pin connector 130 to which the package 60 or 100 is connected. Therefore, the foregoing description should not be construed as limiting the scope of the invention, which is defined by the appended claims.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer performance enhancement device according to the prior art.

FIG. 2 is a cross-sectional view of a conventional IC packaging structure.

FIG. 3 is a cross-sectional view of an embodiment of the invention.

FIG. 4 is a block diagram of a heat sink for an embodiment of the Peltier semiconductor interface of the present invention.

FIG. 5 is a cross-sectional view of an IC chip pin connector according to the present invention.

FIG. 6 is a cross-sectional view of another embodiment of IC performance enhancement packaging according to the present invention.

[Explanation of symbols]

40 Prior art packages 60, 100 Performance-enhancing PGA-type package structures 62, 62', 102 Peltier devices 64, 104
Cooling plate 66, 90, 106 Peltier effect semiconductor 68, 10
8 Hot plate 72, 80, 112, 116 Frame member 70, 1
10 Semiconductor dice 74, 120 Pins 78, 114 Circuit wiring board 81, 112 Thin wire 92 Heat absorber 94 Fin 96 Substrate 82, 118 Bottom cap

Claims (20)

[Claims] 1. An integrated circuit chip package comprising a semiconductor die and a Peltier device, characterized in that the Peltier device forms a cover for the package, and the semiconductor die is directly coupled to the Peltier device. package. 2. The package of claim 1, wherein the semiconductor die is hermetically sealed within the package under reduced pressure for thermal insulation. 3. The package of claim 1, wherein the semiconductor die is hermetically sealed with a dry inert gas for thermal insulation. 4. The Peltier device comprises a cooling plate and at least one Peltier effect semiconductor, the cooling plate forming the cover, and the semiconductor die being directly coupled to the cooling plate. A package according to claim 1. 5. Coupled with means for reducing heat generated by at least one Peltier effect semiconductor, said heat reducing means comprising a plurality of fins and an electrically insulating surface, said insulating surface being connected to said at least one Peltier effect semiconductor. 5. The package according to claim 4, wherein the package is arranged adjacent to a Peltier effect semiconductor. 6. The Peltier device comprises a cooling plate, at least one Peltier effect semiconductor, and a hot plate, the hot plate forming the cover, and the semiconductor die attached to the cooling plate. 2. The package of claim 1, wherein the package is directly coupled and wherein the cooling plate and the at least one Peltier effect semiconductor are disposed therein together with the semiconductor die. 7. The package of claim 6, wherein the semiconductor die, the cooling plate and the at least one Peltier effect semiconductor are hermetically sealed under reduced pressure to thermally insulate the die. 8. The semiconductor die, the cooling plate and the at least one Peltier effect semiconductor are sealed together with a dry inert gas to thermally insulate the die. Package described in Section 6. 9. A plurality of pins electrically coupled to the semiconductor die, a pin connector for thermally isolating the package from a circuit board to which the package is electrically coupled; The pin connector includes means for engaging the plurality of pins to electrically couple the pins to the circuit board and a thermal and moisture barrier for substantially thermally isolating the package from the circuit board. A package according to claim 1, characterized in that it comprises means for: 10. The package of claim 9, wherein said pin connector further comprises a housing in which said thermal isolation means is housed. 11. A semiconductor die encased between a substrate, a thermally conductive cover plate, and a means for coupling the semiconductor die to the cover plate; An integrated circuit performance enhancement chip package comprising a Peltier effect semiconductor disposed adjacent to said cover plate to absorb transferred thermal energy. 12. A device that is coupled to a Peltier effect semiconductor and functions as a heat plate, the heat plate comprising a plurality of fins and an electrically insulating surface disposed adjacent to the Peltier effect semiconductor. 12. A package according to claim 11, characterized in that it includes means for absorbing. 13. An IC package comprising a substrate, a cover plate, and a semiconductor die wrapped between the two, a first heat exchanger plate, a Peltier effect semiconductor, and a second heat exchanger plate, wherein the Peltier effect semiconductor is a Peltier device configured to absorb thermal energy from a heat transfer plate and dissipate thermal energy to the second heat transfer plate, the cover plate of the IC package being configured to absorb thermal energy from the heat transfer plate and dissipate thermal energy to the second heat transfer plate; An IC package Peltier device characterized in that the IC package is a hot plate and the semiconductor die is thermally coupled to the cover plate. 14. Consisting of a semiconductor die, a first heat transfer plate, a Peltier effect semiconductor, and a second heat transfer plate, the Peltier effect semiconductor absorbs thermal energy from the first heat transfer plate and the second heat transfer plate absorbs thermal energy from the first heat transfer plate. a Peltier device configured to dissipate thermal energy to a hot plate, the second heat transfer plate forming a cover plate for a package enclosing the semiconductor dice therein; IC chip package with cooling capacity. 15. Claim 14, further comprising a plurality of leads for electrically connecting the package to a circuit board and means for thermally insulating the second heat exchanger plate from the leads. Package listed. 16. A plurality of fins and an electrically insulating surface disposed adjacent to at least one Peltier effect semiconductor forming the second heat exchanger plate, including means for reducing heat generated by the Peltier effect semiconductor. The package according to claim 14, characterized in that: [Claim 17] It has one cover and a thin wire lead,
and a semiconductor die attached to the cover, a wiring board to which the thin wire leads are electrically connected, and a device that physically connects the cover and the wiring board and has a smaller surface area than the wiring board, a frame member for minimizing the heat gain of the cover with respect to the circuit board to which the package is connected; and a Peltier semiconductor and the cover, and a means for realizing a Peltier effect for cooling the semiconductor die; IC chip package with thermal cooling ability. 18. A performance-enhancing IC package having a plurality of pins for thermal isolation from a circuit board to which it is electrically connected, the plurality of pins being electrically connected to the circuit board. a pin connector comprising: means for engaging said pin; and means comprising an insulating and vapor barrier material to provide sufficient thermal isolation of said package from said wiring board. 19. A connector according to claim 18, characterized in that it comprises a housing in which said thermally insulating means is housed and through which said engagement means extends. 20. Claim 1, wherein said engagement means comprises a pin extension lead extending through said housing.
Connector described in item 9.