JPH02139952A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02139952A
JPH02139952A JP63292328A JP29232888A JPH02139952A JP H02139952 A JPH02139952 A JP H02139952A JP 63292328 A JP63292328 A JP 63292328A JP 29232888 A JP29232888 A JP 29232888A JP H02139952 A JPH02139952 A JP H02139952A
Authority
JP
Japan
Prior art keywords
package
heat
conductive member
semiconductor
cooling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63292328A
Other languages
Japanese (ja)
Other versions
JP2656328B2 (en
Inventor
Tomoaki Takubo
知章 田窪
Kazuyoshi Saito
和敬 斎藤
Hiroshi Tazawa
田沢 浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63292328A priority Critical patent/JP2656328B2/en
Publication of JPH02139952A publication Critical patent/JPH02139952A/en
Application granted granted Critical
Publication of JP2656328B2 publication Critical patent/JP2656328B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To perform cooling efficiently by providing the following elements and heat insulating layers: a semiconductor element which is installed to the face inside of a package of a heat conductive member for plugging the openings of the package; a cooling element which is installed on the opposite side of the package; heat insulating layers which are provided at least on one side of surfaces of the package as well as the heat conductive member. CONSTITUTION:A heat conductive member 102 is prepared so that openings of the rear of a package 101 on which a glass cover 101b is provided on the upper face of a mainframe 101a are filled up and a semiconductor 103 is installed at the inside of the package 101. Cooling elements 104 are installed at the face of the opposite side of the package. Heat insulating layers 113 are provided not only by covering a part where the glass cover 101b is removed, that is, the surface of the heat conductive member 102 but also by covering the surface of the cooling elements 104 as well. Once an electric current flows from the side of a metallic plate 106 of the cooling element 104 to a P-type semiconductor 105 and a metallic plate 107, the metallic plate 106 acts as a heat absorption part and the metallic plate 107 acts as a heat radiation part due to the Peltier effect.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置に係り、特に冷却素子を取り付け
た半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a semiconductor device equipped with a cooling element.

(従来の技術) 半導体装置は、一般に温度変化に対しその素子の特性も
変化する。即ち、温度上昇により熱雑音が増加し、その
素子の持つ性能が著しく劣化する。それを防ぐ為には、
素子の温度上昇を妨げる様素子を冷却することが必要と
なる。従来、この種の半導体装置としては、例えば特開
昭63−6864号公報記載のものが知られている。こ
の半導体装置を第7図に示す。誘電体基板201の上下
面にメタライズ部202,203が形成され、下側のメ
タライズ部203には更に放熱板204が装着されてい
る。上側のメタライズ部202には、高周波トランジス
タ205が搭載されている。
(Prior Art) In a semiconductor device, the characteristics of its elements generally change as the temperature changes. That is, thermal noise increases as the temperature rises, and the performance of the element significantly deteriorates. In order to prevent that,
It is necessary to cool the element in a manner that prevents the temperature of the element from rising. Conventionally, this type of semiconductor device is known, for example, as described in Japanese Unexamined Patent Publication No. 63-6864. This semiconductor device is shown in FIG. Metallized portions 202 and 203 are formed on the upper and lower surfaces of the dielectric substrate 201, and a heat sink 204 is further attached to the lower metalized portion 203. A high frequency transistor 205 is mounted on the upper metallized portion 202.

また、誘導体基板201内には冷却素子が埋めこまれて
いる。即ち、これはP型半導体206の両面に金属板2
07,208を形成したもので、これによりベルチェ効
果を用いた冷却素子を構成しており、上側の金属板20
7は誘電体基板201の上表面に形成されたメタライズ
部202と導電体209にて連結され、下側の金属板2
08は放熱板204に接続されている。誘電体基板20
1上面のメタライズ部202には外部リード210が接
続されている。
Further, a cooling element is embedded within the dielectric substrate 201. That is, this means that the metal plates 2 are placed on both sides of the P-type semiconductor 206.
07, 208, which constitutes a cooling element using the Beltier effect, and the upper metal plate 20
7 is connected to the metallized portion 202 formed on the upper surface of the dielectric substrate 201 by a conductor 209, and is connected to the metal plate 2 on the lower side.
08 is connected to the heat sink 204. Dielectric substrate 20
An external lead 210 is connected to the metallized portion 202 on the top surface of the metallized portion 202 .

今、熱の移動に関してみると、メタライズ部202と放
熱板204間に電圧を印加するとベルチェ効果により、
金属板207とP型半導体206との接合部では吸熱さ
れ、金属板208とP型半導体206との接合部では、
放熱される。
Now, regarding heat transfer, when a voltage is applied between the metallized portion 202 and the heat sink 204, due to the Beltier effect,
Heat is absorbed at the joint between the metal plate 207 and the P-type semiconductor 206, and at the joint between the metal plate 208 and the P-type semiconductor 206,
Heat is dissipated.

そのため、高周波トランジスタ205により発生した熱
は、導電体209を通してベルチェ効果を用いた冷却素
子に伝わり、放熱板204を通して放熱し得るのである
。しかしながら、ここで示した従来例においては周囲温
度が高周波トランジスタ205の温度よりも゛高くなっ
た場合、ベルチェ効果により吸収される熱としては、高
周波トラン、ジスタ205から発生したもののみならず
周囲の雰囲気中から冷却素子へ伝わるものがあるため、
高周波トランジスタ205から発生した以外の熱が大き
いと、ベルチェ効果により周囲の雰囲気を冷却する成分
が大きくなり、効率的に高周波トランジスタ205を冷
却することが難しくなる。
Therefore, the heat generated by the high-frequency transistor 205 is transmitted to the cooling element using the Beltier effect through the conductor 209, and can be radiated through the heat sink 204. However, in the conventional example shown here, when the ambient temperature becomes higher than the temperature of the high-frequency transistor 205, the heat absorbed by the Beltier effect includes not only the heat generated from the high-frequency transformer and the transistor 205 but also the surrounding heat. Because some things are transmitted from the atmosphere to the cooling element,
If the amount of heat other than that generated by the high-frequency transistor 205 is large, the component that cools the surrounding atmosphere due to the Beltier effect becomes large, making it difficult to efficiently cool the high-frequency transistor 205.

(発明が解決しようとする課題) 以上の様に半導体素子の特性を安定して引き出す為に、
ベルチェ効果を用いた冷却素子を用い半導体素子の冷却
を行なう場合、周囲の温度が半導体素子の温度よりも高
いと半導体素子から発生する以外の周囲の熱を冷却素子
が吸収し効率的な冷却を妨げる。この為、半導体素子は
、温度上昇により充分な性能を発揮し得ない。これを改
善するには冷却素子の能力を高めれば良いが、冷却の為
の消費電力が著しく大きくなってしまう。
(Problem to be solved by the invention) As described above, in order to stably bring out the characteristics of semiconductor elements,
When cooling a semiconductor element using a cooling element that uses the Beltier effect, if the ambient temperature is higher than the temperature of the semiconductor element, the cooling element absorbs the surrounding heat other than that generated by the semiconductor element, resulting in efficient cooling. hinder. For this reason, the semiconductor element cannot exhibit sufficient performance due to the temperature rise. Although this can be improved by increasing the capacity of the cooling element, the power consumption for cooling increases significantly.

本発明は、この様な課題を解決する半導体装置を提供す
ることを目的とする。
An object of the present invention is to provide a semiconductor device that solves these problems.

[発明の構成] (課題を解決するための手段) 本発明は上記事情に鑑みて為されたもので、表面に開口
が設けられたパッケージと、この開口を塞ぐ如く設けら
れた熱伝導性部材と、この熱伝導性部材のパッケージ内
部側の面にとりつけられた半導体素子と、熱伝導性部材
の半導体素子とは反対側の面にとりつけられた冷却素子
と、パッケージ、熱伝導性部材の少な、くとも一方の表
面に設けられた断熱層とを備えた事を特徴とする半導体
装置を提供するものである。
[Structure of the Invention] (Means for Solving the Problems) The present invention has been made in view of the above circumstances, and includes a package having an opening on its surface, and a thermally conductive member provided to close the opening. , a semiconductor element attached to the surface of the thermally conductive member on the inside of the package, a cooling element attached to the surface of the thermally conductive member opposite to the semiconductor element, a package, and a small portion of the thermally conductive member. The present invention provides a semiconductor device characterized by comprising a heat insulating layer provided on at least one surface.

(作用) この様にパッケージ、熱伝導性部材の少なくとも一方の
表面に断熱層を設けることにより、パッケージの周囲で
発生した熱がパッケージ次いで熱伝導性部材を介して冷
却素子へ伝わる熱波路、パッケージの周囲で発生した熱
が直接熱伝導性部材を介して冷却素子へ伝わる熱流路の
一方又は双方を伝導する熱を低減することができ、効率
的に半導体素子を冷却することが可能となり、冷却の為
の消費電力を節約しながら、半導体素子の性能劣化を抑
えることができる。
(Function) By providing a heat insulating layer on at least one surface of the package and the thermally conductive member in this manner, a thermal wave path is formed in which the heat generated around the package is transmitted to the cooling element through the package and the thermally conductive member. It is possible to reduce the heat that is transmitted through one or both of the heat flow paths in which the heat generated around the semiconductor element is directly transmitted to the cooling element via the thermally conductive member, making it possible to efficiently cool the semiconductor element. It is possible to suppress performance deterioration of semiconductor elements while saving power consumption.

(実施例) 以下、本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第、1図は、本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

例えば、ムライトセラミック(3A12032 S i
O2)製の枠体101aの上面にガラスカバー101b
が設けられたパッケージ101の裏側の開口を塞ぐ様に
例えばCu−W(銅・タングステン合金)からなる板状
の熱伝導性部材102が設けられている。その熱伝導性
部材102のパッケージ101内部側の面に半導体素子
103が取り付けられている。半導体素子103として
、ここでは固体撮像素子を用いた。
For example, mullite ceramic (3A12032 S i
A glass cover 101b is placed on the top surface of the frame 101a made of O2).
A plate-shaped thermally conductive member 102 made of, for example, Cu-W (copper-tungsten alloy) is provided so as to close the opening on the back side of the package 101 in which the package 101 is provided. A semiconductor element 103 is attached to the surface of the thermally conductive member 102 on the inside of the package 101 . As the semiconductor element 103, a solid-state image sensor was used here.

また、熱伝導性部材102の半導体素子103とは反対
側の面にベルチェ効果を有する冷却素子104が取り付
けられている。この冷却素子104はP型半導体105
の上下両面に金属板106.107を被着することによ
り構成されており、上側の金属板106は熱伝導性部材
102に取り付けられ、下側の金属板107は放熱板1
08に取り付けられている。
Further, a cooling element 104 having a Beltier effect is attached to the surface of the thermally conductive member 102 opposite to the semiconductor element 103. This cooling element 104 is a P-type semiconductor 105
The upper metal plate 106 is attached to the heat conductive member 102, and the lower metal plate 107 is attached to the heat sink 1.
It is attached to 08.

また、半導体素子103の電極109と枠体101aに
設けられた接続配線110は、金属ワイヤー111で接
続されている。接続配線110は、夫々、枠体101a
の側壁に沿って互いに間隔を置いて配置された外部リー
ド端子112に接続されている。
Further, the electrode 109 of the semiconductor element 103 and the connection wiring 110 provided on the frame 101a are connected by a metal wire 111. The connection wiring 110 is connected to the frame 101a, respectively.
The external lead terminals 112 are spaced apart from each other along the side wall of the terminal.

パッケージ101のガラスカバー101bを除いた部分
、熱伝導性部材102の表面を覆って例えばポリスチレ
ンから成る断熱層113が設けられている。本実施例で
は、この断熱層113は冷却素子104表面も覆って設
けられている。ここで、冷却素子104の金属板106
側からP型半導体105、金属板107へと電流を流す
と、ベルチェ効果により、金属板106が吸熱部、金属
板107が放熱部となる。よりて、熱伝導性部材102
からの熱はこれと接している金属板106において吸収
され、金属板107側より放熱板・108を通じて放熱
される。ところで、冷却素子104への熱流路としては
 ■半導体素子103で発生した熱が、熱伝導性部材1
02を介して伝わる熱流路 ■半導体103の周囲に配
置された電子部品などから発生した熱がパッケージ10
1、次いで熱電導性部材102を介して伝わる熱流路■
パッケージ101の周囲で発生した熱が直接熱伝導性部
材102に入って伝わる熱流路がある。
A heat insulating layer 113 made of polystyrene, for example, is provided to cover the surface of the thermally conductive member 102, excluding the glass cover 101b of the package 101. In this embodiment, this heat insulating layer 113 is provided to also cover the surface of the cooling element 104. Here, the metal plate 106 of the cooling element 104
When a current is passed from the side to the P-type semiconductor 105 and the metal plate 107, due to the Beltier effect, the metal plate 106 becomes a heat absorption part and the metal plate 107 becomes a heat radiation part. Therefore, the thermally conductive member 102
The heat from the metal plate 106 is absorbed by the metal plate 106 that is in contact with the metal plate 106, and is radiated from the metal plate 107 side through the heat dissipation plate 108. By the way, as a heat flow path to the cooling element 104, heat generated in the semiconductor element 103 passes through the thermally conductive member 1.
■Heat generated from electronic components placed around the semiconductor 103 is transmitted through the package 10.
1. Next, the heat flow path transmitted via the thermoconductive member 102 ■
There is a heat flow path through which heat generated around the package 101 directly enters and is transmitted to the thermally conductive member 102 .

今、第2図に比較例を示す様に断熱層113を設けない
ときは■〜■の熱流路を伝導する熱が存在するが1本実
施例においては、上記の如く断熱層113を設けること
により問題となる。■、■に対応する熱流路を伝導する
熱を低減することが可能となり、効率的に半導体素子1
03を冷却でき、冷却の為の消費電力が節約されるとと
もに1、半導体素子の温度上昇による性能劣化を抑える
ことができる。
Now, as shown in a comparative example in FIG. 2, when the heat insulating layer 113 is not provided, there is heat conducted through the heat flow paths ① to ②, but in this embodiment, the heat insulating layer 113 is provided as described above. This becomes a problem. It becomes possible to reduce the heat conducted through the heat flow paths corresponding to
03 can be cooled, power consumption for cooling can be saved, and performance deterioration due to temperature rise of the semiconductor element can be suppressed.

なお、必ずしも断熱層113を実施例1の如くパッケー
ジ101のガラスカバー101bを除いた部分、熱伝導
性部材102、冷却素子104の表面に設ける必要はな
く、熱源に近い場所に断熱。
Note that it is not necessarily necessary to provide the heat insulating layer 113 on the part of the package 101 except for the glass cover 101b, on the surface of the thermally conductive member 102, and on the surface of the cooling element 104 as in the first embodiment, but insulating the layer 113 in a place close to the heat source.

層を設ける様にしてもよい。図3〜5は、その実施例で
あり、この場合も熱の伝導を低減する効果が充分得られ
る。
A layer may be provided. 3 to 5 show examples thereof, and in this case as well, the effect of reducing heat conduction can be sufficiently obtained.

第3図は、本発明の第2の実施例であり、断熱層113
をパッケージ101の裏面、熱伝導性部材102、冷却
素子104の表面に設けた場合である。この場合は■の
一部及び■に対応する熱流路による熱の伝導を低減する
ことが可能となる。
FIG. 3 shows a second embodiment of the present invention, in which a heat insulating layer 113
This is a case in which these are provided on the back surface of the package 101, the thermally conductive member 102, and the surface of the cooling element 104. In this case, it is possible to reduce heat conduction through part of (2) and the heat flow path corresponding to (2).

第4図は、本発明の第3の実施例であり、断熱層113
をパッケージ101の裏面、熱伝導性部材102の表面
に設けた場合である。この場合も■の一部及び■に対応
する熱の流路による熱の伝導を低減することが可能とな
る。
FIG. 4 shows a third embodiment of the present invention, in which a heat insulating layer 113
is provided on the back surface of the package 101 and on the surface of the thermally conductive member 102. In this case as well, it is possible to reduce heat conduction through a part of (2) and the heat flow path corresponding to (2).

第5図は、本発明の第4の実施例であり、断熱層113
をパッケージ101のガラスカバー101bを除いた部
分の表面に設けた場合である。
FIG. 5 shows a fourth embodiment of the present invention, in which a heat insulating layer 113
This is a case in which this is provided on the surface of the package 101 except for the glass cover 101b.

この場合は主に■に対応する熱流路による熱の伝導を低
減することが可能となる。
In this case, it is possible to mainly reduce heat conduction through the heat flow path corresponding to (2).

また、他の実施例として断熱層113を熱伝導性部材1
02の表面にのみ設ける場合も考えられる。この場合は
、■に対応する熱流路による熱の伝導を低減することが
可能となる。
In another embodiment, the heat insulating layer 113 may be
It is also possible to provide it only on the surface of 02. In this case, it becomes possible to reduce heat conduction through the heat flow path corresponding to (2).

また、熱伝導性部材102と冷却素子104の位置関係
としては、第1図、第3図〜第5図に示した様に熱伝導
性部材102の一部に冷却素子104が取り付けられた
場合の他に、第6図に示す様に熱伝導性部材102の全
面に冷却素子が取り付けられたものでもよい。
Furthermore, the positional relationship between the thermally conductive member 102 and the cooling element 104 is such that the cooling element 104 is attached to a part of the thermally conductive member 102 as shown in FIGS. 1 and 3 to 5. Alternatively, as shown in FIG. 6, a cooling element may be attached to the entire surface of the thermally conductive member 102.

なお、枠体101a材質としてはムライトセラミック(
3A1 0  ・2 S t O2)の他、アルミナセ
ラミック(A1203)等のセラミックを用いてもよい
し、他の絶縁体も使用可能である。
The material of the frame 101a is mullite ceramic (
3A1 0 .2 S t O2), a ceramic such as alumina ceramic (A1203) may be used, and other insulators may also be used.

また、熱伝導性部材102の材質としては、セラミック
と熱膨脹率がほぼ等しいCu−W(銅・タングステン合
金)金属板を用いたが他の材料でもよく、またその形も
必ずしも板状に限定されるものではない。また、断熱層
113の材質としては、枠体101aや熱伝導性部材1
02より熱伝導率の小さいものが好ましく、ポリスチレ
ンの他、例えばポリエチレン、ポリプロピレン等の高分
子樹脂でもよい。その他、本発明の趣旨を逸脱しない範
囲で程々変形して実施することができる。
Further, as the material of the thermally conductive member 102, a Cu-W (copper-tungsten alloy) metal plate, which has a coefficient of thermal expansion almost equal to that of ceramic, was used, but other materials may be used, and the shape is not necessarily limited to a plate shape. It's not something you can do. Furthermore, the material of the heat insulating layer 113 includes the frame body 101a and the thermally conductive member 1.
A material having a thermal conductivity lower than that of 02 is preferable, and in addition to polystyrene, a polymer resin such as polyethylene or polypropylene may be used. Other modifications may be made without departing from the spirit of the invention.

[発明の効果] 以上述べて来た様に本発明によれば、冷却素子の冷却能
力を半導体素子を冷却することに効率良く使うことがで
き、その結果冷却の為の消費電力が節約されるとともに
、半導体素子の温度上昇による性能劣化を抑えることが
できる。
[Effects of the Invention] As described above, according to the present invention, the cooling capacity of the cooling element can be efficiently used to cool the semiconductor element, and as a result, the power consumption for cooling is saved. At the same time, performance deterioration due to temperature rise of the semiconductor element can be suppressed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の実施例を示す半導体装置の断面図、
第2図は、比較例の半導体装置の断面図、第3図、第4
図、第5図、第6図は本発明の他の実施例を示す半導体
装置の断面図、第7図は従来例を示す半導体装置の断面
図である。 図において、 101・・・・・・・・・・・・・・・パッケージ10
1a・・・・・・・・・・・・枠  体101b・・・
・・・・・・・・−ガラスカバー102・・・・・・・
・・・・・・・・熱伝導性部材103・・・・・・・・
・・・・・・・半導体素子104・・・・・・・・・・
・・・・・冷却素子105・・・・・・・・・・・・・
・・P型半導体106.107・・・金属板 108・・・・・・・・・・・・・・・放熱板109・
・・・・・・・・・・・・・・電  極110・・・・
・・・・・・・・・・・接続配線1・・・・・・・・・
・・・・・・金属ワイヤー2・・・・・・・・・・・・
・・・外部リード端子3・・・・・・・・・・・・・・
・断熱層1・・・・・・・・・・・・・・・誘電体基板
2.203・・・メタライズ部 4・・・・・・・・・・・・・・・放熱板5・・・・・
・・・・・・・・・・高周波トランジスタ6・・・・・
・・・・・・・・・・P型半導体7.208・・・金属
FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention;
Figure 2 is a cross-sectional view of a semiconductor device of a comparative example, Figures 3 and 4.
5 and 6 are cross-sectional views of a semiconductor device showing other embodiments of the present invention, and FIG. 7 is a cross-sectional view of a semiconductor device showing a conventional example. In the figure, 101・・・・・・・・・・・・Package 10
1a...... Frame Body 101b...
......-Glass cover 102...
......Thermal conductive member 103...
...... Semiconductor element 104 ......
...Cooling element 105......
...P-type semiconductor 106.107...Metal plate 108... Heat sink 109...
......... Electrode 110...
・・・・・・・・・・・・Connection wiring 1・・・・・・・・・
・・・・・・Metal wire 2・・・・・・・・・・・・
・・・External lead terminal 3・・・・・・・・・・・・・・・
・Insulating layer 1・・・・・・・・・・・・Dielectric substrate 2.203・・・Metallized part 4・・・・・・・・・・・・・・・Radiation plate 5・・・・・・・
......High frequency transistor 6...
・・・・・・・・・P-type semiconductor 7.208・・・Metal plate

Claims (1)

【特許請求の範囲】[Claims] 表面に開口が設けられたパッケージと、この開口を塞ぐ
如く設けられた熱伝導性部材と、この熱伝導性部材のパ
ッケージ内部側の面に取り付けられた半導体素子と、前
記熱伝導性部材の前記半導体素子とは反対側の面に取り
付けられた冷却素子と、前記パッケージ、前記熱伝導性
部材の少なくとも一方の表面に設けられた断熱層とを備
えた事を特徴とする半導体装置。
a package having an opening on its surface; a thermally conductive member provided to close the opening; a semiconductor element attached to a surface of the thermally conductive member on the inside of the package; A semiconductor device comprising: a cooling element attached to a surface opposite to a semiconductor element; and a heat insulating layer provided on at least one surface of the package and the thermally conductive member.
JP63292328A 1988-11-21 1988-11-21 Semiconductor device Expired - Fee Related JP2656328B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63292328A JP2656328B2 (en) 1988-11-21 1988-11-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63292328A JP2656328B2 (en) 1988-11-21 1988-11-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02139952A true JPH02139952A (en) 1990-05-29
JP2656328B2 JP2656328B2 (en) 1997-09-24

Family

ID=17780364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63292328A Expired - Fee Related JP2656328B2 (en) 1988-11-21 1988-11-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2656328B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04212442A (en) * 1990-09-07 1992-08-04 Japan Computer Aid:Kk Performance-reinforced ic packaging structure body
US6476483B1 (en) * 1999-10-20 2002-11-05 International Business Machines Corporation Method and apparatus for cooling a silicon on insulator device
JP2002329897A (en) * 2001-05-01 2002-11-15 Eco Twenty One:Kk Thermoelectric conversion element and optical communication module using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04212442A (en) * 1990-09-07 1992-08-04 Japan Computer Aid:Kk Performance-reinforced ic packaging structure body
US6476483B1 (en) * 1999-10-20 2002-11-05 International Business Machines Corporation Method and apparatus for cooling a silicon on insulator device
JP2002329897A (en) * 2001-05-01 2002-11-15 Eco Twenty One:Kk Thermoelectric conversion element and optical communication module using the same

Also Published As

Publication number Publication date
JP2656328B2 (en) 1997-09-24

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