JPH04211837A - Register saving system - Google Patents

Abstract

PURPOSE:To shorten processing time for register saving by saving the contents of a register on the basis of the information of an information holding means. CONSTITUTION:An operating system executes an instruction for saving the register. A microprocessor stores data in order from the register R0, but at that time, it refers to a modified bit corresponding to each.register. Then, it checks the modified bits corresponding to the registers R0 to R3, and because of '1', it stores their contents in a context storage area, and updates a storage address. Next, when it checks the modified bits of the registers R4 to R28, because of '0', it does not store their contents, but it updates only the storage address. The microprocessor executes the saving of a register set in a way mentioned above.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multitasking operating system, and particularly to a method for saving register contents when switching tasks.

[Conventional technology]

In a single-processor system, a multiple programming method is used to efficiently use a microprocessor (hereinafter abbreviated as CPU). In multiple programming, a program is divided into tasks, which are execution units, and the operating system (hereinafter abbreviated as OS)
selects tasks according to various situations and assigns CPU execution rights. When the OS allocates the CPU execution right to a certain task, it saves the context of the task currently using the CPU into its storage area, and restores the context from the context storage area of the assigned task. The operation at this time will be explained with reference to FIGS. 7 and 8.

FIG. 7 shows an example of a CPU register set. This CPU has 32 registers with a length of 32 bits. It is also assumed that the CPU has instructions for saving and restoring these registers. Figure 8 shows C
This figure shows the processing flow when transferring the PU execution right.

For simplicity, we will assume that there are two tasks: Task A and Task B.

Task A has CPU execution authority, and task A to task B
Assume that the CPU execution right is transferred to Further, it is assumed that the context of the task is the register set shown in FIG. 7, and that the context storage area is secured within the task control block (hereinafter abbreviated as TCB).

In order to switch the execution right of the CPU, the OS uses the TC of task A.
Obtain the B address (■ in Figure 8). The OS is this TCB
A register set save instruction is executed to store the context of task A within. This instruction causes the CPU to
stores all 32 registers in order from register RO to register R31 (■ in FIG. 8). Next, the TCB address of task B is obtained from the head of the execution matrix (■ in FIG. 8). The OS executes a register set return instruction to store the context of task B in this TCB in the register of the CPU. This command causes C
The PU transfers the data stored in the TCB to the register RO.
and stored in R31 (■ in FIG. 8). Throw it away like this
S switches the CPU context from task A to task B.

[Problem to be solved by the invention]

In an information processing system, OS processing time seen from an application program is considered extra processing time (overhead). The time for the task context switching process described above is also an overhead, and is preferably as short as possible.

However, there are 32 32-bit registers, a total of 12
The process of saving 8 bytes of data to memory and storing the same amount of data from memory to a register takes an extremely long time. Therefore, switching of application programs is delayed, causing processing delays. In particular, when such a delay occurs, the response time to an interrupt will decrease in an embedded OS that mainly performs real-time processing. For example, in the case of data transfer, it takes time to process arriving data due to OS overhead, and the next data sent may be overlooked.

Furthermore, in a CPU that incorporates the RISC concept, the number of registers is certain to increase, and the overhead of the OS in a system using such a CPU will further increase.

[Means to solve the problem]

The present invention provides, in a CPU having a plurality of register sets, a means for holding information in one-to-one correspondence with the register set, and a means for holding information that corresponds to the register set in a one-to-one manner; It has means for storing information indicating that it has been changed.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows one embodiment of the invention.

In FIG. 1, one register is provided with a corresponding modify bit.

FIG. 2 shows a register set using this embodiment. FIG. 3 shows the flow when saving the contents of the registers in FIG. 2. Table 1 shows the meanings of the modify bits in FIG.

Next, the operation in a situation similar to the conventional one will be explained using FIGS. 2, 3, and 8. Since the operation indicated by ``■'' in FIG. 8 is the same as that of the conventional example, the operation will be explained from ``■'' in FIG. 8.

As in the past, the OS executes an instruction to save the register set. The CPU sequentially stores data starting from register R0, and at this time refers to the modify bits corresponding to each register. Assume that the modify bits are now as shown in FIG. First, the CPU checks the modify bit corresponding to register R0.

This modification bit is "1". Therefore, C.P.
U stores the contents of register R0 in the context storage area and updates the storage address. Register R1, R2,
The modify bit of R3 is also “1” like register R0.
”. Therefore, the contents of registers R1, R2, and R3 are also stored in the context storage area. Next, register R4
Check the modification bits. The modify bit of register 4 is "0". Therefore, register R
The contents of 4 are not stored, and only the storage address is updated.

The modify bits from register R5 to register R28 are "0". Therefore, during this time, the contents of the register are not stored, and only the storage address is updated. Register R2
Modification bits 9, 30, and 31 are "1".

Therefore, as with register R0, the contents of the register are stored in the context storage area. CPU as above
saves the register set.

Next, the OS obtains the TCB address of task B (the eighth
■) in the figure. The OS executes a register set return instruction in order to store the context of task B stored in the TCB in the register of the CPU. With this command, CP
U sets all the modify bits to "0" and stores the data stored in the context storage area in registers R0 to R31 (■ in FIG. 8).

In this way, the OS replaces the task context.

Another embodiment of the invention will be described in the same manner as the previous embodiment with reference to the figures.

FIG. 4 shows one embodiment of the present invention.

FIG. 5 shows an example of the operation of this embodiment. Figure 6 shows
4 shows a flow for saving the contents of a register when the embodiment shown in FIG. 4 is used.

Next, the operation in a situation similar to the conventional one will be explained using FIGS. 5, 6, and 8. Since the operation indicated by {circle around (2)} in FIG. 8 is the same as in the first embodiment, the operation will be explained starting from {circle around (2)} in FIG.

As in the first embodiment, the OS executes an instruction to save the register set. The modify bit word is now as shown in (■) in FIG. The CPU shifts the modify bit word to the right by one bit (■ in Figure 5).
). Bit 0 of the modify bit word is "1" and a carry occurs. Therefore, the CPU stores the contents of register R0 in the context storage area and updates the storage address. The modify bits of registers R1, R2, and R3 are also "1" like register R0. Therefore, a carry occurs as a result of right shift (■ in Figure 5)
. Therefore, the contents of registers R1, R2, and R3 are also stored in the context storage area.

Again, shift the modify bit word to the right by one bit. Bit 0 at this time is "0".

Therefore, the contents of register R4 are not stored, and only the storage address is updated. All bits corresponding to registers R5 to R28 are "0".

Therefore, during this time, the CPU does not store the contents of the register,
The storage address of the shift of the modify bit word is updated (■ in FIG. 5). Shift the modify word bits to the right again. At this time, bit 0 is "1".

Therefore, the contents of register R29 are stored in the context storage area. The bits corresponding to registers 30 and 31 are “
1'' (■ in Figure 5). Therefore, registers 30,3
The contents of 1 are also stored in the context storage area. As described above, the CPU saves the register set.

Next, the OS obtains the TCB address of task B (the eighth
■) in the figure. The OS executes a register set return instruction in order to store the context of task B stored in this area in the CPU register. This command causes C
The PU stores the data stored in the context storage area in registers R0 to R31 (■ in FIG. 8).

In this way, the OS replaces the task context.

〔Effect of the invention〕

As described above, when saving a register set, the present invention updates only the storage address without saving registers that were not used by the execution of the task.
This has the effect of shortening the register saving processing time. This makes it possible to speed up context switching, which requires the highest processing speed among OS processing. Therefore, the overhead caused by OS processing, which has been a problem in the past, can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the present invention. FIG. 2 shows an example of a register set using the first embodiment. FIG. 3 shows a register set saving flow using the first embodiment. FIG. 4 shows a second embodiment of the present invention. FIG. 5 shows an example of the operation of the second embodiment. FIG. 6 shows a register set saving flow using the second embodiment. FIG. 7 shows a register set of a conventional CPU. FIG. 8 shows the flow when replacing the register set as a task context. Table 1 shows the meanings of the modify bits in FIGS. 1 and 4. Agent: Susumu Uchihara, patent attorney

Claims (1)

[Claims] In a microprocessor having a plurality of register sets, means for retaining information in one-to-one correspondence with the register set, and means for retaining information indicating that the register contents have been changed when the contents of the registers are changed. 1. A register saving method, comprising means for storing in said information holding means corresponding to said information holding means, and saving the contents of said register based on information in said information holding means.