JPH04207323A - Encoder circuit - Google Patents

Abstract

PURPOSE:To obtain an encoder circuit capable of performing fast encoding by deciding the time interval of input of input data based on the processing time of a variable length-fixed length conversion circuit. CONSTITUTION:The input of the input data to a variable length encoder circuit 3 is controlled by an input control circuit 2, and a control means 12 controls the input control circuit 2 so as to vary the time interval of input of the input data corresponding to the processing time of the variable length-fixed length conversion circuit 4. For example, to what bit length the input data is converted by the variable length encoder circuit 3 is found by a bit length generation circuit 11, and the control means 12 conforms the time interval of input of the input data to the processing time of the variable length-fixed length conversion circuit 4 by controlling the input control circuit 2 based on the bit length. Thereby, it is possible to eliminate null time to interrupt the processing of the variable length-fixed length conversion circuit 4, which accelerates encoding.

Description

[Detailed Description of the Invention] 1. Object of the Invention] (Industrial Application Field) The present invention relates to an encoding circuit, and particularly to an encoding circuit suitable for converting a Huffman code into fixed length data for two-image compression. Regarding.

<Conventional technology> In recent years, digital technology in electronic devices has made remarkable progress.
stomach. In the field of digital image processing technology, there has been remarkable progress in image compression technology. This image compression technique is a technique for encoding images at a smaller bit rate in order to improve the efficiency of digital transmission and recording. Examples of this technology include predictive coding technology and orthogonal coding technology (described in detail in ``Multidimensional Signal Processing of ITV Images'' by Takahiko Fukinuki, 1'' published by Kancho-Gyoshinkaisha). Furthermore, by applying variable length encoding to the codes compressed by these encodings, even further image compression is possible. Variable-length encoding changes the encoding bit width depending on the frequency of code occurrence, and can reduce the bit rate compared to fixed-length encoding.

Next, a method for generating a Huffman code as an example of a variable length code will be explained with reference to FIG. FIG. 3 (2i) shows the Huffman code generation process, and the third block (1) shows the Huffman code tree.

Now, the fixed length codes Sl, S2,...,S of one flight are
Let l be converted to a Huffman ladle number. Figure 3 shows t.
- An example of case 6 is shown. First, these box numbers S1
The Noji S6 are arranged in descending order of frequency of occurrence (probability of occurrence). The sum i + of the symbols S1 to 80 is shown in FIG.
), sea urchin, 0.3 each! ], 0.70°0.
15.0.15.0.10.0.05, and the code S1
[Nona] S6. Next, we combine the two codes starting from the one with the smallest probability of occurrence to create a set of seven self-probable i
Find (the sum of two occurrence probabilities). In Figure 31, the probability of occurrence of codes S6 and S5 is small, and their combined probability is 0.
．． It is 15.

Next, this set and other codes are rearranged in descending order of probability of occurrence (or composite probability). Next, the probability of occurrence (
From the small force, the two codes (or combinations) are set as a new set, and the combined probability is determined. Thereafter, these processes are repeated 5 until the combined probability becomes 1, as shown in FIG.

Next, based on FIG. 3 <a>, a code tree shown in the third r interval (b) is created. Then, according to the branching of this code tree, '0゛ and]' are assigned 4, Figure 3 ()))
In this case, the − upper branch is set to “0” and the l· side branch is set to 1′°. Along this branch, we obtain the Hanoma〉′ code.

For example, the fixed length code 84 passes through the "0" branch, the "1" branch, and finally the "O" branch, as shown by the thick line in FIG. 3 (+). The Huffman codes of codes 81 to S6 thus obtained are shown in Table 1 below.

Table 1 As shown in Table 1, when the probability of occurrence is high, it is converted to a Huffman code with a short bit length, and when the probability of occurrence is low, it is converted to a Huffman code with a long bit length.9As a result, The overall bit rate can be reduced.

Recently, standardization of image data compression force methods has been considered. According to this standard image compression technique, the fourth
As shown in the figure, after the image data is Huffman encoded, additional data is added to the lower bits. Only valid bits are included as additional data.
add For example, “1 pa and °15” in decimal representation are 2
Just as the number of bits in the decimal representation is different (] bit, 4 bits), additional data made up of only effective bits is also a variable length code like the Huffman code. Note that the lower bit side of the additional data is the valid bit, so
The additional data is added to the Huffman code in LSB first order, starting from the LSB (lower bits of fi).

When recording such variable length encoded data,
It is necessary to convert variable-length encoded data into fixed-length data based on the input format of the recording element before recording. For example, as a recording element, 1. When a C carnide is adopted, input/output is performed in ]pi1~shizukueα, and the encoded data must be converted to a fixed length of 8hill−.

FIG. 5 is a block diagram showing a conventional encoding circuit that converts such variable length Huffman code data into 8-hit fixed length data and outputs the converted data. Further, FIG. 6 is a flowchart for explaining the operation of the input clock generation circuit 5 in FIG. 5.

Input data such as image data is input through the input terminal 1, and the input control circuit I! Give to @2. The input control circuit 2 takes in input data at the timing of the input clock and outputs it to the Huffman encoding circuit 3.

The Huffman encoding circuit 3 converts the input data into a Huffman code, adds additional data, and outputs it to the variable length-fixed length conversion circuit 4. The variable length-fixed length conversion circuit B4 converts the input variable length data into fixed length data of predetermined bits and outputs the converted data.

Now, for example, two variable length data A and B successively output from the Huffman encoding circuit 3 are as shown in FIG. 7(a).
As shown in the shaded area in (b), it is assumed that the data is composed of 21 bits and 1.12 bits. 0I variable length-fixed length conversion circuit n4 converts the input variable length data P into fixed length data of 8 hits every 1 clock and outputs it. 16 pits out of 21 bits or 98 converted to fixed length and output
The remaining five bits (referred to as "sons" or "remaining bits") of the variable length data A, which are not converted into fixed data because they are less than a hit, are added to the beginning of the next variable length data B.

In this way, the variable length-fixed length conversion circuit 4 is then configured as shown in FIG.
) Converts the variable length data of 7biy, ti to fixed length. In this case, 16 bits out of 17 bits are converted to a fixed length in two clocks and output, and the remaining 1 bit is added to the beginning of the next data. thus,
=ir The variable length-fixed length conversion circuit 4 sequentially outputs fixed length data of 8-pill length.

In this way, the time required to convert variable length data into fixed length data in 1-byte units is based on the data length of the variable length data. In addition, variable length - fixed +,,
S:, even when converting circuit 4 converts data into fixed length data of 8 bit length for each data, it is actually necessary to add the remaining data to the next data, for example, 25 bits. It takes five clocks to convert bit length data to fixed length data.

Here, it is assumed that the maximum number of bits of input data is 25 bits. In this case, the variable length-fixed length conversion circuit 4
In consideration of the processing time, the input data is controlled to be input every five clocks using the input clock from the input clock generation circuit. This input clock generation circuit 5 includes a down counter 6, a flip-flop (hereinafter referred to as F
7 and an inverter 8.

The down counter 6 receives "3" from the input terminal, and
When the load terminal LD becomes low level (hereinafter referred to as "L"), the count output is preset to "3". The down counter 6 is connected to the clock CK shown in FIG.
J- is counted, the counter starts counting down from the value 1 to 3', and outputs a count output from the output terminal Q, not shown in FIG. 6(d).

When the count output reaches O, the down counter 6 outputs the ripple carry shown in FIG. 6(b) to the input terminal of the F door. F'F7 outputs the input clock at the timing of the next clock CK, as shown in the sixth diagram (c). This human power clock is input to the input control circuit B2 and is applied to the load end 10 via the inverter 8.

Thereafter, the same operation is repeated at 1L, Fig. 6(a).

As shown in <c>, a high power clock is generated every 5 clocks. The input control circuit 2 provides input data to the Huffman encoding circuit 3 in synchronization with this input clock.

By the way, as described above, when the data length of variable length data is relatively short, the time required for variable length to fixed length conversion is also short. For example, variable length to fixed length conversion may be completed three clocks after input data is input. Even in this case, the next input data will not be input until the secondary input clock is input. Therefore, in this case,
This results in vacant time in which no processing is performed for two clock periods in the variable-length/fixed-length conversion circuit 4, making it impossible to perform initial encoding at high speed6. When used for H-reduction, it took a long time to write to the memory card, so it was rated 8 points, meaning that it was not possible to take quick pictures at a relatively fast speed.

(Problems to be Solved by the Invention 15) As described above, in the conventional encoding circuit mentioned above, there is idle time in the variable length-to-identified length conversion process, and the conversion process takes a long time. There was a problem that it took time.

The present invention was made in view of such problems.
The present invention aims to provide an encoding circuit that can perform high-speed processing.

1. Configuration of the Invention] (Part 1 of the Solution to the Problem 1'811) The encoding circuit according to claim 1 of the present invention converts manual data into a variable length code and outputs variable length data. In a clockwise conversion circuit comprising an encoding circuit and an ilJ variable length-fixed length conversion circuit that converts the variable length data into fixed length data of a predetermined length of 1 and outputs it, The above-mentioned input is done overnight (■1)
an input control circuit for controlling input to the variable length encoding circuit;
5. A control stage for controlling the input control circuit so as to vary the input time interval of the input data according to the processing time of the variable length to fixed length conversion circuit. The encoding circuit according to claim 2 of the present invention converts input data into 6
■+1 for variable length encoding! An encoding circuit comprising: a variable length encoding circuit that outputs variable length data; and a variable length-fixed length conversion circuit that converts the vU variable length data into fixed length data of a predetermined bit length and outputs the converted length data. , an input control circuit for controlling the input of the input data to the i''T variable length encoding circuit, and an output of the input control circuit.
Bit 1 to find the bi-i and l-length when the ζhuman power data is right-handed by the q variable length sign ↓ conversion circuit.
(Enter the time interval of the input data in the Wii input by controlling the J control circuit.) The variable length and fixed length conversion circuits are equipped with control means for matching m1 during processing.

(Function) In the present invention, input of input data to the IjJ-variable length encoding circuit is controlled by the input control circuit6.
The control means controls the input control circuit so as to change the input time interval of the input data according to the processing time of the variable length-fixed length conversion circuit.

For example, how many bits of input data is processed by a variable length encoding circuit?
・Determine whether it is converted to a long bit length by the bit length generation record,
Based on this bit length, the control means controls the input control circuit to match the input time interval of the input data with the processing time of the variable length-fixed length conversion circuit. This allows variable length −
There is no longer any free time for the fixed length conversion circuit to interrupt processing.
This enables high-speed encoding.

(Embodiments) 1. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an encoding circuit according to the present invention. In FIG. 1, the same constituent elements as in FIG. 5 are designated by the same symbols (=t).

An input terminal 1 receives input data such as image data. The human power control circuit 2, which provides this person data to the input control circuit 2, takes in the input data at the timing of the person start and provides it to the Huffman encoding circuit 3.
It is also given to the bit length generating circuit 11.

The Huffman encoding circuit 3 converts the input data into a Huffman code, and also converts the input data into a Huffman code.
Adding the additional data, il variable length-fixed ((output to the conversion circuit 4. The variable length-fixed length conversion circuit 4 converts the input h] variable length data into 8-pips 1-parallel fixed length data. It is designed to be output as follows.

In this embodiment, the input clock 17 is generated by the input clock generation circuit 12.
In addition to the down counter (>), FF 7 and inverter 8, it has FFs 13.1/i and 15 and an adder 16. The output of the bit length generation circuit 11 is input to F'F 13. The bit length intervening circuit 11 has T'(, OM
etc., and converts this human data into a Huffman code to the address indicated by the input data,
When input data is input to the input data, the output circuit 11 stores data indicating the length when +r is added (,). The FF 13 outputs the pit length data of the output of 3, and outputs the output of the long generation time gii to the adder 16 at the timing of the input clock.

Adder 16 includes i'FI3. The outputs of ff5 are added together, the first three bits of the addition result are given to FF14, and the lower three bits I
Give to FF15. The FF 15 outputs the lower three bits of the output of the adder 16 to the adder 16 at the timing of the input clock. The FF 14 is configured to input the upper three bits of the output of the adder 16 to the input terminal of the down counter 6 at the timing of the input clock.

Now, suppose that the variable-length to fixed-length conversion circuit 4 converts IIJ variable-length data to fixed-length data with a length of 2 to the power of T). -) indicates the remainder (pi) or number. For example, variable length −1i′+
When the fixed length conversion circuit 4 outputs 8-bit fixed length data, the lower three bits of the output of the adder 16 result in a remainder hit of 1. @As mentioned above, the adder 16 inputs the number of output bits of the Huffman code north circuit 83 from FF 13, and inputs the remainder bit number from FF 15. That is, the output of the adder 16 is
It shows the data length of variable length data that the variable length to fixed length conversion circuit 14 attempts to convert by variable length to fixed length conversion processing until the next variable length data is input.

On the other hand, the upper three bits of the output of the adder 16 indicate how many pieces of fixed length data the variable length data is converted into, that is, how many clocks it takes to complete the variable length to fixed length conversion process. The time required for variable length-fixed length conversion is +2 clock periods (the value indicated by the lower 3 bits). In this embodiment, the upper three bits are used as a preset value of the town counter 6 to determine the time m1 interval between input data inputs.

The configurations of the down counter 6, F F7, and inverter 8 are the same as the conventional ones61.In other words, the town counter 6 is not supplied with an input clock of "1,°" via the inverter 8, and is connected to the input terminal L). The down counter 6 counts the clock CK 2, and when the count value becomes the minimum, it outputs the ripple N Yary to the input terminal of FF7.FF7 is clocked at the timing of the clock CK after the ripple carry. An input clock is generated and output to the input control circuit 2 and the inverter 8.

Next, the operation of the encoding circuit refined in this way will be explained with reference to the timing chart in FIG.

FIG. 2(a) shows the clock CK, No. 21J(b) shows the ripple Nyari from the down counter 6, and the second
D16 (c) shows the input clock 5, Fig. 2 (d) shows the output of FF13, Bo L5, Fig. 2 (e) shows the output of r; Fig. 2(g) shows the output of FF14, Fig. 2(h) shows the output of FF16.
) indicates the count output of the town counter 6.

Input control times &! 82, '-(The input data is given to the Huffman encoding circuit 3 and Huffman encoded,
Variable length-fixed length conversion circuit 4 by adding additional data to the history
give to The variable length-fixed length conversion circuit 4 converts the input variable length data into 8-bit fixed length data every clock and outputs the converted data. The variable-length to fixed-length conversion circuit 4 adds the remaining bits to the beginning of the next input variable-length data, and sequentially performs variable-length to fixed-length conversion.

On the other hand, the input data from the input control circuit B2 is also input to the bit length generation circuit B11. The bit length generation circuit 11 outputs to F F 13 data indicating the bit length when this input data is Huffman encoded and the addition data is added. A series of a plurality of input data are processed by the Huffman encoding circuit 3 at 13°9.20,11 . ... shall be converted into bits. For example, assume that data input at the timing of the input clock Kl in FIG. 2(C) is converted into 13-bit data by the Huffman encoding circuit 3. It is assumed that, at this point, there are no remaining bits.

In this case, F F 13.15 each has a number of bits of 13
Data indicating 0 is given to the adder 16 (Fig. 2(d)
, (e)), the adder 16 adds the two inputs, gives the upper 3 bits (“1”) to the FF 14, and gives the lower 3 bits (°5
'') to F F i5 (Fig. 2(g)).

(e)), the FF 14 gives a preset value "1" to the down counter 6. The down counter 6 loads this value into the input clock at timing 2, and starts counting down at the next clock CK. After 2 to 2 clocks from the input clock, the count value becomes "0", and the down counter 6 outputs the ripple carry to FF7 as shown in FIG. 2(b). 2 is generated as the input clock shown in FIG.

Further, at timing 2 of the input clock, the input control circuit 2 takes in input data having a data length of 9 bits by Huffman encoding. Variable length-fixed length conversion for this input data is performed after three input clocks occur. 2 to the input clock causes FF13 and FF15 to become "9" respectively.
”, “5”” are output to the adder 16.The adder 16 outputs the top three of the values “14” obtained by adding the two human forces
Outputs (“1”) to FF14, lower 3 bits
“6”) is output to the FF15. As before, "1" is loaded into the town counter 6 by 3 in the input clock (Figure 2 (tl)), and the input clock is changed from 3 to 3.
After the clock, 4 is generated as an input clock from FF7.

At timing 3 of the input clock, the input control circuit 2 takes in input data having a data length of 20 bits by Huffman encoding. 3 to 4 for input clock
The number of remaining bits in the variable length-fixed length conversion process during the period is 6 bits, and the adder 16 outputs "26°" data.The upper 3 bits ("3") of the adder 16 are F
Output to F14, lower 3 bits (°"2") are FF
1! output to l.

The preset value "3" from the FF 14 is o-i'd to the down counter 6 at the timing of 4 in the input tarlock.

In this way, the next input clock is generated from FF7 four to five clocks after the input clock.

Thereafter, the same process is repeated, and the input time interval is switched according to the processing time of variable length to fixed length conversion.

In this way, in this embodiment, the bit length generation circuit 1
1 to obtain the bit length by variable length encoding, and by adding this bit length and the number of remaining bits from the previous time using an adder 16, the bit length of the variable length data to be converted from variable length to fixed length this time is obtained. By using the upper bits of the output of the adder 16 as the preset value of the down counter 6, the timing for inputting the next data is made based on the variable length data length and the number of remaining bits.

As a result, the time interval until the next data is input is equal to the processing time of variable length - fixed length conversion, and the time interval until the next data is input is equal to the processing time of variable length - fixed length conversion.
There is no idle time during which no processing is performed in the fixed length conversion circuit 4, and high-speed encoding is possible.

[Effects of the Invention] As explained above, according to the present invention, the input time interval of input data is made based on the processing time of the variable length-fixed length conversion circuit, so high-speed encoding is possible. It has the effect that it is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the encoding circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment, and FIG. 3 is an explanatory diagram for explaining Huffman codes. FIG. 4 is an explanatory diagram showing image data, FIG. 5 is a block diagram showing a conventional encoding circuit, FIG. 6 is a timing chart to explain the operation of the conventional example, and FIG. 7 is an illustration of the operation of the conventional example. 6 is an explanatory diagram for explaining 2... input control circuit, 3... Huffman encoding circuit,
4...Variable length-fixed length conversion circuit, 12...Input clock generation circuit. -N1 dimension 0Φ C/)CQ ω of ψ Fig. 7(b)

Claims (2)

[Claims] (1) A variable-length encoding circuit that variable-length encodes input data and outputs variable-length data, and a variable-length-fixed-length conversion circuit that converts the variable-length data into fixed-length data of a predetermined bit length and outputs it. An encoding circuit comprising: an input control circuit that controls input of the input data to the variable length encoding circuit; and an input control circuit that controls input of the input data according to a processing time of the variable length-fixed length conversion circuit. An encoding circuit comprising: control means for controlling the input control circuit so as to change a time interval. (2) A variable-length encoding circuit that variable-length encodes input data and outputs variable-length data; and a variable-length-fixed-length conversion circuit that converts the variable-length data into fixed-length data with a predetermined bit length and outputs it. an input control circuit for controlling input of the input data to the variable length encoding circuit; and an input control circuit for controlling input of the input data to the variable length encoding circuit; A bit length generation circuit that calculates the bit length when encoded, and the input control circuit based on the bit length calculated by this bit length generation circuit, so that the input time interval of the input data is changed to the variable length. - a control means for matching the processing time of the fixed length conversion circuit.