JPH05304480A - Fixed length converting circuit - Google Patents

Abstract

PURPOSE:To accelerate a variable length/fixed length conversion processing. CONSTITUTION:In an adder 22, the low-order 3 bits of output are fed back thorugh an FF 23 and valid bit numbers and the low-order 3 bits the added. The low-order 3 bits of the output of the adder 22 indicate the remaining bit numbers from the previous time and an adder 28 attains shifting amount fromt these low-order 3 bits and Huffman code length. A parallel shifting circuit 21 shifts input data to the MSB side for the shifting amount and supplys the data to an 8-bit fixed length circuit 30. A control clock generating circuit 31 controls the processing of the 8-bit fixed length circuit 30 using the high-order 3 bits of the adder 22. The 8-bit fixed length circuit 30 is supplied with the 7-bit length output indicating the remaining bits from a decoding circuit 40 and synthsizes the remaining bits in the previous fixed length converting processing and the valid bits of the input data consecutively to be outputted in parallel at every 8-bit unit. The input data are processed in parallel so that the 8-bit fixed length converting processing can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fixed length conversion circuit suitable for an electronic still camera or the like capable of high speed encoding processing.

[0002]

2. Description of the Related Art In recent years, the progress of digital technology in electronic equipment has been remarkable. In the field of digital image processing technology, progress in image compression technology is remarkable. This image compression technique is a technique for encoding an image with a smaller bit rate in order to improve the efficiency of digital transmission and recording. This technology includes predictive coding technology and orthogonal coding technology (“multidimensional signal processing of TV images”).
Fukubuki Takahiko, detailed in the Nikkan Kogyo Shimbun)) etc. Furthermore, for codes compressed by these encodings,
By applying variable length coding, further image compression is possible. Variable-length coding changes the bit width of coding according to the frequency of code generation, and can reduce the bit rate compared to fixed-length coding.

Next, a method of generating a Huffman code as an example of a variable length code will be described with reference to FIG. FIG. 9A shows a Huffman code generation process, and FIG. 9B shows a Huffman code tree.

Now, t fixed length codes S1, S2, ...
Let St be converted to Huffman code. In FIG. 9, t =
An example in the case of 6 is shown. First, these codes S1 to S6 are arranged in descending order of occurrence frequency (occurrence probability). The occurrence probabilities of the symbols S1 to S6 are 0.35, 0.20, 0.15, 0.15, 0.10 and 0.05, respectively, as shown in FIG. 9A, and are arranged in the order of the symbols S1 to S6. Next, the combination probability (sum of two occurrence probabilities) is calculated by setting two codes from the smallest occurrence probability as one set. In FIG. 9, the occurrence probabilities of the symbols S6 and S5 are small, and the combination probability thereof is 0.15.

Next, this set and other codes are rearranged in the descending order of occurrence probability (or combination probability). Next, two codes (or sets) from the smallest occurrence probability (or combination probability) are set as a new set, and the combination probability is obtained. After that, these processes are repeated, and as shown in FIG. 9A, rearrangement is performed until the synthesis probability becomes 1.

Next, based on FIG. 9A, FIG.
Create a tree of codes shown in. Then, "0" and "1" are assigned according to the branching of the tree of this code. Figure 9 (b)
Then, the upper branch is set to "0" and the lower branch is set to "1". A Huffman code is obtained along this branch. For example, the fixed-length code S4 passes through the branch of "0", the branch of "1", and finally the branch of "0", as shown by the thick line in FIG. Is converted to the Huffman code ". Code S1 obtained in this way
The Huffman codes from S6 to S6 are shown in Table 1 below.

[0007]

[Table 1] As shown in Table 1, when the occurrence probability is high, it is converted into a Huffman code having a short bit length, and when the occurrence probability is low, it is converted into a Huffman code having a long bit length. Thereby, the bit rate can be reduced as a whole.

By the way, recently, standardization of a compression method of image data has been studied. In an example of this standardization proposal, as shown in FIG. 10, after Huffman coding of image data, additional data is added to the lower bits. Only valid bits are added as additional data. For example, since the number of bits in the binary representation is different between the decimal representation "1" and "15" (1 bit, 4 bits), the additional data composed of only valid bits has a variable length like the Huffman code. It is a code. Since the lower bits of the additional data are effective bits, the additional data is added to the Huffman code by LSB first arranged in order from the LSB (least significant bit).

When recording such variable-length coded data, it is necessary to convert the variable-length coded data into a fixed length based on the input format of the recording element before recording. For example, when an IC card is used as the recording element, input / output is performed in 1-byte units, and encoded data must be converted into a fixed length of 8 bits.

FIG. 11 is a block diagram showing a conventional fixed length conversion circuit for converting such variable length Huffman code data into 8-bit fixed length data. In addition, in FIG. 11, the state of the signal of each part is also illustrated, and M is the MSB.
(Most significant bit), and L indicates LSB. Also, valid data is indicated by diagonal lines.

The Huffman code register 1 and the additional bit register 2 store independently generated Huffman code data and additional data, respectively. The Huffman code register 1 has a bit width capable of storing the Huffman code having the maximum bit length, and the additional bit register 2 has a bit width capable of storing the additional data having the maximum bit length. For this reason,
Invalid data 5 and 6 are stored in each of the registers 1 and 2 in addition to the valid data 3 and 4 shown by hatching in FIG.

The outputs of the registers 1 and 2 are combined as shown by the signal 7 and given to the serial conversion shifter 8. The serial conversion shifter 8 serially converts the input data and then shifts it. The output of the serial conversion shifter 8 is given to the fixed length circuit 10 through the extra bit addition circuit 9. The fixed length circuit 10 converts serial data that are sequentially input into 8-bit parallel fixed length data and outputs the parallel fixed length data. Fixed length circuit
When the data obtained by parallel conversion is less than 8 bits, 10 outputs each bit of this data (hereinafter referred to as a remainder bit) to the remainder bit addition circuit 9, and
The bit number (remainder bit number) is output to the shift amount calculation circuit 11. For example, the total number of effective bits of the Huffman code and the additional data input to the fixed length circuit 10 is 26.
If it is a bit, the fixed-length circuit 10 outputs three sets of 8-bit fixed-length data, and feeds the 2-bit remainder bit back to the remainder-bit addition circuit 9.

In the fixed length conversion process, it is necessary to make the remaining bits and the valid data 3 and 4 continuous. Therefore, the synthetic data 7 is shifted by the serial conversion shifter 8. The shift amount is obtained by the shift amount calculation circuit 11. The shift amount calculation circuit 11 is also provided with information on the effective bit number of the Huffman code and the additional data, and obtains the shift amount by subtracting the effective bit number and the surplus bit number from the maximum bit number of the data. The serial conversion shifter 8 converts the data into serial data and then shifts it by 1 bit in accordance with the clock. Therefore, the fixed-length conversion processing requires time for the number of bits to be shifted.

As shown by the signal 12, the serial conversion shifter 8 arranges the invalid data (half-tone line portion) for the number of surplus bits at the head of the output data string, and the Huffman code and the effective bit (oblique line) of the additional data in the center. Section) and outputs the data in which the invalid bits are arranged on the LSB side. This data is applied to the surplus bit addition circuit 9. The surplus bit adding circuit 9 is
As shown by the satin pattern portion of the signal 13, the surplus bit 14 of the previous data is added to the head of the effective bit of the next data and given to the fixed length circuit 10. In this way, the fixed-length circuit 10 sequentially outputs parallel data of 8-bit length regardless of the number of bits of the Huffman code and the additional data.

In order to simplify the processing, the serial conversion shifter 8 converts the input data to serial when shifting the effective bit of the additional data. Therefore, it takes a long time to perform the fixed length conversion process. Therefore, for example, when it is used for compressing image data of an electronic still camera, it takes a long time to write to a memory card, and there is a problem that continuous shooting cannot be performed at a relatively high speed. It was

[0016]

As described above, the conventional fixed length conversion circuit described above has a problem that it takes a long time for the conversion process.

An object of the present invention is to provide a fixed length conversion circuit capable of high speed processing.

[0018]

In a fixed length conversion circuit according to the present invention, data indicating the effective bit length of input variable length data is given and the lower n bits of the output are fed back to be fed back to the effective bit length. Shift means for adding the lower n bits and the lower n bits and the data of the effective bit length to obtain a shift amount for making the remaining bits and the effective bit in the previous fixed length processing continuous. Quantity calculating means, shift means for bit-shifting and outputting the input variable-length data based on the shift amount, effective bits of the output of the shift means and the remainder using lower n bits of the output of the adding means. The combining data is obtained by using combining means for obtaining combined data in which bits are consecutive and data from the most significant bit to the lower n + 1 bits of the output of the adding means. To a fixed-length data of n-bit length, and a control clock generation means for controlling the processing timing, and a fixed-length conversion processing of the synthetic data in n-bit units using the clock from the control clock generation means, and output. And a fixed length means.

[0019]

In the present invention, the adding means adds the data indicating the effective bit length of the input variable length data and the lower n bits of the output. The lower n bits of the addition result indicate the number of residual bits in the previous n-bit fixed length conversion processing, and the shift means bit-shifts the input variable length data using the lower n bits and the effective bit length data and outputs the data. .. The synthesizing means obtains synthetic data in which the remainder bits and the effective bits are consecutive by using the lower n bits, and gives them to the fixed length means.
The control clock generating means controls the processing of the fixed length means by using the data from the most significant bit to the lower n + 1 bits of the output of the adding means. In this way, the fixed length means outputs fixed length data having an n-bit length.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a fixed length conversion circuit according to the present invention. This embodiment shows an example in which image data composed of a Huffman code having a maximum bit length of 16 bits and additional data having a maximum bit length of 11 bits is converted into parallel fixed-length data having an 8-bit length.

First, the operating principle of this embodiment will be described with reference to FIG. The Huffman code having a maximum length of 16 bits and the additional data having a maximum length of 11 bits are combined, and parallel data in which effective bits are consecutive is input as shown by a hatched portion in FIG. In all the 27-bit parallel data, the LSB of the Huffman code is always located at a fixed position.

Next, as shown in FIGS. 2 (a) and 2 (b),
This parallel data is bit-shifted. Now, assuming that the Huffman code is y bits and the remaining bits in the previous encoding are h bits, in the present embodiment, x bits shown in the following equation (1) are shifted to the MSB side.

X = 16−h−y (1) As a result, the invalid data is arranged on the MSB side by the extra bits, and the Huffman code and the additional data are continuous on the LSB side of the invalid data. Next, as shown in FIG. 2C, the surplus bits are arranged in the invalid data portion on the MSB side,
Finally, 8 bits are output in parallel from the MSB side (FIG. 2 (a)). In this way, 8-bit fixed length conversion is performed.

In FIG. 1, the combined data of the Huffman code and the additional data shown in FIG. 2A is a parallel shift circuit.
Give to 21. On the other hand, the adder 22 includes a parallel shift circuit 21
The effective bit number e of the composite data given to Adder
22 adds the number of effective bits e and the output of a flip-flop (hereinafter referred to as FF) 23, and gives the lower 3 bits of the addition result f to FFs 23 and 24 and the upper 3 bits to FF 25. F
F23 gives the lower 3 bits g of the output of the adder 22 one clock before to the adder 22 at the timing of the input clock. Thus, partial integration is performed by the adder 22 and the FF 23. The lower 3 bits of the FF23 output indicate the remainder obtained by dividing the bit length by 8, that is, the number of remainder bits in the case of performing fixed length conversion into 8-bit data. The adder 22 adds the remaining bit number in the previous conversion process from the FF 23 and the effective bit number e of the input data and outputs the result.

Now, assuming that an 8-bit fixed-length circuit 30 described later converts variable-length data into fixed-length data having a power of 2 to the n-th bit, the number of surplus bits is indicated by the lower n bits of the output of the adder 22. .. For example, 8-bit fixed length circuit
When 30 outputs 8-bit fixed-length data, the number of surplus bits is indicated by the lower 3 bits of the adder 22 output.

The FF 24 outputs the surplus bit number h to the adder 27 via the inverter 26 at the timing of the clock ck. The adder 27 adds the output of the inverter 26 and “16” and outputs the result to the adder 28. The Huffman code length y is inverted by the inverter 29 and input to the adder 28.
The adder 28 adds the output of the adder 27 and the inverted output of the Huffman code length y. The adder 27, 28 calculates the above equation (1) to obtain the shift amount x. Since the maximum bit length of Huffman code is clear,
In this embodiment, adding "16" is omitted. The shift amount x is given to the parallel shift circuit 21.

FIG. 3 is a block diagram showing a specific structure of the parallel shift circuit 21 shown in FIG.

The LSBa0 to MSBa26 of the composite data input to the parallel shift circuit 21 are applied to the terminals 1 of the selectors S0 to S26, respectively, and the terminals 1 of the selectors S27 to S33 are supplied.
Also give MSBa26. "0" is applied to the terminals 2 of the selectors S1 to S6, and outputs a0 to a26 are applied to the terminals 2 of the selectors S7 to S33. Further, "0" is given to the terminals 3 of the selectors S1 to S14, and the selectors S15 to S33 are
A0 to a18 are applied to the terminal 3 of.

In this embodiment, the shift amount x can be represented by 5 bits, and the upper 2 bits of the shift amount x are given to the control terminals s of the selectors S0 to S33. Selector S
0 to S33 output the data input to the terminal 1 when the value input to the control terminal s is 0, output the data input to the terminal 2 when the value is 1, and output the terminal 3 when the value is 2 Output the input data. That is, the selectors S0 to S33
By this, parallel shift in 8-bit units is possible.

Outputs SO0 to S of selectors S0 to S33
O33 is given to the terminals 0 of the selectors SS0 to SS33, respectively. In addition, the outputs SO0 to SO32 are respectively connected to the selector SS1.
Through SO33 to terminals 1 and outputs SO0 through SO31 to terminals 2 of selectors SS2 through SS33, respectively. Thereafter, similarly, each output is shifted to select the selectors SS0 to S0.
It is given to each terminal 0 to 7 of S33, for example, selector SS7
Outputs SO0 to SO26 are applied to terminals 7 to SS33. Selectors S to which outputs SO0 to SO33 are not input
"0" is given to the terminals of S0 to SS33.

The lower 3 bits of the shift amount x are given to the control terminals s of the selectors SS0 to SS33. The selectors SS0 to SS33 select and output the data input to the terminal having the same number as the value input to the control terminal s. As a result, the selectors SS0 to SS33 perform parallel shift on the data input by 0 to 7 bits to output the outputs b0 to b33 to 8 bits.
Output to the fixed bit length circuit 30.

As described above, the adder 22 adds the number of effective bits and the number of residual bits from the FF 23. That is, the upper 3 bits of the output f of the adder 22 indicate how many pieces of variable-length data are converted into 8-bit fixed-length data, that is, how many clocks the variable-length to fixed-length conversion process ends. There is. In this embodiment, the time required for the variable length-fixed length conversion is (the value indicated by the upper 3 bits) +2 clock periods. By supplying the upper 3 bits to the control clock generating circuit 31 via the FF 25, the operation timing of the variable length-fixed length conversion processing is controlled.

FIG. 4 is a block diagram showing a specific structure of the control clock generating circuit 31 in FIG. FIG. 5 is a timing chart for explaining the operation of FIG.
FIG. 5 shows an example in which the value of the upper 3 bits is 2.

The upper 3 bits from the FF 25 are given to the data terminal D of the down counter 32. The down counter 32 receives the data end D according to the output from the inverter 33 (FIG. 5 (d)).
The value of the upper 3 bits is loaded into (FIG. 5 (c)). The down counter 32 counts down the clock MCK (FIG. 5A). The count output Q is as shown in FIG. When the down counter 32 counts down,
The ripple carry k shown in FIG. 5 (f) is output. FF
34 applies this ripple carry k to the 8-bit fixed length circuit 30 as the clock ck (FIG. 5B) at the timing of the clock MCK. Further, the clock ck is synchronized with the clock MCK by the FF 35 and supplied to the load end LO through the inverter 33. In this way, the next clock ck is generated after the passage of (the value of the upper 3 bits + 2) MCK clocks from the generation of the clock ck. This clock ck
Is supplied to the 8-bit fixed length circuit 30.

The lower 3 bits of the adder 22 are applied to the decoding circuit 40. The decoding circuit 40 converts the input surplus bits into 7-bit data and outputs the data. As shown in Table 2 below, the output of the decoding circuit 40 is 7-bit data in which "0" continues from the LSB side by the value indicated by the lower 3 bits and the other bits are "1". Decoding circuit 40
Is output to the 8-bit fixed length circuit 30.

[0036]

[Table 2] Further, the upper 3 bits of the adder 22 are given to the 8-bit fixed length circuit 30 as a signal m through the FF 25, FF 41, the AND circuit 42, FF 43 and FF 44. The signal m becomes low level (hereinafter referred to as "L") only when all the upper 3 bits of the output of the adder 22 are "0".

FIG. 6 is a block diagram showing a specific structure of the 8-bit fixed length circuit 30 shown in FIG.

34-bit output b of the parallel shift circuit 21
0 to b34 are selectors SA of the 8-bit fixed length circuit 30, respectively
0 to the terminal of SA33. Selectors SA0 to S
Outputs O0 to O18 of A18 are applied to terminals 0 of selectors SA8 to SA26 via FFA0 to A18, respectively, and outputs O19 to O25 of selectors SA19 to SA25 are applied to terminals 1 of selectors SB27 to SB33 via FFA19 to A25, respectively. .. The outputs of the selectors SB27 to SB33 are the selector SA.
27 to SA33 terminal 0. Selector SA26 to S
The outputs O26 to O33 of A33 are output as 8-bit parallel data via the FFAs 26 to A33, respectively. As will be described later, simultaneously with the output of 8-bit parallel data from FFA26 to A33, the data from FFA0 to A25 is shifted by 8 bits to the selector on the MSB side.

Clock c from control clock generation circuit 31
k is given to the series circuit of FF51,52. The FFs 51 and 52 delay the clock ck by 2MCK clocks to obtain the clock c.
k1 is given to the selectors SA0 to SA26. Selector S
A0 to SA26 are high levels of the clock ck (hereinafter,
Select the terminal 1 with "H") and select parallel shift circuit
The output of 21 is taken in and outputted, terminal 0 is selected by "L" and the selector output on the 8-bit LSB side is taken in and outputted.

The remainder bits output from the selectors SA27 to SA33 are combined with the output of the parallel shift circuit 21 and output in the next fixed length conversion process. That is,
In this case, the selectors SA27 to SA33 are controlled by signals ii6 to ii0, which will be described later, to take in and output the outputs of the selectors SB27 to SB33. The outputs of the selectors SA27 to SA33 are also given to the terminals 0 of the selectors SB27 to SB33 via the FFB27 to B33, respectively. The signal m is fed to the selectors SB27 to SB33 by FF53.
Given through the selectors SB27 to SB33.
Selects 8-bit LS by selecting terminal 1 by "H" of signal mm
Selector SA27 to SA by taking in the selector output on the B side
Output to 33, select terminal 0 with "L" and select SA27
To the output of SA33 (remainder bit) and the selector S
Output to A27 to SA33. Therefore, when the sum of the previous remaining bits and the number of effective bits of the combined data is less than 8 bits (m is “0”), the selector outputs on the 8-bit LSB side are not shifted to the selectors SA27 to SA33.

The synthesis of the remainder bits and the output of the parallel shift circuit 21 is controlled by the 7-bit output i of the decoding circuit 40. That is, the bits i0 to i6 of the output i are given to the AND circuits C33 to C27 via the FF54, respectively.
The clock ck1 is also applied to the AND circuits C33 to C27, and the outputs ii0 to ii6 are applied to the selectors SA33 to SA27 during the "H" period of the clock ck1.

The clock ck is applied to the NOR circuit 57 via the FFs 55 and 56, and the output of the FF 56 is output to the NOR circuit 57.
Give to. The output of the NOR circuit 57 is given to the AND circuit 58, and the AND circuit 58 outputs the logical product of the output of the NOR circuit 57 and the clock MCK to the FFA0 to FFA33 as the clock ACK. Therefore, when the clock ck before and after 1 MCK clock is “L”, the next MC
A clock ACK is generated at the timing of K clocks.
FFA0 to FFA at the timing of this clock ACK
33 outputs the outputs O0 to O33 of the selectors SA0 to SA33. That is, the 8-bit fixed-length output is output by (the number of MCK clocks between clocks ck) -1, and the remaining bits are not output.

Next, the operation of the embodiment thus constructed will be described with reference to the explanatory view of FIG. 7 and the timing chart of FIG. Timings A to F in FIG. 7 indicate respective timings of the MCK clocks A to F in FIG. 8, respectively. FIG. 7A shows the outputs of FFB27 to B33, and FIG.
7B shows 8-bit parallel data from the parallel shift circuit 21, FIG. 7C shows outputs ii0 to ii6 of the AND circuits C33 to C27, and FIG.
A0 to SA33 outputs O0 to O33 are shown and FF
The outputs of A0 to FFA25 are shown in parentheses in FIG.
(E) shows the outputs d of the FFA 27 to A 33. 8A shows the MCK clock, FIG. 8B shows the clock ck, FIG. 8C shows the clock ck1, FIG. 8D shows the output i, and FIG. 8) shows the outputs ii0 to ii6 from the AND circuits C33 to C27, FIG. 8 (f) shows the clock ACK, and FIG. 8 (g) shows the signal m.
8 (h) shows the signal mm.

As shown in FIG. 2A, the parallel shift circuit 21 is supplied with composite data of a Huffman code having an effective bit length of 8 bits and additional data having an effective bit length of 6 bits from a register (not shown). Shall be. At this point, the remaining bits in the previous fixed length conversion process are 3 bits, and the effective bit length of the Huffman code and the additional data of the next input synthetic data are both 2 bits. Furthermore, the effective bit lengths of the Huffman code and the additional data of the synthetic data input next are 3 bits and 2 bits, respectively.

The effective bit number e (= 14) is given to the adder 22. The lower 3 bits of the output f of the adder 22 indicate the number of residual bits in the 8-bit fixed length conversion processing, and the FF 23 calculates the number of residual bits at the timing of the clock ck.
Output to 22. The adder 22 adds the effective bit number e and the output of the FF 23 to indicate the remaining number of bits in the fixed length conversion processing of this time by the lower 3 bits, and the upper 3
The number of parallel data by the current 8-bit fixed length conversion processing is shown by the bit.

The lower 3 bits are given to the decoding circuit 40 via the FF 24, the conversion of Table 2 is performed, and the output i of 7-bit length is output to the 8-bit fixed length circuit 30. Also, the bottom 3
The bits are supplied to the adder 27 via the inverter 26 as the remainder bit h. Further, the output of the adder 27 is given to the adder 28,
The adder 27, 28 calculates the above equation (1), obtains the shift amount x, and supplies it to the parallel shift circuit 21.

In this case, since the shift amount x is 5, the selectors S0 to S33 of the parallel shift circuit 21 select the terminal 1 and the selectors SS0 to SS33 select the terminal 5. As a result, the parallel shift circuit 21 operates as shown in FIG.
As shown in (b), the input data is converted into a 5-bit MS.
It is shifted to the B side and output to the 8-bit fixed length circuit 30.

On the other hand, the upper 3 bits of the output of the adder 22 are FF
It is given to the control clock generation circuit 31 via 25. The down counter 32 of the control clock generation circuit 31 receives the signal shown in FIG. 5D at the load end LO and loads the value (2) of the upper 3 bits. The down counter 32 starts down counting by the MCK clock, and outputs a ripple carry k shown in FIG. 5 (f) when counting down. This ripple carry k is output to the 8-bit fixed length circuit 30 as a clock ck via the FF34. Since the number of remaining bits in the fixed length conversion processing this time is 1, and the number of effective bits of the next input data is 4, the value of the upper 3 bits of the output of the next adder 22 is “0”. , Fig. 8
MCK clocks C and D as shown in FIG.
k is generated at an interval of 2MCK clocks. Further, since synthetic data having an effective bit length of 5 bits is input next, the value of the upper 3 bits of the output of the next adder 22 becomes "1", and the next clock ck is generated at 3MCK clock intervals (Fig. 8). (A), (b)).

Thus, as shown in FIG. 7B, the terminals 1 of the selectors SA0 to SA9 of the 8-bit fixed length circuit 30.
Is input to the terminals SA of the selectors SA10 to SA23, the additional data and the valid bit of the Huffman code are input to the terminals SA1 to SA26, and the invalid data is input to the terminal 1 of the selectors SA24 to SA26. Output i of decoding circuit 40 (“111
1000 ") is the clock c as shown in FIG.
It is given to the FF 54 at the timing of k. Also clock ck
Is delayed by 2MCK clocks by FF51 and FF52 and given to AND circuits C27 to C33 as clock ck1.
The outputs i0 to i6 of the FF 54 are output ii0 to ii6 (see FIG. 7) at the timing of the MCK clock A in FIG.
It is supplied to the selectors SA33 to SA27 as (c)). As a result, the selectors SA31 to SA33 select the outputs of the selectors SB27 to SB33, respectively, and the FFA23 to AFA are selected.
Take in the surplus bit from the previous time from 25 (the matte pattern part in Fig. 7 (d)).

On the other hand, the clock ck is 1M by the FF55.
It is delayed by the CK clock period and given to the NOR circuit 57, and delayed by 2FFK clock periods by the FFs 55 and 56 and given to the NOR circuit 57. The AND circuit 58 obtains the logical product of the output of the NOR circuit 57 and the MCK clock and outputs it as an ACK clock, and the ACK clock indicates a fixed length output number. As shown in FIG. 8, an ACK clock is generated at the timing of MCK clock B, and as shown at timing B of FIG. 8 bits of data consisting of the effective bits of are output in parallel. Further, FFA0 to A25 are output O0 of the selector.
To O25 are applied to the selectors SA7 to SA33 to shift them to the 8-bit MSB side (FIG. 7 (d)).

Further, in this case, the lower 3 bits of the output of the adder 22 become "0", and as shown in FIG.
The signals ii0 to ii6 all become "0", and the selectors SA27 to SA33 select the outputs of the selectors SB27 to SB33.

The same operation is performed at the next MCK clock C timing, and the FFA23 to FFA33 output the Huffman code and the effective bit of the additional data. The output O25 (remainder bit) of the selector SA25 is given to the selector SB33 via the FFA25 (timing C in FIG. 7D). On the other hand, the next data (timing C in FIG. 7B) is input to the terminals 1 of the selectors SA0 to SA32 by the clock ck generated at the timing of the MCK clock C. The decoding circuit 40 outputs i (“1111110”) indicating that the number of remaining bits is 1 (FIG. 8D).
To the FF54 and output ii0 of the AND circuit C33.
As shown in FIG. 8E, the selector SA33 selects the output (remainder bit) of the selector SB33 at the timing of the MCK clock D.

At the timing of this MCK clock D,
The effective bit length is less than 8 bits, and the ACK clock is not generated as shown in FIG. At the timing of the MCK clock next to the MCK clock D, the output m (FIG. 8 (g)) of the FF44 of FIG. 1 becomes "L", and the signal mm becomes "L" at the timing of the MCK clock E, and the selectors SB27 to SB27 through SB33 selects the outputs of the selectors SA27 to SA33, respectively. On the other hand, at the timing of the MCK clock E, the next data having 5 effective bits is input to the terminals 1 of the selectors SA0 to SA28. Selector SA24 to SA
33 captures these remainder bits and the valid bits of the input data (hatched portion of timing E in FIG. 7D) at the timing of MCK clock E.

At the next MCK clock F timing,
The valid bit selected by the selectors SA26 to SA33 is AC
The signals are output from FFA26 to A33 by K clock.
The outputs O24 and O25 of the selectors SA24 and SA25 are FF.
It is supplied to the terminal 1 of the selectors SB32, SB33 via A24, A25. After that, the same operation is repeated, and 8-bit parallel data is sequentially output.

As described above, in this embodiment, the parallel shift circuit 21 shifts the input parallel data in parallel without converting it to serial data, and the 8-bit fixed length circuit 30 sequentially shifts the 8-bit fixed length by several clocks. The data is converted and output, and high-speed variable-to-fixed length conversion is possible.

[0056]

As described above, according to the present invention, there is an effect that high speed processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a fixed length conversion circuit according to the present invention.

FIG. 2 is an explanatory diagram for explaining the operation principle of the embodiment.

FIG. 3 is a block diagram showing a specific configuration of a parallel shift circuit in FIG.

4 is a block diagram showing a specific configuration of a control clock generation circuit in FIG.

5 is a timing chart for explaining the operation of FIG.

FIG. 6 is a block diagram showing a specific configuration of an 8-bit fixed length circuit in FIG.

FIG. 7 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 8 is a timing chart for explaining the operation of the embodiment.

FIG. 9 is an explanatory diagram for explaining a Huffman code.

FIG. 10 is an explanatory diagram for explaining a combination of Huffman code and additional data.

FIG. 11 is a block diagram showing a conventional fixed length conversion circuit.

[Explanation of symbols]

21 ... Parallel shift circuit, 22, 27, 28 ... Adder, 30 ... 8
Bit fixed length circuit, 31 ... Control clock generation circuit, 40 ... Decode circuit

Claims (1)

[Claims] 1. Addition in which data indicating the effective bit length of input variable-length data is given and lower n bits of output are fed back to add the effective bit length and the fed back lower n (n is a natural number) bits. Means for calculating a shift amount for making the remainder bit and the valid bit in the previous fixed length processing continuous by using the lower n bits and the data of the valid bit length; and the input variable length. Shift means for bit-shifting and outputting the data based on the shift amount; and composite data in which the effective bit and the remainder bit of the output of the shift means are consecutively formed by using the lower n bits of the output of the adding means. A fixed length data of n-bit length is obtained by using the synthesizing means for obtaining and the data from the most significant bit to the lower n + 1 bits of the output of the adding means. Control clock generation means for controlling the processing timing in the case of conversion, and fixed length means for performing fixed length conversion processing of the synthesized data in units of n bits using the clock from the control clock generation means and outputting the fixed data are provided. Fixed length conversion circuit characterized by.