JPS6228113Y2 - - Google Patents

Description

[Detailed explanation of the idea]

(Technical Field of the Invention) The present invention relates to an encoding circuit that counts and encodes counting pulses, and in particular divides a coded run length code into blocks each having a predetermined number of bits.
The present invention relates to a variable length block encoding circuit that performs block encoding using concatenated blocks. (Problems with the Prior Art) Conventionally, as a means of encoding digital facsimile image signals and compressing the band, it has been used to make a set of multiple scanning lines, for example, two scanning lines, and to make sure that the corresponding bits are consecutive and identical combinations. The run-length encoding method shown is widely used. A variable-length block coding method has already been proposed as such a run-length coding method. In the variable length block coding method, the run length is expressed in binary and divided into blocks of a fixed length, and a code word is formed from the required number of blocks. A simple example is to display the run length in natural binary and display the run length by 2 from the bottom.
Each bit is divided into blocks, a flag of "0" or "1" is added to the beginning or end of each block to indicate the division of the block, and one code word is constructed by treating all blocks in a connected state. However, conventional variable length block encoding circuits have had the disadvantage of having a complicated configuration. (Objective of the invention) An object of the invention is to provide a variable length block encoding circuit with a simple circuit configuration. (Embodiment of the invention) FIG. 1 is an explanatory diagram showing the configuration of a facsimile transmission circuit as an embodiment of the invention. In the figure, a facsimile original is scanned along scanning lines by a scanner 1, and is sequentially photoelectrically converted to create electrical signals, and a synchronization signal is added to each scanning line. When the run-length encoded start pulse A is input to the control circuit 6, the synchronization circuit 5 detects the start signal of the control circuit 6 and the synchronization signal from the scanner 1, and starts the sampling pulse control circuit 4. The sampling pulse control circuit 4 outputs the clock pulse from the clock generation circuit 10 to the sampling circuit 2 and the counting circuit 3 at the same time as the start. The sampling circuit 2 samples the electric signal of one scanning line of the original image from the scanner 1 using the clock pulse inputted from the sampling pulse control circuit 4, and stores it in the memory circuit ( ) 7 for one scanning line. The counting circuit 3 counts the sampling pulses, and when the sampling pulses for one scanning line are counted, the sampling pulse control circuit 4 and the synchronization circuit 5
Sends a sampling end signal to stop the sampling pulse. Further, this sampling end signal is input to the scanner 1 to shift the original by one line. The synchronization circuit 5 detects the synchronization signal from the scanner 1 again and starts the sampling pulse control circuit 4. The sampling pulse control circuit 4 sends the sampling pulse to the sampling circuit 2 and the counting circuit 3 as before, samples the next line, and stores it in the memory circuit ( ) 8 for one scanning line. When the counting circuit 3 counts the sampling pulses for one scanning line, it outputs a sampling end signal to the sampling pulse control circuit 4 and the synchronization circuit 5 to stop the sampling pulses. Further, the original on the scanner 1 is shifted by one line in response to this sampling end signal. When the sampling pulse control circuit 4 receives the sampling end signal for two lines, it sends a signal to the control circuit 6 to convert the start signal of the control circuit 6 into a stop signal, and ends the sampling.
The control circuit 6 operates the memory read clock control circuit 9 simultaneously with the completion of sampling. Memory read clock control circuit 9 sends the clock of clock generation circuit 10 to memory circuit ( ) 7 and memory circuit ( ) 8 in response to a signal from control circuit 6 . Two lines of sampled image information stored in the memory circuit ( ) 7 and memory circuit ( ) 8 are sent to the change point detection circuit 11 while the clock of the memory readout clock control circuit 9 is being generated. When a change occurs in the information on the two lines, the change point detection circuit 11 sends a change point detection signal to the memory read clock control circuit 9 and stops reading the memory circuits ( ) 7 and ( ) 8 . Further, the memory read clock generated by the memory read clock control circuit 9 is simultaneously sent to the run length encoding counter circuit 12 (input terminal 24 in FIG. 2), and the change point detection signal from the change point detection circuit 11 is inputted. Run-length encoding is performed by counting the memory read clocks up to (input 25 in FIG. 2). That is, the change point detection signal becomes a reset pulse for the run length encoding counter 12. The P/S conversion circuit 13 inputs in parallel the count state (run length code) when the run length encoding counter circuit 12 counts the memory read clock and the memory read clock stops due to the change point detection signal. . The run length encoding counter circuit 12 inputs the run length code to the P/S conversion circuit 13 in parallel and is then reset by the change point detection signal.
When a run-length code is input in parallel to the P/S conversion circuit 13, the run-length code is stored in the line buffer memory circuit 14. in this case,
Since this run-length code has a variable length in which a continuation designation flag is inserted every predetermined number of bits, the flag detection circuit 16 monitors the flag bits and sends the code to the P/S conversion circuit 13 in parallel until the code end flag is detected. The run length code inputted to the line buffer memory circuit 14 is serially stored in the line buffer memory circuit 14. The run-length code data stored in the line buffer memory circuit 14 is transmitted onto a line (not shown) at a predetermined transmission rate. The line buffer control circuit 15 controls the data amount of the run-length code stored in the line buffer memory circuit 14 to be a constant amount (number of bits). That is, if the accumulated amount of run-length codes is small, a control signal to start encoding is output to the control circuit 6. Furthermore, when the run length code stored in the line buffer memory circuit 14 matches the reference bit, the line buffer control circuit 15 outputs a control signal to the control circuit 6 to stop encoding. On the other hand, the memory read counting circuit 17 counts the memory read clock issued from the memory read clock control circuit 9. Thereby, the amount of sampling signals read out from each memory circuit 7, 8 is monitored, and a detection signal indicating whether all the sampling signals in each memory circuit 7, 8 have been read out is supplied to control circuit 6. Thus, the control circuit 6 controls the memory read clock control circuit 9 in response to the encoding start signal from the line buffer control circuit 15 on the condition that there is no memory read end detection signal from the counting circuit 17.
make it work again. As a result, the memory read clock is supplied to each memory circuit ( ) 7, ( ) 8, and reading and encoding of the sampling signal is restarted. This encoding operation is continued until a change occurs in the information between two lines by the change point detection circuit 11 as described above. Similarly, every time a change point occurs between two lines, reading of the memory circuits 7 and 8 is stopped → encoding → storage in the line buffer memory circuit 14 → according to the amount of encoded data in the line buffer memory circuit 14. Memory reading is then restarted repeatedly. When the memory read counting circuit 17 counts the end of memory reading, it sends a memory read end signal to the control circuit 6. The control circuit 6 starts the synchronization circuit 5 in response to this memory read end signal. Synchronous circuit 5
When starts, as described above, two lines of information obtained by sampling the original image are stored in the memory circuit () 7 and memory circuit () 8, and the line buffer memory circuit 14 is stored until the run-length encoding start pulse A stops. A run-length code is output from. FIG. 2 is a detailed explanatory diagram of a run-length encoding counter circuit, which is a main part of the embodiment of FIG. 1, and FIG. 3 is an explanatory diagram of its operation. In Figure 2,
For example, flip-flops 21 ₁ to 21 ₁₀ consisting of bistable multivibrators are shift registers, FFs 21 ₁ to 21 ₄ including 21 ₁ are block a,
₂₁₅ to ₂₁₇ are the b block, ₂₁₈ to ₂₁₁₀ are the c block, and the first part of each block is
A constant voltage (+5V) is supplied to the FF stage, and the memory read clock pulse output from the memory read clock control circuit 9 shown in FIG.
The change point detection signal output from the change point detection circuit 11 shown in the figure is used as a reset signal for the FFs 21 ₁ to 21 of each stage.
_Signs A and B are extracted from the Q outputs of _FF212 and ₂₁₃ , and each output of _FF212 and ₂₁₃ is used as one input of _FF214 via a NOR gate circuit ₂₂₁ , and the control input terminal 25 FF21 as the other input of _FF214 through inverter 23
Extract flag C from the output of ₄ . Next level FF2
The control inputs of _FF21 to ₂₁₇ are supplied with the Q output of _FF213 and the Q output of _FF214 as a reset input, and the control input of FF217 is supplied with the Q output of _FF214 .
Each output of ₅ and 21 ₆ is connected to a NOR gate circuit 22 ₂
The output through the inverter 23 and the branch output of the inverter 23 are given, and from the Q outputs of _FF215 and ₂₁₆ , the code D,
E, and flag F is extracted from the output of _FF217 . Similarly, codes G, H and flag J are taken out by a combination of FFs 21 ₈ to 21 ₁₀ , NOR gate circuit 22 ₃ , and inverter 23 . To explain the operation of such a circuit configuration, first, when the change point detection signal applied to the control input terminal 25 becomes low level, the FF
₂₁₁ to _FF214 are reset. As a result, the Q output of _FF214 becomes low level, so _FF215 to _FF217 are reset. Subsequent blocks are reset in the same way, and are marked A,
B, D, E, G, and H become “0”, and flags C,
F and J become "1" and are in the initial state. After that, the change point detection signal becomes high level and the reset is canceled, and then the code corresponding to the memory read clock pulse CL is counted as follows. Memory read clock pulse CL
Then, the output of shift register FF21 ₁ for this is shifted by one stage, and the Q output of FF21 ₂ becomes sign A.
The symbols A and B of block a and the flag C represent variable run lengths 1 to 4. shift register
The reason why _FF211 is provided is to encode the "1" state of the run length code as "001".
"1" of flag C indicates that the variable run length ends in the range of 1 to 4, and when it is "0", the run length continues to codes D, E and flag F of the next block b. It will show 9. The state of this encoding is shown in Table 1, and further 10~
2nd for increased run length up to 5460
Shown in the table.

【table】

【table】

[Table] Figure 3 shows the operating waveforms of the circuit in Figure 2, especially the first waveform.
Table, codes A, B, D, E, G, H, etc. that constitute the run length codes in Table 2, and flags C,
Time charts of F, J, etc. are shown. In other words, the FF 21 is obtained by shifting the output of the shift register ₂₁₁ by one stage in response to the clock pulse CL of the control input terminal 24.
The waveform of the Q output of _{No. 2} with symbol A and the waveforms of symbols B, D, and E of each stage with this as a reference are shown. Furthermore, block a or b is terminated or continued, and the run length code is changed to 1 as shown in Tables 1 and 2.
The flags that make up the section are shown. In this example, the flag is added at the end of each unit block, but it may be added at the beginning. As explained above, according to the present invention, a flag of "1" or "0" is added to the beginning or end of a unit block of a run-length code to indicate the end or continuation of the unit block, and the flag is set to a variable length. By configuring a part of the run-length code, the configuration can be simplified and the band compression efficiency can be increased. In the embodiment, the circuit configuration shown in FIG. 2 and the code structure shown in Table 1 are shown, but in addition to this code structure, codes adapted to the present invention can be created by changing the combination of the encoding circuits shown in FIG. It is possible to realize an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the configuration of a facsimile transmission circuit as an embodiment of the present invention, FIG. 2 is a detailed explanatory diagram of a run-length encoding counter, which is the main part of the embodiment of FIG. This is an operation explanatory diagram, in which 1 is a scanner, 2 is a sampling circuit, 3 is a counting circuit, 4 is a sampling pulse control circuit, 5 is a synchronization circuit, 6 is a control circuit, and 7 is a one-scanning line memory circuit ( ), 8 is one scanning line memory circuit (), 9
10 is a memory read clock control circuit, 10 is a clock generation circuit, 11 is a change point detection circuit, 12 is a run length encoding counter circuit, 13 is a P/S conversion circuit, 14 is a line buffer memory circuit, and 15 is a line buffer control circuit. , 14 is a flag detection circuit, 17 is a memory read counting circuit, 21 ₁ to 21
₁₀ , 21 _o are flip-flops, 22 ₁ to 22 ₃
is a NOR circuit, 23 is an inverter, and 24 and 25 are control input terminals.

Claims (1)

[Claims for Utility Model Registration] Accumulating means for temporarily accumulating at least one line of image signals obtained from the scanning means, and detecting mutual level change points between white and black in the image signals read from the accumulating means. A facsimile device having a detection means, which counts the length of consecutive image signals of the same level based on the detection output of the detection means, and outputs a binary code having a length corresponding to the counted value. Occasionally,
A variable-length block encoding circuit that divides a block into blocks each consisting of a predetermined number of bits each time the block exceeds a predetermined number of bits and outputs the divided blocks includes a number of serially connected flip-flops equal to the number of bits constituting the block; The flip-flop includes gate means for detecting that the code state of the flip-flop corresponds to the end or continuation of the block, and a flip-flop that sets a flag indicating the end or continuation of the block in response to the output of the gate means. A plurality of counting stages are provided corresponding to the blocks to be divided, and when the level of the image signal changes, a plurality of counting stages of a length determined according to the block position where the end flag from each counting stage is inserted is provided. A variable length block encoding circuit characterized in that it outputs a code consisting of blocks.