JPH04206797A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04206797A
JPH04206797A JP33743390A JP33743390A JPH04206797A JP H04206797 A JPH04206797 A JP H04206797A JP 33743390 A JP33743390 A JP 33743390A JP 33743390 A JP33743390 A JP 33743390A JP H04206797 A JPH04206797 A JP H04206797A
Authority
JP
Japan
Prior art keywords
package
mounting
mounting board
semiconductor device
recessed part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33743390A
Other languages
Japanese (ja)
Inventor
Takahiro Komatsu
隆宏 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP33743390A priority Critical patent/JPH04206797A/en
Publication of JPH04206797A publication Critical patent/JPH04206797A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve mounting accuracy of a package while reducing mounting volume by providing a mounting substrate with a recessed part or a through hole, into which a package can be trapped. CONSTITUTION:A recessed part 6 having about the same size as a package is made in a package mounting position 3. Then, positioning of mounting the package 4 on a mounting substrate 1 is automatically fixed by the recessed part 6 on the mounting substrate 1, and the mounting height of the package 4 is suppressed by a portion trapped by the recessed part 6 of the mounting substrate 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置に関し、特に面実装基板に半導体
装置を実装する場合の実装基板の構造を提供するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly provides a mounting board structure for mounting a semiconductor device on a surface mounting board.

〔従来の技術〕[Conventional technology]

第7図は従来の半導体装置の実装基板の平面図、第8図
は第7図の実装基板にパッケージを実装した状態を示す
断面図である。
FIG. 7 is a plan view of a conventional mounting board for a semiconductor device, and FIG. 8 is a sectional view showing a state in which a package is mounted on the mounting board of FIG.

図において、(1)は実装基板、(2)は実装基板(1
)のリード部コンタクト、(3)はパッケージ実装位置
、(4)はパッケージ、(5)はパッケージ(4)のリ
ードである。
In the figure, (1) is the mounting board, (2) is the mounting board (1
) is the lead part contact, (3) is the package mounting position, (4) is the package, and (5) is the lead of the package (4).

第8図に示すように例えば外部リード(5)か水平に出
ているパッケージ(4)を実装する場合、パッケージ(
5)のリード(5)部がパッケージ(4)の底面とほぼ
同一高さとなっているため、リード(5)部を実装基板
(1)上のコンタクト(2)部に接続する場合、その位
置決めには高い精度か必要とされる。また、パッケージ
(4)を実装基板(1)に実装した場合の実装高さは、
パッケージ(4)の厚み分だけ必要となり、例えば複数
枚の実装基板を使用し、モジュールとした場合、そのモ
ジュールの体積は大きくなってしまう。
For example, when mounting a package (4) with external leads (5) protruding horizontally as shown in FIG.
Since the lead (5) part of 5) is almost at the same height as the bottom of the package (4), when connecting the lead (5) part to the contact (2) part on the mounting board (1), it is difficult to determine its position. requires high precision. Also, the mounting height when the package (4) is mounted on the mounting board (1) is:
The thickness of the package (4) is required. For example, if a plurality of mounting boards are used to form a module, the volume of the module will become large.

〔発明か解決しようとする課題〕[Invention or problem to be solved]

従来の半導体装置は以上のように構成されていたので、
実装基板が平面として形成されているため、パッケージ
の実装に際して位置決め精度が高く要求され、また、こ
の実装基板を用いてモジュール化する場合、その体積が
大きくなるなとの問題点があった。
Since conventional semiconductor devices were configured as described above,
Since the mounting board is formed as a flat surface, high positioning accuracy is required when mounting the package, and when this mounting board is used to create a module, there is a problem in that the volume becomes large.

この発明は上記のような問題点を解消するためになされ
たもので、パッケージの実装を高精度にするとともに、
実装体積も小さくてきる半導体装置を得ることを目的と
する。
This invention was made to solve the above-mentioned problems, and in addition to making the packaging of the package highly accurate,
The object is to obtain a semiconductor device whose packaging volume can be reduced.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、半導体装置の実装基板上
のパッケージ実装面に、実装するパ・yケージとほぼ同
し大きさの凹部又はスルーホールを設けたものである。
In the semiconductor device according to the present invention, a recess or a through hole approximately the same size as the package to be mounted is provided on the package mounting surface of the semiconductor device mounting board.

〔作用〕[Effect]

だの発明における実装基板は、パッケージを実装基板に
実装する場合、その位置決めは実装基板上の凹部にパッ
ケージを設置することにより高精度を保つことかてき、
また、凹部にパッケージを設置しているためパッケージ
の実装高さは従来のものより低(なり、複数の実装基板
によりモジュールを構成する場合、その体積を小さくす
ることができる。
In the mounting board according to Dan's invention, when the package is mounted on the mounting board, the positioning can be maintained with high precision by installing the package in a recess on the mounting board.
In addition, since the package is installed in the recess, the mounting height of the package is lower than that of conventional products, and when a module is configured with a plurality of mounting boards, its volume can be reduced.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において、(1)は実装基板、(2)はパンケージを
実装する場合のリート部コンタクト、(6)はパッケー
ジ実装位置(3)に設けられたパッケージとほぼ同じ大
きさの凹部加工部分である。第2図は第1図の■−■線
における断面図、第3図は第1図の実装基板(1)にパ
ッケージを実装した場合の折面図である。図において、
(4)はパッケージ、(5)はパッケージ(4)のリー
トである。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is the mounting board, (2) is the reed contact when mounting the pan cage, and (6) is the recessed part that is approximately the same size as the package provided at the package mounting position (3). . 2 is a cross-sectional view taken along the line ■--■ in FIG. 1, and FIG. 3 is a cross-sectional view when the package is mounted on the mounting board (1) of FIG. 1. In the figure,
(4) is a package, and (5) is a REIT of package (4).

次に動作について説明する。第3図に示すようにパッケ
ージ(4)の実装基板+1)への実装の位置決めは、実
装基板(1)上の凹部(6)によって自動的に決まって
いるため、あらためて位置決めをする必要かなくなる。
Next, the operation will be explained. As shown in Figure 3, the mounting position of the package (4) on the mounting board +1) is automatically determined by the recess (6) on the mounting board (1), so there is no need to reposition it. .

また、第3図に示されるようにパッケージ(4)の実装
高さは実装基板(1)上の凹部(6)に落とし込まれた
分だけ低く抑えられることとなる。さらに、パッケージ
(4)のリード(5)の加工の面からは、あらためて外
部リード(5)の曲げ加工の必要かなくなるため、パッ
ケージアセンブリのスルーブツトの向上も可能である。
Further, as shown in FIG. 3, the mounting height of the package (4) can be reduced by the amount that the package (4) is dropped into the recess (6) on the mounting board (1). Furthermore, in terms of processing the leads (5) of the package (4), there is no need to bend the external leads (5) again, so it is possible to improve the throughput of the package assembly.

第4図第5図は、この発明の他の実施例であるパッケー
ジの実装状態を示す断面図である。
FIG. 4 and FIG. 5 are cross-sectional views showing the mounting state of a package according to another embodiment of the present invention.

第4図第5図はこの発明の他の実施例であるパッケージ
の実装状態を示す断面図である。
4 and 5 are cross-sectional views showing the mounting state of a package according to another embodiment of the present invention.

なお、上記実施例では実装基板(1)上に凹部(6)を
設けた場合を示したが、これらの他の実施例ではスルー
ホール(7)を設けるようにしたもので、第4図は第3
図の凹部(6)の底部をスルーホール(7)によって貫
通する構造となっている。また、第5図は第4図のスル
ーホール(7)の両面にパッケージ(4)を取付けた場
合で、極めて実装体積を縮小できる。
In addition, although the above embodiment shows the case where a recess (6) is provided on the mounting board (1), in these other embodiments, a through hole (7) is provided, and FIG. Third
The structure is such that a through hole (7) penetrates the bottom of the recess (6) shown in the figure. Further, FIG. 5 shows a case where the package (4) is attached to both sides of the through hole (7) shown in FIG. 4, and the mounting volume can be extremely reduced.

この構造を採用することにより、第3図の実施例の効果
の他に、パッケージの冷却効率の向上という効果も得ら
れる。
By adopting this structure, in addition to the effect of the embodiment shown in FIG. 3, it is also possible to obtain the effect of improving the cooling efficiency of the package.

第6図は第3図の凹部(6)を実装基板(1)の両面に
設け、パッケージ(4)を実装基板(1)の両面に実装
したもので、実装体積を縮小している。
In FIG. 6, the recesses (6) shown in FIG. 3 are provided on both sides of the mounting board (1), and the package (4) is mounted on both sides of the mounting board (1), thereby reducing the mounting volume.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、実装基板にパッケージ
か落し込める凹部又はスルーホールを設けたので、パッ
ケージの実装精度が向上できるとともに、実装体積を縮
小できるという効果がある。
As described above, according to the present invention, since the mounting board is provided with a recess or a through hole into which the package can be dropped, it is possible to improve the mounting accuracy of the package and reduce the mounting volume.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例である実装基板の平面図、
第2図は第1図の■−■線における断面図、第3図は第
2図にパッケージを実装した場合の断面図、第4図〜第
6図はこの発明の他の実施例を示す断面図、第7図は従
来の実装基板の平面図、第8図は第7図の■−■線にお
ける断面図である。 図において、(1)は実装基板、(2)はコンタクト、
(3)はパッケージ実装位置、(4)はパッケージ、(
5)はリード、(6)は凹部、(7)はスルーホールを
示す。 なお、図中、同一符号は同一、または相当部分を示す。
FIG. 1 is a plan view of a mounting board which is an embodiment of the present invention.
Fig. 2 is a sectional view taken along the line ■-■ in Fig. 1, Fig. 3 is a sectional view when the package shown in Fig. 2 is mounted, and Figs. 4 to 6 show other embodiments of the present invention. 7 is a plan view of a conventional mounting board, and FIG. 8 is a sectional view taken along the line ■--■ in FIG. 7. In the figure, (1) is the mounting board, (2) is the contact,
(3) is the package mounting position, (4) is the package, (
5) is a lead, (6) is a recess, and (7) is a through hole. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  半導体素子を封止したパッケージを実装する実装基板
に、前記実装基板上に前記パッケージが落とし込める凹
部又はスルーホールを設けたことを特徴とする半導体装
置。
1. A semiconductor device, wherein a mounting board on which a package in which a semiconductor element is sealed is mounted is provided with a recess or a through hole into which the package can be dropped.
JP33743390A 1990-11-30 1990-11-30 Semiconductor device Pending JPH04206797A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33743390A JPH04206797A (en) 1990-11-30 1990-11-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33743390A JPH04206797A (en) 1990-11-30 1990-11-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04206797A true JPH04206797A (en) 1992-07-28

Family

ID=18308586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33743390A Pending JPH04206797A (en) 1990-11-30 1990-11-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04206797A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631807A (en) * 1995-01-20 1997-05-20 Minnesota Mining And Manufacturing Company Electronic circuit structure with aperture suspended component
WO2000014788A2 (en) * 1998-09-09 2000-03-16 Telefonaktiebolaget Lm Ericsson An electronic arrangement comprising a component carrier, a carrier for an electronic component, and a method of producing an electronic arrangement

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631807A (en) * 1995-01-20 1997-05-20 Minnesota Mining And Manufacturing Company Electronic circuit structure with aperture suspended component
US5689600A (en) * 1995-01-20 1997-11-18 Minnesota Mining And Manufacturing Company Electronic circuit structure
WO2000014788A2 (en) * 1998-09-09 2000-03-16 Telefonaktiebolaget Lm Ericsson An electronic arrangement comprising a component carrier, a carrier for an electronic component, and a method of producing an electronic arrangement
WO2000014788A3 (en) * 1998-09-09 2000-07-20 Ericsson Telefon Ab L M An electronic arrangement comprising a component carrier, a carrier for an electronic component, and a method of producing an electronic arrangement

Similar Documents

Publication Publication Date Title
US8035987B2 (en) Electronic device having a groove partitioning functional and mounting parts from each other
US7629660B2 (en) Semiconductor sensor component including a sensor chip and methods for the manufacturing thereof
JPH04206797A (en) Semiconductor device
JPH0217430Y2 (en)
JPS63296252A (en) Resin sealed semiconductor device
US7449770B2 (en) Substrate with slot
US5157587A (en) Sealing arrangement
JP2000049271A (en) Semiconductor device
JP2906635B2 (en) Hybrid integrated circuit device
JPH10209207A (en) Method for mounting chip
JPH09184850A (en) Method for mounting semiconductor acceleration sensor on substrate
JPH0536296Y2 (en)
JPH0697355A (en) Stacked electronic component
JPH0521902Y2 (en)
JPH02253646A (en) Lead frame
JPH04201880A (en) Embossed type carrier tape
JPH0471288A (en) Semiconductor packaging substrate
JPH036029Y2 (en)
JP2024078985A (en) Semiconductor Device
JPS63248155A (en) Semiconductor device
JPH0287654A (en) Surface mounting semiconductor device
JPH03211861A (en) Package for plastic molded semiconductor
JP2000133911A (en) Electronic component mounting device
JPS61222724A (en) Bonding of member
JPS63241954A (en) Resin-sealed semiconductor device