JPH04205794A - Data delay circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit having a large delay amount at a low cost by supplying the addresses of different initial values for each input cycle of input data to the memory of the required delay amount of the input data, holding them, and reading out for the specified numbers of time. CONSTITUTION:The input data are applied to an I/O terminal of the memory 11 holding the data to be delayed through a buffer 14. The address is applied to a terminal A of the memory 11 from an address counter 12. To this counter 12, the data outputted from an adding device 13 for each input cycle of the input data are loaded as the initial value. Then, in the case N pieces of data are held, the access to the memory 11 is executed once for a writing access for each input cycle of the input data and N-1 times for a reading access. Thus, the circuit can be constituted at a low cost even in the case the delay amount is large.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a data delay circuit, and more particularly to a circuit with a large amount of delay.

<Prior Art> FIG. 5 shows a conventional example of a data delay circuit. In the figure,
1 to N are registers, Q terminals and D terminals of adjacent registers are sequentially connected, and a clock is commonly input to each clock terminal.

Input data is sequentially moved from register N to register N in synchronization with the clock, and the input data after N clocks is output from register N as output data.

<Problems to be Solved by the Invention> However, the above-mentioned circuit is simple when the value of N is small.
If the value is N or several hundred, it becomes virtually impossible to realize the value of several [-].

The present invention has been made in view of these points, and an object of the present invention is to provide a data delay circuit that can be constructed at low cost even if the circuit has a large amount of delay.

Means for Solving the Problems> The present invention for solving the above problems comprises: a memory having a capacity to hold input data for a required amount of delay; an address counter that generates an address to be added to the memory; The present invention is characterized by comprising an initial value generating means for giving a different initial value to the counter for each input cycle of input data, and a register for holding data read from the memory.

<Operation> For each input cycle of input data to a memory holding N pieces of data, a write access is performed once and a read access is performed N-1 times.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a data delay circuit according to the present invention. In the figure, 11 is a memory that holds data to be delayed, 12 is an address counter that generates a memory address that can be loaded with an initial value, and the Q terminal is connected to the A terminal of the memory 11 and the A of the adder 13. connected to the terminal. Adder 13 is address counter 12
'2' is added as data to the output of B
2" is applied to the terminal, and the f terminal is connected to the DI terminal of the address counter 12. 14 is an input data buffer, which is connected to the I10 terminal of the memory 10. The D terminal of the register 15 is also connected to the I10 terminal of the register 15.

The Q terminal of register] 5 is connected to the D terminal of register 16. ]7 is a control circuit which applies a write enable signal to the WE terminal of the memory 11, applies a load signal to the LD terminal of the address counter 12, and outputs a clock signal to the clock terminals of the address counter 12 and each register]5 and 16. and sends an output control signal to the buffer 14.

In such a configuration, input data is applied to the I10 terminal of memory 11 via buffer 14. memory 1
An address is added to the A terminal of 1 from the address counter 12. The address counter 12 is loaded with data outputted from the adder 13 as an initial value every input cycle of input data. For example, in the case of holding four pieces of data, the number of accesses to the memory 11 during one input cycle period is three read cycles and one write cycle, a total of four times.

FIG. 2 is a timing chart explaining the operation of FIG. 1. In the figure, (a) represents the clock of input data in (b). (C) is a clock given to the address counter 12, and (d) represents the output of the address counter 12, that is, the memory address. (e
) represents the counter load signal Ij received by the address counter 12. (f) is address counter 1
2 represents the output of the adder 13 loaded as an initial value, and (g) represents the memory write enable signal. (h) represents memory read data. (i)
represents the output enable signal of buffer]4. (
j) represents a clock for latching into the register 15, (10 represents the output of the register 15, and (1) represents the output of the register 16.

As a result, the number of accesses to the memory that holds the input data to be delayed is, for example, four times in total when holding four pieces of data, making high-speed processing possible.

FIG. 3 is a circuit diagram of another embodiment of the present invention, in which the same parts as in FIG. 1 are designated by the same numbers.

The difference between the circuit of FIG. 3 and the circuit of FIG. 1 is that a counter 18 is used as an initial value generating means for supplying an initial value to the address counter 12.

FIG. 4 is a timing chart explaining the operation of FIG. 3. In the figure, (a) to (e) are the same as in FIG. 2. (f) represents the output of the counter 18. The counter 18 is incremented according to the same clock as the input clock in (a), and the count data is given to the address counter 2 as an initial value. In addition, the fourth
In the figure, the steps after (g) in FIG. 3 are omitted because they are the same.

<Effects of the Invention> As described in detail above, according to the present invention, the following effects can be obtained.

Uses cheap memory to hold data that should be delayed. Therefore, especially when the amount of delay is large, a data delay circuit can be constructed at low cost. And access to memory is
When holding N pieces of data, the number of write accesses for each cycle of input data is 1, and the number of read accesses is 111 times.

It is possible to improve processing speed.

The data delay circuit is useful when performing moving average calculations and the like in digital signal processing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the data delay circuit according to the present invention, FIG. 2 is a timing chart explaining the operation of FIG. 1, and FIG. 3 is another embodiment of the data delay circuit according to the present invention. 4 is a timing chart explaining the operation of FIG. 3, and FIG. 5 is a conventional example of a data delay circuit. 11...Memory 12...Address counter 13...Adder 1.4・Buffer 15.16・
・Register] 7... Control circuit] 8... Counter (initial value generation)

Claims (1)

[Scope of Claims] A memory having a capacity to hold input data for a required delay amount, an address counter that generates an address to be given to the memory, and an initial value that is different for each input cycle of the input data in the address counter. 1. A data delay circuit comprising: initial value generation means for giving a value of 0.0, and a register for holding data read from the memory.