JPH04205675A - Picture element density conversion device - Google Patents

Abstract

PURPOSE:To obviate the generation of a deviation in the phase of dither patterns in the boundary part of an original image and the convered image overwritten thereon by determining and outputting the dither threshold reading out address of a memory in which the dither threshold is stored from the addresses for writing the convered picture elements to an image memory. CONSTITUTION:This device is constituted of an Src address generating circuit 1, a Dst address generating circuit 2, a multiplex selector (MUX) 3, the image memory 4, and a picture element density conversion circuit 5. One piece of the element of a dither matrix, i.e., dither threshold, is intrinsically allotted to the respective addresses of the image memory 4 and the adequate dither threshold is selected in correspondence to the addresses where the conversion picture elements are written. This threshold is used for reditherization. The generation of the deviation in the phase of the dither patterns at the boundary part of the original image and the conversion image overwritten thereon is obviated and the dither image processing with high image quality is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a pixel density conversion device that performs pixel density conversion of a dithered image with high image quality.

(Prior art) Conventionally, as a method for performing pixel density conversion in a dithered image with high image quality, each pixel constituting the converted image, that is, the position in the original image corresponding to the converted pixel, is determined, and the local There is a method in which the density is measured r times and re-dither processing is performed based on the predicted value. By using this method, it is possible to preserve the gradation of the original image and prevent the occurrence of moiré.

However, when this method is used, the following problems occur. Now, for example, an image that has been expressed with pseudo gradation using an 8x8 dither matrix will be converted to 8 pixels horizontally and 4 pixels vertically at the same size.
Consider the process of copying even pixels. Also,
It is assumed that the density value of this image is uniformly "32". If the dither threshold settings are as shown in Figure 9 (A), the dither pattern that represents this image is as shown in Figure 9 (B).
become that way. In the conventional technology, the converted pixels are determined by re-dithering without using the address information of the image memory where the converted image is written. If the reference is started from the threshold set at a certain position in the dither matrix, for example, if reference is made from the threshold at the upper left corner of the dither matrix, the processing result will be as shown in Figure 10 (
A). Looking at FIG. 10A, it can be seen that a phase shift of the dither pattern occurs at the boundary between the original image and the converted image overwritten thereon, and a boundary line appears. However, the boundary line should not originally appear as shown in FIG. 10(B), and it can be said that the result of FIG. 10(A) clearly causes a deterioration in image quality.

(Problem to be Solved by the Invention) As described above, conventionally, when obtaining converted pixels by re-dithering, this is done without using the address information of the image memory where the converted image is written. Reference is always started from a threshold value set at a fixed position in the dither matrix, regardless of the address. As a result, there is a problem in that a phase shift of the dither pattern occurs at the boundary between the original image and the converted image overwritten thereon, and a boundary line appears, resulting in a reduction in image quality.

Therefore, the present invention eliminates the phase shift of the dither pattern at the boundary when writing the converted image obtained by performing pixel density conversion on the original image expressed by dithering and then performing re-dither processing. It is an object of the present invention to provide a pixel density conversion device that can obtain processing results of higher image quality.

[Structure of the Invention (Means for Solving the Problems)] The pixel density conversion device of the present invention, when performing pixel density conversion on a dithered image, calculates the In a pixel density conversion device that calculates a converted pixel value by re-dithering using a local density predetermined value ΔIIL and a comparison result between the predetermined value and a dither threshold value, , address generation means for determining and outputting a dither threshold read address of a memory in which the dither threshold is stored.

(Function) 1 of the dither matrix for each address of the image memory.
elements, i.e. dither thresholds are uniquely assigned,
By selecting an appropriate dither threshold 1 in accordance with the address to which the converted pixel is written and using it for re-dithering, there is no phase shift in the dither pattern at the boundary between the original image and the converted image written over it. , high-quality dither image processing is possible.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

-5= FIG. 1 shows the overall configuration of a pixel density conversion device according to the present invention. That is, this pixel density conversion device is composed of an Src address generation circuit, a Dst address generation circuit 2, a multiplex selector (MUX) 3, an image memory 4, and a pixel density conversion circuit 5. ing.

The Src address generation circuit 1 calculates the position in the original image corresponding to each converted pixel in the image after pixel density conversion (hereinafter referred to as converted pixel position), and calculates the address corresponding to that position (hereinafter referred to as Src address). ) is output. The Dst address generation circuit 2 generates a memory address (hereinafter referred to as Dst address) that stores the converted pixel.
occurs. In addition, below, Src address, Dst
Addresses and dither threshold read addresses to be described later will all be explained as two-dimensional addresses consisting of an X-direction component and a y-direction component.

The pixel density conversion circuit 5 is composed of a density r side cover 6, an internal RAM 7 storing a dither threshold value, a re-dither section 8, and an internal address generation circuit 9.

The density predictor 6 predicts the local density at the converted pixel position based on the Src address of the image memory 4 and the referenced original pixel group read from the surrounding area. The internal address generation circuit 9 generates a dither threshold read address from the internal RAM 7, and has the same circuit configuration as the Dst address generation circuit 2. A comparator is used in the re-dithering unit 8, which compares the read dither threshold value with the predicted density value output from the density predictor 6, and as a result of the comparison, outputs a converted pixel value as follows. do.

When density pre-7Ill value>threshold value, converted pixel value = “1”
When the predicted density value≦threshold value, the converted pixel value−rOJ converted pixel is written to the Dst address of the image memory 4.

Next, each component in FIG. 1 will be explained in detail.

FIG. 2 shows the Dst address generation circuit 2. As shown in FIG. Further, FIG. 3 shows a schematic diagram of scanning when a converted image is written into the image memory 4. Note that xini is the initial value of the X address, Δxm is the X component of the address step in the main scanning direction, and ΔXS is the X component of the address step in the sub-scanning direction.

FIG. 2(A) shows the X-direction address projection section.

That is, the adder 10 adds Δxm to the current address X, and the flip-flop]] latches the output of the adder]0 every time the converted pixel is updated by the pixel update clock.

The selector 12 selects the main scanning start address xmi only at the start of the main scanning based on the main scanning start status signal.
At other times, the latch output of the flip-flop 11 is selected and output as the updated address X. The adder 13 adds ΔXS to the current main scanning start address xmi, and the flip-flop 14 latches the output of the adder 13 every time the main scanning line is updated using the line update clock. The selector 15 selects the address initial value xini only at the start of sub-scanning in response to the sub-scanning start status signal, and thereafter selects the latch output of the flip-flop 14.

FIG. 2(B) shows a y-direction address calculation section.

That is, the adder 16 adds Δym to the current address y, and the flip-flop 17 latches the output of the adder 6 every time the converted pixel is updated using the pixel update clock.

The selector 18 selects the main scanning start address ymi only at the start of the main scanning based on the main scanning start status signal.
At other times, the launch output of the flip-flop 17 is selected and output as the updated address y. The adder 19 adds Δys to the current main scanning start address ymi, and the flip-flop 20 latches the output of the adder 19 every time the main scanning line is updated using the line update clock. The selector 21 selects the initial address value yini only at the start of sub-scanning in response to the sub-scanning start status signal, and thereafter selects the latch output of the flip-flop 20.

Next, each component of the pixel density conversion circuit 5 will be explained.

The internal address generation circuit 9 has the same circuit configuration as the Dst address generation circuit 2 shown in FIG. 2, and uses the initial value of the Dst address and the address step to generate the 3 bits of the A 216-bit address consisting of 3 bits is generated as a direct read address. However, the internal address generation circuit 9 has a dither matrix whose number of rows and columns is 2" and 2", respectively.
In this case, any address that can generate an address with an information amount of m bits or more in the y direction, n bits or more in the x direction, and a total of (m+n) or more in correspondence with the Dst address may be used.

FIG. 4 shows the configuration of the internal RAM 7 that stores dither threshold values. This internal RAM7 is 2'''X2
When using a dither matrix of n, it takes the configuration of (m+n) bits/word X 2 L m"0" word.

In this embodiment, as shown in FIG. 4(A), the internal RAM 7
inputs the 6-bit address generated by the internal address generation circuit 9 and outputs the dither threshold value stored in that address. The structure of the internal RAM 7 is 6 bits/word×64 words as shown in FIG. 4(B).

FIG. 5 shows the configuration of the concentration predeterminer 11111 6. As shown in FIG. In the density prediction by the density predictor 6, the number of black pixels in an area surrounded by the same 8×8 aperture as the dither matrix with the converted pixel position as the center is counted, and this value is used as a predicted value. FIG. 6 shows the density prediction at this time. FIG. 5(A) shows an example of the configuration of the density predictor 6. Assuming that the value representing a black pixel is "1", one stage [
The I decoders 30 to 37 are logic circuits that output the number of "]" in the input 8 bits. The outputs of the decoders 30 to 37 are sent to the adders 40 to 46 in the second stage 1'' and beyond.
In the end, a count value of "1" in the 64-bit input data is output.

Or, as shown in FIG. 5(C), as the aperture moves,
A method may be used in which the value obtained by subtracting the number of black pixels among the eight pixels that enter the aperture from the number of black pixels among the eight pixels that exit the aperture is added sequentially as an increment.

The circuit configuration in this case is shown in FIG. 5(B), but the decoders 50, 5] are the same as in FIG. 5(A). The output from subtractor 53 is the increment, and the output from flip-flop 54 is the density predetermined 1111+value.

The clock to the flip-flop 54 is a clock generated as the aperture moves.

Next, the features of the present invention will be explained using specific examples.

In this embodiment, the dither matrix is 8×8, and the threshold value distribution uses the settings shown in FIG. 9(A). Also, the conversion rate is 1 (equal magnification).

Now, pixel density conversion is performed on the original image, which has a density value of "32" and is similar to -, and the converted image is shifted from the position of the original image by 8 pixels in the X direction and 4 pixels in the Y direction, as shown in Figure 8. Consider the case of overwriting. First, the position in the original image to which the conversion pixel to be currently sought corresponds is determined by the Src address generation circuit. In this case, assuming that the interval between the original pixels is "1", it is assumed that when the conversion rate is r, the converted pixels are distributed within the original image at an interval of 1/r.

Here, in the example shown here, since it is the same magnification, that is, r=1, the converted pixels are also distributed at intervals of "1" in the original image.

Next, the local density value at the converted pixel position is predicted using the density predictor 6 from the obtained Src address and the group of referenced original pixels around it. In this embodiment, since the original image has a uniform density of "32", according to this method, the predicted density value of the converted pixel also becomes "32".

Finally, the converted pixel value is obtained by re-dithering processing and written on the Dst address of the image memory 4. In the 11f dithering process, the image obtained changes depending on whether one threshold value in the dither matrix is compared with the measured density r value, and which threshold value is used at that time. In this embodiment, it is assumed that the image memory 4 is filled with dither matrices as shown in FIG. This is equivalent to assigning a day→no threshold value to Na for the address of the image memory 4. Furthermore, in this example, 8X
8, the dither threshold corresponding to the address [x, y] of the image memory 4 is the address in the dither matrix (
8). Here, (x % 8
) represents the remainder when X is divided by 8.

When calculating the first converted pixel value, the original image is at address [0
, 0], the converted image starts at address [
8, 4], the predicted density value "32" is the threshold read address (
8% 8, 4% g) = (0,4) compared to the threshold. According to FIG. 9(A), the threshold value at address (0,4) in the dither matrix is "38", so as a result of the comparison, "0" is written to [8,4] as the first converted pixel value. It will be done.

In this way, converted pixels are successively determined and written into the image memory 4, and finally the image shown in FIG. 10(B) is obtained.

As explained above, according to the second embodiment, the dither threshold value is selected corresponding to the address of the image memory and used for re-dither processing, so that the boundary between the original image and the converted image overwritten thereon is A high-quality dither image processing result can be obtained without causing any phase shift in the dither pattern.

[Effects of the Invention] As described in detail above, according to the present invention, after performing pixel density conversion on an original image expressed by dithering, it is possible to write a converted image obtained by performing re-dither processing. , it is possible to provide a pixel density conversion device that eliminates the phase shift of the dither pattern at the boundary and obtains processing results of higher image quality.

[Brief explanation of the drawing]

The figures are for explaining one embodiment of the present invention, and FIG. 1 is a block diagram schematically showing the overall configuration, FIG. 2 is a block diagram showing the configuration of the st address generation circuit, and FIG.
The figure is a schematic diagram of scanning when a converted image is written to the image memory, FIG. 4 is a diagram for explaining the configuration of the internal RAM, and FIG. 5 (A). (B) is a diagram showing an example of the configuration of a concentration predictor, FIG. 5(C) is a diagram for explaining the circuit configuration of FIG. 5(B'), and FIG. 6 is a diagram for explaining concentration prediction. Schematic diagram, Figure 7 is a diagram to explain the positional relationship between the converted image, original image and dither matrix, Figure 8 is a diagram to explain the positional relationship between the converted image and the original image, and Figure 9 is a diagram to explain the positional relationship between the converted image and the original image. FIG. 10 is a diagram for explaining the threshold value and is a diagram for explaining image quality deterioration due to phase shift of the dither pattern. 1... Src address generation circuit, 2... Dst address generation circuit, 3... Multiplex selector (M
UX), 4... Image memory, 5... Pixel density conversion circuit, 6... Density predictor, 7... Internal RAM, 8...
- Re-dither section, 9... Internal address generation circuit. Applicant's agent Takeshi Suzue r r-) ＼ °ε Yomiku 0-hem<punishment...0 Δ
ψ (A) 1st 'F [Heisei 4-1 (Dbl: J (Cuff (B))] Figure

Claims (2)

[Claims] (1) When performing pixel density conversion on a dithered image,
In a pixel density conversion device that calculates a converted pixel value by predicting the local density at a position in the original image corresponding to each pixel of the converted image and performing re-dithering using the result of comparing the predicted value with a dither threshold. . A pixel density conversion device comprising address generation means for determining and outputting a dither threshold read address of a memory in which a dither threshold is stored from a write address of a converted pixel to an image memory. (2) When the number of rows and columns of the dither matrix is 2^m and 2^n, respectively, the address generating means generates a total of (m+
Claim 1 characterized in that an address having an information amount of n) bits or more is determined from a converted pixel write address and output.
The pixel density conversion device described.