JPH07212593A - Method and device for processing picture - Google Patents

Abstract

PURPOSE:To obtain a method and a device for processing picture, whereby a circuit scale is made to be smaller, flexibility is held in a weighing coefficient and rounding difference is restricted to be less than one from zero so that picture quality in a high-light part in a difference diffusing method. CONSTITUTION:The value of binary difference which is multiplied by the denominator of the weighing coefficient is previously calculated so as to be stored in a table 8 and the total sum of the density of an input picture element which is obtained by multiplying the denominator of the weighing coefficient and difference distributed from the peripheral picture element is obtained by an adder 2. The difference between the total sum and a binarized result is divided by the denominator of the weighing coefficient so as to obtain a quatient and a remainder. The quotient is distributed to the peripheral picture element based on the value stored in the table and the remainder is also distributed to the peripheral picture element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus, and more particularly to quantizing input data into binary or multi-valued data while preserving the difference between input image density and output image density by an error diffusion method or the like. The present invention relates to an image processing method and apparatus for processing.

[0002]

2. Description of the Related Art Conventionally, an error diffusion method has been known as a pseudo halftone process for expressing input multi-valued data with binary or multi-valued levels lower than the level of the input multi-valued data. For this error diffusion method, see "An Adaptive Al".
gorithm for Spatial Gray
Scale ”in society for Info
rmation Display 1975 Symp
osium Digest of Technical
Papers, 1975, 36. In this method, the pixel of interest is P, the density of the pixel is v, and the densities of the unbinarized pixels P0, P1, P2, and P3 around the point P are binarized to v0, v1, v2, v3, respectively. Letting T be the threshold value of T, the binarization error E at the point of interest P is empirically obtained for the peripheral pixels P0, P1, P2, P3.
This is a method in which weighting processing is performed by 0, W1, W2, and W3 and distribution is performed to make the average density of the output image equal to the density of the input image in a macro manner. At this time, assuming that the output binary data is o, the errors E0, E1, E2, E3 with respect to the peripheral pixels P0, P1, P2, P3 can be obtained by the following formula.

[0003]

[Outer 1] (However, Vmax: maximum density, Vmin: minimum density) E0 = E × W0; E1 = E × W1; E2 = E × W2; E3 = E × W3; (Example of weighting factor: W0 = 7/16, W1 = 1/16, W
2 = 5/16, W3 = 3/16)

However, if this method is realized by a logic circuit, as will be understood from the above example, the multiplier and divider for each weighting factor are required, resulting in a large circuit scale and rounding error when performing integer arithmetic. (E- (E0 + E1 + E2 +
Due to E3)), the average density of the output image is not equal to the density of the input image.

As a method for solving this, Japanese Patent Laid-Open No. 58-58
No. 215169, JP-A No. 61-52073,
Japanese Patent Application Laid-Open No. 61-293068 discloses a method of reducing the circuit scale by using shift registers instead of multipliers and dividers by reducing the weighting coefficient to a power of two. JP-A-63-3507
In Japanese Patent Laid-Open No. 4 (1994), a weighted binarization error value is determined for each value of density information, and the sum of the binarization errors is made equal to the binarization error, thereby simplifying multiplication and division. , And a method of eliminating rounding error has been proposed.

Further, Japanese Patent Application Laid-Open No. 63-155950 proposes a method for making the average density of an output image equal to the density of an input image by adding a rounding error in weighted peripheral pixels. .

[0007]

However, the method using the shift register described above has a drawback in that the weighting factor is fixed to a power of 1 and the flexibility is poor. Further, in the method of determining the value of the binarization error weighted in advance and adding the rounding error in the error distributed to the weighted peripheral pixels so that the sum of the values becomes equal to the binarization error, The average density of is equal to the density of the input image, but since the integer calculation is performed, the value of the rounding error itself becomes 0 or at least 1 or more. Therefore, in the highlight part which is easily affected by the error, the image quality is distributed by the rounding error. Has the drawback that it deteriorates.

The present invention eliminates the above-mentioned drawbacks of the prior art, and improves the image quality especially in the highlight portion of an image by setting the value of the rounding error generated by weighting error data to less than 1. An object of the present invention is to provide an image processing method and apparatus capable of performing the above.

Another object of the present invention is to omit the multiplier and the divider for each weighting coefficient, to reduce the circuit scale, that is, to increase the flexibility of the weighting coefficient and to calculate the value of the rounding error itself. It is an object of the present invention to provide an image processing method and apparatus capable of improving the image quality by setting the value from 0 to less than 1.

[0010]

According to a first aspect of the present invention for achieving the above object, an input means for inputting image data, a processing means for quantizing the image data, and An error data generated at the time of the quantization processing is weighted, and a dispersion unit for distributing the error data to a plurality of image data is provided, and the distribution unit sets the value of the rounding error generated by the weighting to less than 1.

Further, according to the second aspect of the present invention, the error between the density of the input image and the density after binarization is distributed as a binarization error to the peripheral pixels of the pixel of interest, and after binarization. In the image processing method of making the average density equal to the density of the input image, a table in which a value obtained by multiplying the denominator of the weighting coefficient when allocating the error is calculated in advance is provided, and the density of the input pixel multiplied by the denominator of the weighting coefficient, The sum of the error distributed from the peripheral pixels is calculated, and the difference between the sum and the binarization result is divided by the denominator of the weighting coefficient to obtain the quotient and the remainder. The quotient is based on the values stored in the table. In addition to the distribution to the peripheral pixels, the surplus is also distributed to the peripheral pixels.

[0012]

According to the first aspect of the present invention, by setting the value of the rounding error generated by weighting the error data to be less than 1, it is possible to improve the image quality particularly in the highlight portion of the image.

According to the second aspect of the present invention, since the value of the binarization error obtained by multiplying the denominator of the weighting coefficient is calculated in advance and stored in the table, a multiplier and a divider for each weighting coefficient are used. It can be omitted, and the circuit scale can be reduced to enable high-speed processing. Furthermore, the sum of the density of the input pixel multiplied by the denominator of the weighting coefficient and the error distributed from the peripheral pixels is obtained, and the difference between the sum and the binarization result is divided by the denominator of the weighting coefficient to obtain the quotient and the remainder. The quotient and the quotient are distributed to the peripheral pixels based on the values stored in the table, and the remainder is also distributed to the peripheral pixels, so that the weighting coefficient can be made flexible and the value of the rounding error is 0 to 1. It is possible to improve the image quality including the highlight part.

[0014]

【Example】

[First Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining the arrangement of an image processing apparatus according to the first embodiment of the present invention.

In FIG. 1, 1 is a multiplier, and the multiplier 1
Multiplies the denominator value (256 in the case of the distribution coefficient of FIG. 3) of the distribution coefficient when the error is distributed to the 8-bit input data.
Reference numeral 2 denotes an adder, which adds the error data from the pixel which has already been binarized to the 16-bit data from the multiplier 1. Reference numeral 3 is a comparator, which corresponds to an intermediate level between the 17-bit data from the adder 2 and the 8-bit input data, "1".
27 ”multiplied by the value of the denominator of the distribution coefficient (“ 127 × 2
56 "). The 1-bit binary data from the comparator 3 is sent to an inkjet printer or laser beam printer (not shown), and an image is formed by turning dots on and off.

Reference numeral 4 denotes a subtractor, which calculates the difference between the 17-bit data from the adder 2 before binarization and the value after binarization, that is, error data. The binarized value used in the subtractor 4 is 2
When the binarization result is 1, it is “255 × 256”, and when the binarization result is 0, it is “0”.

A divider 5 divides the 16-bit data from the subtractor 4 by the value of the denominator of the distribution coefficient, and outputs a quotient 8-bit (signed) and a remainder 8-bit data.

Reference numerals 6 and 7 denote latches for delaying the remainder data from the divider 5 pixel by pixel. That is,
The remaining 8-bit data from the latch 7 is added by the adder 2 to the input data input after two pixels. An error distribution table 8 stores in advance error data to be distributed to the pixel positions shown in FIG. 2A for each value of the quotient data from the divider 5. For example, when the quotient is 1 and the remainder is 50, e0 to 128, e1 to 71, e2 to 37, e3 to 2
The error data of 0 is distributed to the pixel on the right of e0 by 50.
Error data is distributed.

Reference numerals 9, 11, 13 are latches for delaying data by one pixel. Reference numerals 10 and 12 are adders, which are used for adding error data. or,
Reference numeral 14 denotes an error buffer capable of storing data for one line, which delays the error data for one line.

The circuit of FIG. 1 switches processing from the left to the right in the → direction and from the right to the left in the ← direction for each line of input data. As shown in FIG. 1, the storage position of the error data from the adder 12 in the error buffer 14 changes depending on the processing in the → direction and the processing in the ← direction. This control is executed by a control circuit (not shown).

By executing the zigzag processing for changing the processing direction for each line from the → direction to the ← direction, it is possible to prevent the occurrence of a unique stripe pattern which is a problem when the error diffusion method is executed.

Next, the flow of processing will be described.

The input image pixel data input to the multiplier 1 is 8-bit multivalued image data. In the multiplier 1, the denominator value of the error distribution coefficient as shown in FIG. 3 is multiplied. In the present embodiment, the value of the denominator of the error distribution coefficient is 256, so the value multiplied by 256 is output from the multiplier 1 and input to the adder 2. The adder 2 is
The input image data multiplied by the denominator of the error distribution coefficient in the multiplier 1 and the rounding error output from the latch 7, the error from the previous line read from the error buffer 14, and the left horizontal (output from the latch 13 → Add the error from the direction processing) or right side (← direction processing) pixel and output. The data output from the adder 2 is input to the comparator 3. The comparator 3 compares the value output from the adder 2 with a predetermined threshold value (127 × 256 in this embodiment). At this time, 1 is output when the output of the adder 2 is larger than the threshold value, and 0 is output otherwise, which becomes binary data. Further, the data output from the adder 2 and the data output from the comparator 3 are input to the subtractor 4, and the latter is subtracted from the former. Since the data output from the adder 2 is 17 bits and the value output from the comparator 3 is 1 bit, the latter is bit-extended inside the subtractor 4, and the denominator multiple of the error distribution coefficient is further added. When the binary data is 1, it becomes 255 × 256, and when it is 0, it also becomes 0.
Then, the binarization error represented by (Equation 1) is calculated. The binarization error calculated by the subtractor 4 is input to the divider 5,
It is divided by the value of the denominator of the allocation coefficient. As a result, the quotient becomes an integer value and becomes a reference value for referring to the error distribution table 8, while the remainder becomes a rounding error of less than 1 and is input to the latch 6.

Here, the remaining 8-bit data is 0 to 255.
However, since the input data is multiplied by 256 in the multiplier 1, the input data is 8 bits (0
~ 255), the remaining 8-bit data 0-255 becomes 0-255 / 256, which is a value less than 1 for 8-bit input data. As a result, the value of the rounding error can be reduced, and the image quality can be improved especially in the highlight portion of the image.

When the value obtained by dividing the data from the subtractor 4 by the value of the denominator of the distribution coefficient is 1.5, the divider 5 outputs a value of -2 and a remainder of +128.
That is, the remaining data will not be negative.

The remaining 8-bit data is delayed by two pixels by the latches 6 and 7 and then input to the adder 2 again. The quotient output from the divider 5 is input to the error distribution table 8 as a reference value. The error distribution table 8 is RAM (random access memory) or R
It is a lookup table configured by an OM (Read Only Memory), and stores a value obtained by multiplying a denominator of a predetermined weighting coefficient for each value of the binarization error. The error distribution table 6 stores values corresponding to error distribution windows as shown in FIGS. 2A and 2B, and each value is a denominator multiple of the error distribution coefficient according to the value of the binarization error. Therefore, each is represented by a 16-bit number. In this embodiment, two symmetrical error distribution windows as shown in FIGS. 2 (a) and 2 (b) are switched for each line depending on the processing direction, and the symmetrical error distribution windows are used. Therefore, one error distribution table is sufficient.

The error distribution table 8 outputs four values ek0, ek1, ek2, and ek3 in accordance with the value of the binarization error k, and each of them has an error distribution window e shown in FIG.
It corresponds to the values 0, e1, e2, and e3. Therefore, the output ek0 is input to the latch 13 and delayed by one pixel, and then input to the adder 2 again. The output ek1 is input to the latch 9 and delayed by one pixel, and then input to the adder 10 to be added to the output ek2. Further, the output of the adder 10 is input to the latch 11 to be delayed by one pixel, and then input to the adder 12 to be added to the output ek3. Then, the output of the adder 12 is written in the error buffer 14.
In this embodiment, the place where the error is written is 2
Depending on the direction of the binarization process, it is a position two pixels away from the pixel of interest to the left or right, and the direction of the binarization process is switched line by line.

By the above processing, 2 for 1 input data
Since the binarization process is completed, the binarization process can be performed on the entire image by shifting the above process by one pixel in the process direction and repeating the process.

As described above, according to the first embodiment of the present invention, the value of the binarization error obtained by multiplying the denominator of the weighting coefficient is calculated in advance and stored in the table. The divider can be omitted, the circuit scale can be reduced, and high-speed processing can be performed. Further, the sum of the density of the input pixel and the error distributed from the peripheral pixels is obtained, the difference between the sum and the binarization result is divided by the denominator of the weighting coefficient, the quotient and the remainder are obtained, and the quotient is stored in the table. By allocating to the peripheral pixels based on the value that is set, and allocating the remainder to the peripheral pixels, the weighting coefficient can be made flexible and the value of the rounding error can be reduced from 0 to less than 1. It is possible to improve the image quality including the light portion.

[Second Embodiment] FIG. 4 is a block diagram for explaining the arrangement of an image processing apparatus according to the second embodiment of the present invention.

In the first embodiment, since the error distribution coefficient as shown in FIG. 3 is used, the denominator of the error distribution coefficient is a power of two. Therefore, the 1 multiplier 1 and the divider 5 of the first embodiment can be omitted because they can be replaced by a bit shift operation. FIG. 4 is obtained by removing the multiplier 1 and the divider 5 from FIG. That is, 8-bit input data is input to bits 8 to 15 of the adder 2, and the operation result of the adder 2 corresponds to the upper 9 bits including the sign bit and the remainder to the sign bit and the lower 8 bits. The error distribution table refers to the upper 9 bits output from the adder 2.
As can be seen from the equation (1), the binarization error can be obtained from the value of the high-order 9 bits from the adder 2 without referring to this error data. If there is no problem, there is no problem even if the table is referred to by the value of the upper 9 bits from the adder 2. Further, binary data o is also registered in the error distribution table 8 and by referring to this value, the comparator 3 in the first embodiment can be omitted.

FIG. 5 shows a more detailed version of the error distribution table shown in FIG.

As described above, according to the second embodiment, the circuit scale can be reduced and the error diffusion process can be executed at high speed without using the multiplier, the divider and the comparator, and the weighting coefficient can be used. It became possible to have flexibility.
Furthermore, the rounding error when distributing the error can be suppressed from 0 to less than 1, and the image quality in the highlight part can be improved.

Although the input image pixel data is 8-bit multi-valued image data in the embodiment described here, it may be represented by a large number of bits such as 4 bits, 12 bits and 16 bits. . The present invention can also be applied when quantizing 8-bit input data into 2-bit or 3-bit data. Further, in the present embodiment, the error distribution window is composed of 4 pixels, but it goes without saying that a larger window or a smaller window can be similarly constructed.

Further, the error distribution coefficient is not limited to that shown in FIG. 3, and other values can be used. Further, the present invention can be applied to a color image by providing the circuit of this embodiment for the number of input colors.

[0037]

As described above, according to the present invention, by setting the value of the rounding error generated by weighting the error data to be less than 1, it is possible to improve the image quality particularly in the highlight portion of the image.

Further, according to the present invention, the multiplier and the divider can be omitted, the circuit scale can be small, that is, the weighting coefficient can be made flexible, and the value of the rounding error itself can be reduced from 0 to less than 1. By doing so, the image quality can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an image processing apparatus according to a first embodiment.

FIG. 2 is a schematic diagram showing an error distribution window.

FIG. 3 is a schematic diagram showing an error distribution coefficient.

FIG. 4 is a block diagram showing a configuration of an image processing apparatus according to a second embodiment.

FIG. 5 is a diagram showing details of an error distribution table according to the second embodiment.

[Explanation of symbols]

 1 Multiplier 2 Adder 3 Comparator 4 Subtractor 5 Divider 6 7,7,9,11,13 Latch 8 Error distribution table 10,12 Adder 14 Error buffer

Claims (6)

[Claims] 1. An input unit for inputting image data, a processing unit for quantizing the image data, weighting error data generated in the quantizing process, and distributing the error data to a plurality of image data. The image processing apparatus is characterized in that the value of the rounding error generated by weighting is less than 1. 2. An error between a density of an input image and a density after binarization is distributed as a binarization error to peripheral pixels of a pixel of interest,
An image processing method for making the average density after binarization equal to the density of an input image is provided with a table in which a value obtained by multiplying a denominator of a weighting coefficient when an error is distributed is calculated in advance, and an input obtained by multiplying a denominator of the weighting coefficient is provided. The sum of the pixel density and the error distributed from the peripheral pixels is calculated, and the difference between the sum and the binarization result is divided by the denominator of the weighting coefficient to calculate the quotient and the remainder. The quotient is stored in the table. An image processing method characterized by allocating to the peripheral pixels based on the existing value and allocating the remainder to the peripheral pixels. 3. The image processing method according to claim 2, wherein the denominator value of the weighting coefficient is a power of 2. 4. The binarization of the input image density is performed by using a value obtained by multiplying a value of an intermediate level of the input image by a denominator of a weighting coefficient as a threshold value, comparing the total sum with the threshold value, and binarizing the input image density. 2. The image processing method described in 2. 5. When the binarization result is 1, the difference between the total sum and the value obtained by multiplying the maximum density by the denominator of the weighting coefficient is divided by the denominator of the weighting coefficient, and when the binarization result is 0, the total sum is obtained. 5. The image processing method according to claim 4, wherein the denominator of the weighting coefficient is used. 6. The image processing method according to claim 2, wherein the division for obtaining the quotient and the remainder is performed by bit shift.