JP3200274B2 - Image processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus, and more particularly to a method for quantizing input data into binary or multi-valued data while storing a difference between an input image density and an output image density by an error diffusion method or the like. The present invention relates to an image processing method and apparatus for processing.

[0002]

2. Description of the Related Art Conventionally, an error diffusion method has been known as a pseudo halftone process for representing input multi-valued data by binary or multi-valued levels smaller than the level of input multi-valued data. This error diffusion method is described in "An Adaptive Al.
goritm for Spatial Gray
Scale "in society for Info
rmation Display 1975 Symp
osium Digest of Technical
Papers, 1975, 36. In this method, the pixel of interest is P, the density of the pixel is v, and the densities of the non-binarized pixels P0, P1, P2, and P3 around the point P are v0, v1, v2, v3, and binarization, respectively. Is a threshold value of T, a binarization error E at the point of interest P is weighted by a weighting coefficient W empirically obtained for peripheral pixels P0, P1, P2, and P3.
This is a method in which weighting processing is performed with 0, W1, W2, and W3, and the weighting processing is performed so that the average density of the output image is macroscopically equal to the density of the input image. At this time, assuming that the output binary data is o, errors E0, E1, E2, and E3 with respect to the peripheral pixels P0, P1, P2, and P3 can be obtained by the following equations.

[0003]

[Outside 1] (However, Vmax: maximum density, Vmin: minimum density) E0 = E × W0; E1 = E × W1; E2 = E × W2; E3 = E × W3; (Example of weight coefficient: W0 = 7/16, W1) = 1/16, W
2 = 5/16, W3 = 3/16)

However, if this method is realized by a logic circuit, as will be understood from the above example, a multiplier and a divider are required for each weight coefficient, so that the circuit scale becomes large. (E- (E0 + E1 + E2 +
E3)) has a disadvantage that the average density of the output image is not equal to the density of the input image.

As a method for solving this problem, Japanese Patent Application Laid-Open No.
JP-A-215169, JP-A-61-52073,
Japanese Patent Application Laid-Open No. 61-293068 discloses a method of reducing the circuit scale by using a shift register in place of a multiplier and a divider by reducing the weighting factor to a power of two. JP-A-63-3507
In Japanese Patent Application Publication No. 4 (1999) -1994, the value of the binarization error weighted in advance is determined for each value of the density information, and the sum of the values is made equal to the binarization error, thereby simplifying the multiplication and division. And a method for eliminating rounding errors has been proposed.

Japanese Patent Application Laid-Open No. 63-155950 proposes a method in which a rounding error is added to weighted peripheral pixels so that the average density of an output image becomes equal to the density of an input image. .

[0007]

However, the above-described method using the shift register has a drawback that the weighting factor is fixed to a power of 2 and the flexibility is poor. Further, in a method of determining a value of a binarized error weighted in advance and adding a rounding error to an error distributed to the weighted peripheral pixels so that the sum of the values becomes equal to the binarized error, The average density is equal to the density of the input image, but the value of the rounding error itself is 0 or at least 1 because of the integer operation. However, there is a disadvantage that the metal is deteriorated.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to improve the quality of a highlight portion of an image by setting the value of a rounding error generated by weighting error data to less than 1. It is an object of the present invention to provide an image processing method and an image processing apparatus which can perform the image processing.

Another object of the present invention is to omit the multiplier and divider for each weighting factor, to reduce the circuit scale, that is, to increase the speed, to make the weighting factor flexible, and to reduce the value of the rounding error itself. It is an object of the present invention to provide an image processing method and apparatus capable of improving the image quality by reducing the value from 0 to less than 1.

[0010]

According to the image processing apparatus of the present invention, the error between the density of the input image and the density after the quantization is determined as a quantization error by the peripheral pixels of the target pixel. In the image processing apparatus that distributes the average density after quantization to the density of the input image, the value obtained by multiplying the denominator by the weighting factor when distributing the error is calculated in advance as the value of the error that is distributed to the peripheral pixel data. Memory means for calculating the sum of the density of the input pixel multiplied by the denominator of the weighting coefficient and the error distributed from the surrounding pixels; and a plurality of higher-order sums of the sum calculated by the calculating means. Distribution means for selecting an error stored in the storage means based on the bit data and distributing the selected error to peripheral pixels, and distributing the lower-order multiple bit data of the sum to the peripheral pixels as surplus data. .

According to the image processing method of the present invention, the error between the density of the input image and the density after binarization is distributed as a binarization error to the peripheral pixels of the target pixel, and the average after binarization is obtained. In an image processing method for making the density equal to the density of the input image, a table is provided in which the value of the denominator multiplied by the weighting factor at the time of distributing the error is calculated in advance, and the density of the input pixel multiplied by the denominator of the weighting factor and the peripheral The sum of the error distributed from the pixel is obtained, the difference between the sum and the binarization result is divided by the denominator of the weight coefficient, and the quotient and remainder are obtained. The quotient is calculated based on the values stored in the table. While distributing to pixels,
The remainder is allocated to peripheral pixels.

Further, according to the image processing method of the present invention, an error between the density of the input image and the density after quantization is distributed to pixels surrounding the pixel of interest as a quantization error, and the average density after quantization is input. In the image processing method for equalizing the density of an image, a table is provided in which a denominator-multiplied value of a weighting factor when distributing an error is calculated and stored in advance as an error value for distributing to peripheral pixel data, The sum of the density of the input pixel multiplied by the denominator and the error distributed from the surrounding pixels is obtained, and the error stored in the storage means is selected and distributed to the surrounding pixels based on the higher-order plural bit data of the sum. At the same time, the lower-order multi-bit data of the sum is distributed to peripheral pixels as surplus data.

According to the present invention, since the value of the binarization error multiplied by the denominator of the weight coefficient is calculated in advance and stored in a table, the multiplier and the divider for each weight coefficient can be omitted. High-speed processing becomes possible by reducing the circuit scale. Further, the sum of the density of the input pixel multiplied by the denominator of the weighting coefficient and the error distributed from the peripheral pixels is obtained, and the selection and remainder of the values stored in the table are calculated based on the sum and distributed to the peripheral pixels. The coefficient can be made flexible and the value of the rounding error can be reduced from 0 to less than 1, so that the image quality including the highlighted portion can be improved.

[0014]

【Example】

[First Embodiment] An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating the configuration of an image processing apparatus according to a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a multiplier.
Is multiplied by the value of the denominator of the distribution coefficient when allocating the error to the 8-bit input data (256 in the case of the distribution coefficient in FIG. 3).
Reference numeral 2 denotes an adder, which adds error data from a pixel that has already been binarized to the 16-bit data from the multiplier 1. Reference numeral 3 denotes a comparator, which is "1" corresponding to an intermediate level between 17-bit data from the adder 2 and 8-bit input data.
27 ”multiplied by the value of the denominator of the distribution coefficient (“ 127 × 2
56 "). The 1-bit binary data from the comparator 3 is sent to an unillustrated inkjet printer or laser beam printer, and an image is formed by turning on and off dots.

A subtractor 4 calculates a difference between 17-bit data from the adder 2 before binarization and a value after binarization, that is, error data. The value after binarization used in the subtractor 4 is 2
When the binarization result is 1, it is “255 × 256”, and when the binarization result is 0, it is “0”.

Reference numeral 5 denotes a divider, which divides the 16-bit data from the subtracter 4 by the value of the denominator of the distribution coefficient, and outputs a quotient of 8 bits (with a sign) and a remainder of 8 bits.

Reference numerals 6 and 7 denote latches for delaying the remainder data from the divider 5 by one pixel. That is,
The remaining 8-bit data from the latch 7 is added by the adder 2 to the input data input two pixels later. Reference numeral 8 denotes an error distribution table in which error data to be distributed to pixel positions shown in FIG. 2A is stored in advance for each value of the quotient data from the divider 5. For example, when the quotient is 1 and the remainder is 50, 128 to e0, 71 to e1, 37 to e2, 2 to e3.
0 is distributed to the pixel on the right of e0.
Are distributed.

Latches 9, 11, and 13 are used to delay data by one pixel. The adders 10 and 12 are used for adding error data. or,
Reference numeral 14 denotes an error buffer capable of storing data for one line, and is for delaying the error data for one line.

The circuit of FIG. 1 switches between processing from left to right in the direction of → and processing from right to left in the direction of ← for each line of input data. As shown in FIG. 1, the storage position of the error data from the adder 12 in the error buffer 14 changes between processing in the rightward direction and processing in the rightward direction. This control is executed by a control circuit (not shown).

By executing the zigzag processing for changing the processing direction between the → direction and the ← direction for each line, it is possible to prevent the generation of a unique fringe pattern which has been a problem when the error diffusion method is executed.

Next, the processing flow will be described.

The input image pixel data input to the multiplier 1 is 8-bit multi-valued image data. In the multiplier 1, the value is multiplied by the value of the denominator of the error distribution coefficient as shown in FIG. In the present embodiment, the value of the denominator of the error distribution coefficient is 256, and the value multiplied by 256 is output from the multiplier 1 and input to the adder 2. The adder 2
The input image data multiplied by the value of the denominator of the error distribution coefficient in the multiplier 1 and the rounding error output from the latch 7, the error from the previous line read from the error buffer 14, and the left side output from the latch 13 ( (Direction processing) or the error from the right side (← direction processing) pixel is added and output. The data output from the adder 2 is input to the comparator 3. The comparator 3 compares the value output from the adder 2 with a predetermined threshold value (127 × 256 in this embodiment). At this time, when the output of the adder 2 is larger than the threshold value, 1 is output, and when not, 0 is output, and this becomes binary data. The data output from the adder 2 and the data output from the comparator 3 are input to a subtractor 4, where the former is subtracted from the latter. Since the data output from the adder 2 is 17 bits and the value output from the comparator 3 is 1 bit, the latter is bit-expanded inside the subtractor 4 and further multiplied by the denominator multiple of the error distribution coefficient. When the binary data is 1, the result is 255 × 256, and when the binary data is 0, the result is 0.
, The binarization error represented by (Equation 1) is calculated. The binarization error calculated by the subtractor 4 is input to a divider 5,
It is divided by the value of the denominator of the distribution coefficient. As a result, the quotient becomes an integer value and becomes a reference value for referring to the error distribution table 8, while the remainder becomes a rounding error less than 1 and is input to the latch 6.

Here, the remaining 8-bit data is 0 to 255
However, since the input data is multiplied by 256 by the multiplier 1, the input data has 8 bits (0
To 255), the remaining 8-bit data 0 to 255 is 0 to 255/256, which is less than 1 for 8 bits of input data. As a result, the value of the rounding error can be reduced, and particularly, the image quality in the highlight portion of the image can be improved.

When the value obtained by dividing the data from the subtracter 4 by the value of the denominator of the distribution coefficient is 1.5, the divider 5 outputs a value of −2 as a quotient and outputs +128 as a remainder.
That is, the remaining data does not become a negative value.

The remaining 8 bits of data are delayed by latches 6 and 7 for two pixels and then input to adder 2 again. The quotient output from the divider 5 is input to the error distribution table 8 as a reference value. The error distribution table 8 is a RAM (random access memory) or R
This is a look-up table constituted by an OM (read only memory), and stores a value obtained by multiplying a predetermined denominator by a predetermined weighting factor for each binarization error value. The error distribution table 6 stores values corresponding to error distribution windows as shown in FIGS. 2A and 2B, and each value is a denominator multiple of the error distribution coefficient according to the value of the binarization error. Therefore, each is represented by a 16-bit number. In this embodiment, two symmetrical error distribution windows as shown in FIGS. 2A and 2B are used by switching one line at a time in accordance with the processing direction. Therefore, one error distribution table is sufficient.

The error distribution table 8 outputs four values ek0, ek1, ek2, and ek3 in accordance with the value of the binarization error k, and each of them outputs an error distribution window e shown in FIG.
It corresponds to values to 0, e1, e2, and e3. Therefore, the output ek0 is input to the latch 13, and after being delayed by one pixel, is input again to the adder 2. The output ek1 is input to the latch 9 and a delay of one pixel is added. Then, the output ek1 is input to the adder 10 and added to the output ek2. Further, the output of the adder 10 is input to the latch 11 and a delay corresponding to one pixel is added thereto. Then, the output of the adder 12 is written to the error buffer 14.
In this embodiment, the location where the error is written is 2
Depending on the direction of the binarization process, the position is two pixels to the left or right of the target pixel, and the direction of the binarization process is switched every line.

By the above processing, 2 for one input data
Since the binarization processing is completed, the above processing is repeated while being shifted by one pixel in the processing direction, thereby enabling binarization processing for the entire image.

As described above, according to the first embodiment of the present invention, the value of the binarization error multiplied by the denominator of the weight coefficient is calculated in advance and stored in the table. The divider can be omitted, the circuit scale can be reduced, and high-speed processing can be performed. Further, the sum of the density of the input pixel and the error distributed from the surrounding pixels is obtained, and the difference between the sum and the binarization result is divided by the denominator of the weight coefficient to obtain a quotient and a remainder, and the quotient is stored in a table. By allocating the remainder to the peripheral pixels based on the set value, the weight coefficient can be given flexibility and the value of the rounding error can be reduced from 0 to less than 1 by allocating the remainder to the peripheral pixels. It is possible to improve the image quality including the light portion.

[Second Embodiment] FIG. 4 is a block diagram illustrating the configuration of an image processing apparatus according to a second embodiment of the present invention.

In the first embodiment, since the error distribution coefficient as shown in FIG. 3 is used, the number of denominators of the error distribution coefficient is a power of two. Therefore, the 1-multiplier 1 and the divider 5 of the first embodiment can be omitted because they can be replaced by a bit shift operation. FIG. 4 is obtained by removing the multiplier 1 and the divider 5 from FIG. That is, the input data of 8 bits is input to bits 8 to 15 of the adder 2, and in the operation result of the adder 2, the upper 9 bits including the sign bit correspond to the quotient, and the sign bit and the lower 8 bits correspond to the remainder. The error distribution table refers to the upper 9 bits output from the adder 2.
As can be understood from the equation (1), the binarization error can be obtained from the value of the upper 9 bits from the adder 2 without referring to this error data. If it does, there is no problem even if the table is referred to by the value of the upper 9 bits from the adder 2. Further, the binary data o is also registered in the error distribution table 8, and by referring to this value, the comparator 3 in the first embodiment can be omitted.

FIG. 5 shows the error distribution table shown in FIG. 4 in more detail.

As described above, according to the second embodiment, it is possible to execute the error diffusion process at a high speed by reducing the circuit scale without using a multiplier, a divider and a comparator, and to reduce the weight coefficient. It became possible to have flexibility.
Further, the rounding error in distributing the error can be suppressed from 0 to less than 1, and the image quality in the highlighted portion can be improved.

In this embodiment, the input image pixel data is 8-bit multi-valued image data. However, the input image pixel data may be represented by a large number of bits such as 4 bits, 12 bits, and 16 bits. . The present invention can also be applied to quantizing 8-bit input data into 2-bit or 3-bit data. Further, in this embodiment, the error distribution window is constituted by four pixels. However, it goes without saying that the error distribution window can be constituted in the same manner even if the window is larger or smaller.

The error distribution coefficient is not limited to the one shown in FIG. 3, and other values can be used. Further, the present invention can be used for a color image by providing the circuits of this embodiment as many as the number of input colors.

[0037]

[0038]

As described above, according to the present invention, the multiplier and the divider can be omitted and the circuit scale can be reduced, that is, the processing by the error diffusion method can be performed at high speed. In addition, the weighting coefficient can be given flexibility, and the value of the rounding error itself can be reduced from 0 to less than 1, thereby improving the image quality.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment.

FIG. 2 is a schematic diagram showing an error distribution window.

FIG. 3 is a schematic diagram showing an error distribution coefficient.

FIG. 4 is a block diagram illustrating a configuration of an image processing apparatus according to a second embodiment.

FIG. 5 is a diagram showing details of an error distribution table according to the second embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplier 2 Adder 3 Comparator 4 Subtractor 5 Divider 6, 7, 9, 11, 13 Latch 8 Error distribution table 10, 12 Adder 14 Error buffer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-64-32765 (JP, A) JP-A-61-293068 (JP, A) JP-A-61-52073 (JP, A) JP-A 8- 32805 (JP, A) JP-A-63-155951 (JP, A) JP-A-2-57365 (JP, A) JP-A-3-201677 (JP, A) JP-B-5-13421 (JP, B2) (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/405 G06T 5/00 200 H04N 1/40 H04N 1/403

Claims (6)

(57) [Claims] 1. An error between a density of an input image and a density after quantization is distributed as a quantization error to pixels around a pixel of interest.
In an image processing apparatus for equalizing the average density after quantization to the density of an input image, a value multiplied by the denominator of the weighting factor when allocating the error is calculated and stored in advance as an error value to be allocated to peripheral pixel data. Storage means, calculating means for calculating the sum of the density of the input pixel multiplied by the denominator of the weighting coefficient, and the error distributed from the peripheral pixels, based on the higher-order multi-bit data of the sum calculated by the calculating means An image processing apparatus, comprising: a distribution unit that selects an error stored in the storage unit and distributes it to peripheral pixels, and distributes the lower-order multiple bits data of the total as peripheral data to peripheral pixels. 2. An error between the density of the input image and the density after binarization is distributed as a binarization error to pixels surrounding the pixel of interest.
In an image processing method for equalizing the average density after binarization with the density of an input image, a table is provided in which a denominator multiplied value of a weighting factor at the time of allocating an error is calculated in advance. The sum of the density of the pixel and the error distributed from the surrounding pixels is obtained, the difference between the sum and the binarization result is divided by the denominator of the weight coefficient to obtain a quotient and a remainder, and the quotient is stored in the table. An image processing method comprising: allocating the remainder to peripheral pixels based on the value of the image data. 3. The image processing method according to claim 2, wherein the value of the denominator of the weight coefficient is a power of two. 4. A binarization of the input image density, wherein a value obtained by multiplying a value of an intermediate level of the input image by a denominator of a weighting coefficient is set as a threshold, and the sum is compared with the threshold. 2. The image processing method according to 2. 5. When the binarization result is 1, the difference between the sum and the maximum density multiplied by the denominator of the weighting coefficient is divided by the denominator of the weighting coefficient. When the binarization result is 0, the summation is performed. 5. The image processing method according to claim 4, wherein is divided by a denominator of the weight coefficient. 6. An error between the density of the input image and the density after quantization is distributed as a quantization error to pixels surrounding the pixel of interest.
In an image processing method for equalizing the average density after quantization to the density of an input image, a value obtained by multiplying a denominator multiplied by a weighting factor when allocating an error is calculated and stored in advance as an error value to be allocated to peripheral pixel data. A sum of the density of the input pixel multiplied by the denominator of the weighting coefficient and the error distributed from the surrounding pixels is obtained, and the error stored in the storage means is determined based on the higher-order multiple-bit data of the sum. An image processing method comprising: selecting and allocating data to peripheral pixels; and allocating lower-order plural-bit data of the sum as residual data to peripheral pixels.