JPH04205029A - Microprocessor - Google Patents

Abstract

PURPOSE:To speed up the execution of an instruction inside a micro-processor by providing the microprocessor with two types of pipe lines for floating point arithmetic operation and loading/storing floating point data. CONSTITUTION:Instruction decoder 10 reads two instructions at a time via signal lines 71 and 72, and generates decode information and sends it to signal lines 11-13. Pipe line 20 receives decoded information via signal line 12, and if the decoded information received is a floating point arithmetic instruction, the pipe line 20 stores it in the pipe line. Pipe line 30 receives decoded information, and if this decoded information is a load/store information, the pipe line 30 stores it therein. Control circuit 40 receives decoded information via the signal line 11. If instructions read in the decoder 10 cannot be executed at a time, the circuit 40 weights the execution of a load instruction transferred to pipe line 30 via signal line 42. Control circuit 50 receives floating point arithmetic instruction decoded information via signal line 21 and instruction decoded information from control circuit 60 via signal line 31, and executes both signals, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an internal structure of a microprocessor suitable for use in a system in which a floating point arithmetic processor is connected to a microprocessor.

(Prior Art) In order to execute optional operations such as floating point and decimal operations at high speed, it is common practice to use a dedicated coprocessor, connect it to a microprocessor, and execute it to distribute the load on the microprocessor. Conventionally, in microcombininator systems in which a processor for floating-point arithmetic is connected to a microprocessor, the pipeline for floating-point arithmetic and the pipeline for loading/storing floating-point data were not separated. / Store operations could not be executed simultaneously.

(Problems to be Solved by the Invention) As mentioned above, in the past, it was not possible to simultaneously execute floating-point operations and loading/store of floating-point data, and therefore the execution speed of floating-point operations did not improve as expected. There was a problem.

This invention has been made in view of the above circumstances, and provides a microprocessor system that uses floating point arithmetic hardware as a coprocessor, by executing floating point instructions and floating point data load/store instructions in parallel. The purpose of the present invention is to provide a microprocessor capable of speeding up instruction execution.

[Configuration of the Invention (Means for Solving the Problems) The microprocessor of the present invention includes an instruction decoder that simultaneously obtains a plurality of instructions, analyzes the instructions, and generates decode information; A floating-point pipeline that stores this information in the pipeline if it is a floating-point arithmetic instruction, and receives decode information through the instruction decoder and stores it in the pipeline if it is a data load/store instruction. A pipeline for load/store instructions that stores this information, and each of the above pipelines that receives decode information from the instruction decoder, checks whether multiple instructions can be executed simultaneously, and stores instructions to be executed later. It is characterized in that it includes a pipeline control circuit that sends control information to start or wait execution by sending control information to the processor, and simultaneously executes floating-point operations and loading/store of floating-point data.

(Function) As described above, the present invention provides a microprocessor system in which a coprocessor for floating point arithmetic is connected to a microprocessor.
an instruction decoder and a floating-point calculation pipeline that stores control information regarding floating-point calculation instructions to be executed;
A floating-point load/store pipeline that stores control information regarding floating-point data load/store instructions and a pipeline control circuit that controls the operation of each pipeline are provided. It checks whether multiple instructions can be executed simultaneously according to the decode information that arrives, and sends control information to each of the above pipelines that stores instructions to be executed later to start or wait for execution. , which simultaneously executes floating point operations and loading/store of floating point data.

By providing two types of pipelines inside the microprocessor, one for floating-point arithmetic operations and one for floating-point data load/store, floating-point arithmetic instructions and floating-point data load/store instructions can be executed simultaneously. This apparently speeds up instruction execution.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, reference numeral 1 denotes a microprocessor, which reads instructions and data from the main memory 80 and executes floating point data instructions. Reference numeral 10 is an instruction decoder, which decodes instructions and converts them into control information. A signal line 11 transmits instruction decode information decoded by the instruction decoder 10 to a pipeline control circuit 40, which will be described later.

[Symbol] 2 is a signal line, and the instruction decode information decoded by the instruction decoder 10 is transferred to the floating point arithmetic pipeline 2.
Transmit to 0. A signal line 13 transmits instruction decode information decoded by the instruction decoder 10 to a pipeline 30 for floating-point data load/store instructions. The code 20 is a pipeline for floating point calculations, and 1
, the control information of floating-point arithmetic instructions is accumulated in a pipeline structure.

A signal line 21 transmits information from the floating point arithmetic pipeline 20 to the floating point arithmetic control circuit 5°.

Reference numeral 30 is a pipeline for load/store instructions;
Control information for floating-point data load/store instructions is accumulated in a pipeline structure. Reference numeral 31 is a signal line,
Information of the load/store instruction pipeline 30 is transmitted to the floating point data load/store control circuit 60. A signal line 41 transmits control information from the pipeline control circuit 40 to the floating-point arithmetic pipeline 20.

A signal line 42 transmits control information from the pipeline control circuit 40 to the load/store instruction pipeline 30. Reference numeral 50 is a floating point arithmetic control circuit which generates a control code for executing floating point arithmetic.

Reference numeral 51 is a signal line, and the floating point arithmetic control circuit 50
The control code generated is transmitted to the floating point arithmetic circuit 90. Reference numeral 60 denotes a load/store control circuit, which generates a control code for controlling loading/store of floating point data to/from the floating point arithmetic circuit 90, and also executes data exchange. A signal line 61 transmits the code generated by the floating point arithmetic control circuit 50 to the floating point arithmetic circuit 90. Reference numeral 62 denotes a data bus, which transmits and receives data between the load/store control circuit 60 and the floating point arithmetic circuit 90. A data bus 63 transmits and receives data between the load/store control circuit 60 and the memory control circuit 70.

Reference numeral 64 is a control signal line, through which the load/store control circuit 60 controls the memory control circuit 70 when executing a load/store operation. A memory control circuit 70 performs memory control when reading instructions from the main memory 80 or loading/storing floating point data. Reference numeral 71 is a signal line, and data is exchanged between the memory control circuit 70 and the main memory 80 via this signal line. Reference numeral 80 is a main memory in which instructions and floating point data are stored.

Reference numeral 90 denotes a floating point arithmetic circuit, which executes floating point arithmetic by receiving and receiving control codes via the signal line 51, and also receives and receives control codes via the control line 61 and executes the control code via the control line 62. Read floating point data via/
Do light. The floating point arithmetic circuit 90 includes circuits necessary for floating point arithmetic, such as a floating point register.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. First, the instruction decoder 10 reads two instructions simultaneously via signal lines 71 and 72. The instruction decoder 10 further analyzes the read instruction to generate decode information, and sends the decode information to signal lines 11, 12, and 13. Floating point arithmetic pipeline 20 receives decode information via signal line 12 and stores this information within the pipeline if this is a floating point arithmetic instruction. The load/store instruction pipeline 30 receives and receives decode information via the signal line 13, and if this is a load/store instruction, stores this information within the pipeline. The pipeline control circuit 40 receives decode information via the signal line 1].

If the two instructions read by the instruction decoder 10 cannot be executed simultaneously, a signal line 41 is sent to the pipeline 20 or 30 where the instruction to be executed later is stored.
Alternatively, control information is sent via 42 to weight execution. For example, one of the two instructions is a floating-point addition instruction and the other is a load instruction, the source of the addition instruction and the destination of the load instruction match, and the addition instruction is stored at an address before the load instruction. If it is, the load instruction must be executed after the addition instruction has been executed. In this case, the pipeline control circuit 40 waits for execution of the load instruction stored in the load/store instruction pipeline 30 via the signal line 42. In this case, floating point operations and load instructions cannot be executed simultaneously. The floating-point arithmetic control circuit 50 receives instruction decode information for floating-point arithmetic instructions via the signal line 21 and instruction decode information for the load instruction from the load/store control circuit 60 via the signal line 31, and executes them. .

When executing a floating point arithmetic operation, the floating point arithmetic control circuit 50 generates a control code from the instruction decode information received through the signal line 21 and sends it to the floating point arithmetic circuit 90 through the signal line 51. Floating point arithmetic circuit 90
performs operations based on this code.

When executing a load/store of floating point data, the load/store control circuit 60 generates a control code based on the instruction decode information received from the signal line 31 and sends it to the floating point arithmetic circuit 90 through the signal line 61. Send control code. When executing a load, the floating point arithmetic circuit 90 connects the signal line 71, the memory control circuit 70, the load/
Store control circuit 60, main memory 80 through signal line 62
The data sent from the floating point arithmetic circuit 90 is stored in the floating point arithmetic circuit 90. When executing a store, the floating point arithmetic circuit 90 connects the signal line 62, the load/store control circuit 60, and the signal line 63.
, the main memory 8 through the memory control circuit 70 and the signal line 71.
Send data to 0.

Memory control when performing load/store operations is performed by memory control circuit 70. The load/store control circuit 60 generates information necessary for the memory control circuit 70 to control the main memory 80 from the instruction decode information received from the signal line 31, and sends the information to the memory control circuit 70 via the signal line 64. Send to.

[Effects of the Invention] As described above, according to the present invention, a microprocessor has internal functions for floating point operations and loading/loading of floating point data.
By providing two types of store pipelines, floating point arithmetic instructions and floating point data load/store instructions can be executed simultaneously, apparently speeding up instruction execution.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. 10...Instruction decoder 20...Floating point calculation pipeline 30...Floating point calculation data load/
Store instruction pipeline 40...Pipeline control circuit 50...
......Floating point arithmetic control circuit 60...
...Load/store control circuit 70...
-Memory control circuit 80...Main memory 90...Floating point arithmetic circuit.

Claims (1)

[Claims] An instruction decoder that obtains multiple instructions at the same time and analyzes them to generate decode information; and a floating point system that receives decode information via the instruction decoder and stores this information in the pipeline if it is a floating point operation instruction. a pipeline, a load/store instruction pipeline that receives decode information via an instruction decoder and stores this information in the pipeline if this is a data load/store instruction; and a load/store instruction pipeline that receives decode information from the instruction decoder; It is equipped with a pipeline control circuit that checks whether multiple instructions can be executed simultaneously and sends control information to each of the pipelines mentioned above in which instructions to be executed later are stored to start or wait execution. , a microprocessor characterized in that it simultaneously executes floating point operations and loading/store of floating point data.