JPH0573263A - Data processor - Google Patents

Abstract

PURPOSE:To speed up the execution of instruction by enabling the simultaneous execution of more than two instructions by providing at least two-system of pipelines in a microprocessor with a floating point arithmetic processor connected. CONSTITUTION:This data processor is provided with an instruction decoder 10, pipelines 20 and 30 storing control information about each instruction of a floating point arithmetic instruction and the load storing instruction of the floating point data in a pipeline structure, floating point arithmetic control circuits 50 and 60 corresponding to the number of pipelines controlling the execution of each instruction, a floating point arithmetic circuit 90 executing the floating point arithmetic operation by performing read and write of the floating point data according to the control information to be generated, and a pipeline control circuit 40 parallely operating more than two transfer instructions of the floating point arithmetic instruction or the transfer instruction of the floating point data by performing the control of the pipeline according to the control information which is outputted from the instruction decoder 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a data processing device suitable for use in a microprocessor and for performing improved floating point arithmetic.

[0002]

In the field of high performance microprocessors,
For faster processing. It is common practice to employ cache memory and pipeline operations. Further, in order to improve the throughput of the processor itself, the processing is often distributed to the optional devices. A typical example is a computer in which a floating point arithmetic processor is connected as a coprocessor. By the way, in this type of computer system, since there is only one pipeline, the floating point arithmetic instruction and the load / store instruction cannot be executed at the same time.

[0003]

As described above, in a computer in which a conventional floating point arithmetic processor is connected as a coprocessor, two or more instructions cannot be executed at the same time. The execution speed of the operation could not be improved as expected, and there was a problem in increasing the speed of the floating point operation.

The present invention has been made in view of the above circumstances. In a microprocessor to which a coprocessor for floating-point arithmetic is connected, two or more instructions can be simultaneously executed, and the instruction execution speed can be increased. It is an object of the present invention to provide a data processing device aiming at the above.

[0005]

SUMMARY OF THE INVENTION The present invention provides an instruction decoder for decoding an instruction and generating control information in a data processing device for executing a floating point operation instruction by connecting a floating point operation circuit to the outside. , A floating point arithmetic instruction and a floating point data load / store instruction, and at least two pipelines for storing control information regarding a floating point arithmetic instruction and a floating point data load / store instruction in a pipeline structure. A floating-point arithmetic control circuit corresponding to the number of pipelines whose execution is controlled, a floating-point arithmetic circuit that performs floating-point arithmetic by reading / writing floating-point data according to control information generated by this circuit, and the above instruction Control the pipeline according to the control information output by the decoder,
A pipeline control circuit for operating two or more floating point arithmetic instructions or floating point data transfer instructions in parallel is provided.

[0006]

According to the present invention, the instruction decoder first decodes two or more instructions obtained from the main memory, converts them into control information, and supplies the control information to each pipeline. The pipeline stores this in a pipeline structure,
It is controlled by the pipeline control circuit. According to the decode information, the pipeline control circuit interprets the two read instructions as being able to be executed simultaneously, and executes them simultaneously. Thus, by providing two stages of pipelines capable of storing control information of both floating point instructions and floating point data load / store instructions inside the microprocessor, floating point arithmetic instructions or floating point data load / store instructions can be stored. However, up to two commands can be executed simultaneously, and the speed of instruction execution can be apparently increased.

[0007]

1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 is a microprocessor,
Instructions and data are read from the main memory 80 to execute floating point arithmetic instructions.

Inside the microprocessor 1, reference numeral 10 is an instruction decoder, which decodes an instruction and converts control information. Reference numeral 11 is a signal line for transmitting the instruction decode information decoded by the instruction decoder 10 to the pipeline control circuit 40. Reference numeral 12 is a signal line for transmitting the instruction decode information decoded by the instruction decoder 10 to the first pipeline (pipeline 1) 20. Reference numeral 13 is a signal line for transmitting the decode information to the second pipeline (pipeline 2) 30 in the instruction decoder 10.

Reference numeral 20 is a first pipeline (pipeline 1), which stores control information of floating point arithmetic instructions and load / store instructions of floating point data in a pipeline structure. Reference numeral 21 is a signal line for transmitting information of the first pipeline (pipeline 1) 20 to the first floating-point arithmetic control circuit (floating-point arithmetic control circuit 1) 50. Reference numeral 30 is a second pipeline (pipeline 2),
Floating-point arithmetic instructions and control information for floating-point load / store instructions are accumulated in a pipeline structure. Reference numeral 31 is a signal line for transmitting information of the second pipeline (pipeline 2) 30 to the second floating point arithmetic control circuit (floating point arithmetic control circuit 2) 60.

Reference numeral 40 is a pipeline control circuit,
According to the information of the instruction decoder 10, each of the above pipelines 2
Control 0,30. Reference numeral 41 indicates control information of the pipeline control circuit 40 as a first pipeline (pipeline 1).
20 is a signal line transmitted to 20. Reference numeral 42 is a signal line for transmitting control information of the pipeline control circuit 40 to the second pipeline (pipeline 2) 30.

Reference numeral 50 denotes a first floating-point arithmetic control circuit (floating-point arithmetic control circuit 1), which receives information relating to an instruction via the signal line 21 and executes a floating-point arithmetic operation, and a floating-point arithmetic operation. It generates control code that controls loading / storing of data, and also executes data transfer. Reference numeral 51 is a signal line for transmitting the control code generated by the first floating point arithmetic control circuit (floating point arithmetic control circuit 1) 50 to the floating point arithmetic circuit 90. Reference numeral 52 is a data bus for exchanging data between the floating point arithmetic control circuit 1 (50) and the floating point arithmetic circuit 90. Reference numeral 53 denotes a data bus, which exchanges data between the first floating point arithmetic control circuit (floating point arithmetic control circuit 1) 50 and the memory control circuit 70. Code 5
Reference numeral 4 is a signal line for controlling the memory control circuit 70 by the first floating point arithmetic control circuit (floating point arithmetic control circuit 1) 50 when executing load / store.

Reference numeral 60 denotes a second floating point arithmetic circuit (floating point arithmetic circuit 2), which receives control information for receiving information about an instruction via the signal line 31 and executing a floating point arithmetic operation, and loading of floating point data. -Generate a control code to control the store and exchange data. Reference numeral 61 is a signal line for transmitting the control code generated by the second floating point arithmetic circuit (floating point arithmetic circuit 2) 60 to the floating point arithmetic circuit 90. Reference numeral 62 denotes a data bus, which exchanges data between the second floating point arithmetic control circuit (floating point arithmetic control circuit 2) 60 and the floating point arithmetic circuit 90. Reference numeral 63 is a data bus, and the second floating point arithmetic control circuit (floating point arithmetic control circuit 2) 60
Data is exchanged between the memory control circuit 70 and the memory control circuit 70.
Reference numeral 64 is a signal line for the second floating point arithmetic control circuit (floating point arithmetic control circuit 2) 60 to control the memory control circuit 70 when executing the load / store. Reference numeral 70
Is a memory control circuit, which performs memory control when reading an instruction from the main memory 80 or executing load / store of floating-point data. Reference numeral 80 is a main memory that stores instructions and floating point data.

Reference numeral 90 denotes a floating point arithmetic circuit, which executes a floating point arithmetic by receiving a control code via the signal lines 51 and 61, receives a control code from the signal line 51, and floats via a data bus 52. The decimal point data is read / written, the control code is received from the signal line 61, and the floating point data is read / written via the data bus 62. The floating-point arithmetic circuit 90 includes circuits necessary for floating-point arithmetic such as floating-point registers. FIG. 2 is a diagram cited for explaining the operation of the embodiment of the present invention, and shows a pipeline structure. In the figure, the numbers indicate the order in which the instructions are read. Hereinafter, the operation of the embodiment of the present invention will be described in detail. First, the instruction decoder 10 simultaneously reads one or more instructions from the main memory 80 via the data bus 71, the memory control circuit 70, and the line 72.

The instruction decoder 10 analyzes the read instruction and generates decode information. If there is one instruction, the decode information is transmitted to the signal lines 11 and 12. If there are two instructions, the signal line 11 is used. , 12 and 13 are transmitted.

The pipelines 20 and 30 receive the decode information from the instruction decoder 10 via the signal lines 12 and 13, respectively, and store this information in the pipelines 20 and 30 one after another, whether it is a floating point instruction or a load / store instruction. I will do it. However, it is assumed that no interrupt is generated due to this calculation result.

Further, in this pipeline, as shown in FIG. 2, assuming that the number of clocks per pipeline stage is 1T, instructions can be stored in the pipeline one after another. When there is one instruction, only the first pipeline (pipeline 1) 20 is used. The pipeline control circuit 40 receives the decode information from the instruction decoder 10 via the signal line 11.

If the two instructions read as described above cannot be executed simultaneously, the first pipeline (pipeline 1) 2 in which the instructions to be executed later are stored
0, or control information is sent to the second pipeline (pipeline 2) 30 via the signal line 41 or the signal line 42, and execution is weighted. For example, one of the two instructions is a floating point instruction, which is stored in the first pipeline (pipeline 1) 20, the other is a load instruction, which is the second pipeline (pipeline 2) 30.
If the source of the add instruction and the destination of the load instruction match, and the add instruction is stored at an address before the load instruction, the load instruction must be executed after the execution of the add instruction. In this case, the pipeline control circuit 40 waits for the execution of the load instruction stored in the second pipeline (pipeline 2) 30 via the line 42. In this case, the floating point operation and the load instruction can be executed at the same time.

When two instructions are read, the first and second instructions
Floating point arithmetic control circuits 50 and 60 receive and execute instruction decode information of floating point arithmetic instructions and load / store instructions via signal lines 21 and 31, respectively.

When the floating-point operation instruction is stored in the first floating-point operation control circuit (floating-point operation control circuit 1) 50, the first floating-point operation control circuit (floating-point operation Control circuit 1) 50
Generates a control code from the instruction decode information received via the signal line 21 and sends it to the floating point arithmetic circuit 90 via the signal line 51.

The floating point arithmetic circuit 90 executes an arithmetic operation based on this code. When the floating-point operation instruction is stored in the second pipeline (pipeline 2) 30, when executing the floating-point operation, the floating-point operation control circuit 60 uses the control code from the instruction decode information received from the signal line 31. Is generated and sent to the floating point arithmetic circuit 90 through the signal line 61. Floating point arithmetic circuit 9
0 performs an operation based on this code.

When the load / store instruction is stored in the first pipeline (pipeline 1) 20, the floating-point arithmetic control circuit 50 receives it from the signal line 21 when executing load / store of floating-point arithmetic data. A control code is generated from the instruction decode information, and the control code is sent to the floating point arithmetic circuit 90 through the signal line 51. When executing the load, the floating point arithmetic circuit 90
Stores the data sent from the main memory 80 in the floating point arithmetic circuit 90 through the signal line 71, the memory control circuit 70, the floating point arithmetic control circuit 50, and the signal line 52.
When executing the store, the floating point arithmetic circuit 90 includes the signal line 52, the floating point arithmetic control circuit 50, the signal line 53,
Main memory 80 through memory control circuit 70 and signal line 71
Send data to. The memory control circuit 70 controls the main memory 80 when executing load / store. The floating point arithmetic control circuit 50 generates information necessary for the memory control circuit 70 to control the main memory 80 based on the instruction decode information received via the signal line 21, and the memory via the signal lines 54 and 64. It is sent to the control circuit 70.

When the load / store instruction is stored in the floating point arithmetic control circuit 60, the floating point arithmetic control circuit 60 receives the instruction via the signal line 31 when the load / store of the floating point arithmetic data is executed. A control code is generated in the decode information, and the control code is sent to the floating point arithmetic circuit 90 through the signal line 61. The floating point arithmetic circuit 90 includes a signal line 71, a memory control circuit 70,
The data sent from the main memory 80 through the floating point arithmetic control circuit 60 and the signal line 62 is transferred to the floating point arithmetic circuit 90.
Store in. When executing the store, the floating point arithmetic circuit 90 uses the signal line 62, the floating point arithmetic control circuit 60,
Data is sent to the main memory 80 through the signal line 63, the memory control circuit 70, and the signal line 71. The memory control circuit 70 controls the main memory 80 when executing load / store.
Done by

The floating point arithmetic control circuit 60 uses the signal line 31.
The memory control circuit 70 generates information necessary for controlling the main memory 80 from the instruction decode information received via the command decode information and sends it to the memory control circuit 70 via the signal line 64. When one instruction is read, the first floating point operation control circuit (floating point operation control circuit 1) 50 receives the instruction decode information of the floating point operation instruction or the load / store instruction from the signal line 21 and executes it. When executing the floating point arithmetic, the first floating point arithmetic control circuit (floating point arithmetic control circuit 1) 50 generates a control code from the instruction decode information received from the signal line 21, and the floating point arithmetic circuit through the signal line 51. To 90.

When executing loading / storing of floating point operation data, the first floating point operation control circuit (floating point operation control circuit 1) 50 generates a control code from the instruction decode information received from the signal line 21, The control code is sent to the floating point arithmetic circuit 90 through the signal line 51.

When the load is executed, the floating point arithmetic circuit 90 includes the signal line 71, the memory control circuit 70, the first floating point arithmetic control circuit (floating point arithmetic control circuit 1) 5
0, the data sent from the main memory 80 through the signal line 52 is stored.

When executing the store, the floating point arithmetic circuit 90 passes through the signal line 52, the first floating point arithmetic control circuit (floating point arithmetic control circuit 1) 50, the signal line 53, the memory control circuit 70, and the signal line 71. The data is sent to the main memory 80.

In the first floating point arithmetic control circuit (floating point arithmetic control circuit 1) 50, the memory control circuit 70 causes the main memory 8 to operate according to the instruction decode information received from the signal line 21.
Information necessary for controlling 0 is generated and sent to the memory control circuit 70 via the signal line 54.

As described above, the floating point arithmetic instruction and the floating point data are loaded in the microprocessor 1.
By providing two pipelines capable of storing control information for both store instructions, up to two floating point arithmetic instructions or floating point data load / store instructions can be executed simultaneously.

[0029]

As described above, according to the present invention, two stages of pipelines capable of storing control information of both floating point arithmetic instructions and floating point data load / store instructions are provided in the microprocessor. By doing so, up to two floating point arithmetic instructions or floating point data load / store instructions can be executed simultaneously, and the speed of instruction execution can be apparently increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 shows a pipeline structure according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Microprocessor, 10 ... Instruction decoder, 20,
30 ... Pipeline (20 ... First pipeline (pipeline 1), 30 ... Second pipeline (pipeline 2)), 40 ... Pipeline control circuit, 50, 60 ... Floating point arithmetic control circuit (50 ... DESCRIPTION OF SYMBOLS 1 floating-point arithmetic control circuit (floating-point arithmetic control circuit 1), 60 ... 2nd floating-point arithmetic control circuit (floating-point arithmetic control circuit 2), 70
... memory control circuit, 80 ... main memory, 90 ... floating point arithmetic circuit.

Claims (1)

[Claims] 1. A data processing device for executing a floating-point operation instruction by connecting a floating-point operation circuit to the outside, an instruction decoder for decoding an instruction to generate control information, a floating-point operation instruction, and a floating point. At least two pipelines that store control information about each instruction including a data load / store instruction in a pipeline structure, and the number of pipelines that control execution of floating-point arithmetic instructions and floating-point data load / store instructions A floating-point arithmetic control circuit corresponding to the above, a floating-point arithmetic circuit that reads / writes floating-point data according to the control information generated by this circuit, and executes a floating-point arithmetic operation, and the above-mentioned pipe according to the control information output from the instruction decoder. Controls the line to transfer floating point arithmetic instructions or floating point data And a pipeline control circuit for operating two or more instructions in parallel.