JPH042027B2 - - Google Patents

Description

[Detailed Description of the Invention] <<Field of the Invention>> This invention provides a probability density function (p.
df) and uses it as a parameter to improve the transmission characteristics on the receiving side alone.

<<Background of the Invention>> Optimal receivers using statistical methods have been variously studied in conjunction with modeling of target noise.
However, in each case, the receiver circuit is studied according to the noise modeling method for each target, and the optimal general-purpose receiver that operates stably no matter what kind of noise is modeled is a virtual receiver using a large computer. It existed only as a receiver.

For example, in order to realize an optimal receiver, first consider the noise modeling theory, and then calculate the noise probability density function P
Consideration is being given to either expanding (Z) into a simplified formula that is easier to physically process and directly replacing that simplified formula with an electronic circuit, or using a microprocessor to perform arithmetic processing on the simplified formula. .

In this type of design, when the noise model is clarified and a simplified formula is found, an optimal receiver corresponding to the simplified formula is created, but these have different configurations or different calculation algorithms for each noise model. It is necessary to have it. Furthermore, although maximum likelihood test calculations are performed using analog circuits, the calculation processing speed is fast, but there are many settings for operating parameters, which has the disadvantage of placing significant restrictions on the calculation formulas that can be applied to this method. . Furthermore, in the case where arithmetic processing is performed by software using a microprocessor, complex calculations can be performed without complicating the circuit configuration, so there are not many restrictions on the arithmetic expressions to be applied. However, as the calculation algorithm becomes more complex, its processing speed is limited, and it has the disadvantage that it can only support very low-speed data communication in order to operate in real time.

In any case, the optimal receiver based on the statistical method described above operates optimally only when the statistical conditions are satisfied. Therefore, it is necessary to be very careful when inputting the prerequisite conditions, and therefore, to understand the statistical conditions, data averaged from long-term measurements in noise conditions is used, and such average conditions We end up seeking the optimum below.
Conversely, if the noise state of the communication line changes through several different patterns, the average state will be optimal, but
This means that individual patterns are not necessarily optimal.

In order to create an optimal receiver that always operates optimally, it is necessary to have a function that monitors the noise state of the communication line during operation, determines statistical conditions, and feeds back the determination results as parameters for maximum likelihood testing. It becomes necessary. However, until now, no circuit system has been proposed that can accomplish this with a circuit that is actually easy to implement.

≪Object of the Invention≫ An object of the present invention is to be able to perform maximum likelihood test calculation processing at high speed using a simple digital circuit that uses a large amount of memory, and to measure and analyze the noise state during reception operation, and to sequentially transmit the results to the calculation unit. An object of the present invention is to provide a noise-tracking type synchronous general-purpose optimal receiver that can always perform optimal reception by following the fluctuations in the noise state of a communication channel by feeding back to the receiver.

<<Structure of the Invention>> In order to achieve the above object, the present invention provides data on a noise probability density function P(Z), a modification or approximation function thereof, or a function that is part of a maximum likelihood test formula including these. a table access circuit that addresses the function table memory with digitized sample values of the received signal waveform and the synchronization signal waveform to read out the corresponding function data; A maximum likelihood test is performed for each data transmission based on the data read from the output judgment circuit that obtains the demodulated data, and the noise state during reception is measured based on the operation signals of the table access circuit and the output judgment circuit. The present invention is characterized by comprising a noise state analysis circuit that analyzes the noise state and creates a function table tailored to the noise state, and table updating means that replaces the function table created by the analysis circuit in the function table memory.

≪Theoretical background of the invention≫ In general, the probability density function (pd
f) is given by P(z), the optimal synchronous receiver uses the binary synchronizing signals S ₁ (t), S ₂ (t) and the received signal X during the time width T of 1 data bit. (t) to N
It is well known that this can be achieved by sampling twice and performing a maximum likelihood test using the operation shown in equation (1.1).

Here, Λ(〓) is the likelihood ratio, select hypothesis H ₁ (S ₁ was sent) when Λ is less than 1,
Equation (1.1) shows that when Λ is greater than or equal to 1, hypothesis H ₂ (S ₂ was sent) is selected. Also, Xn
is the nth sample value of the received signal wave,
S ₁ n and S ₂ n are the n-th sample values of the synchronization signal, and the relationship is as follows: xn=S ₁ n+Zn (signal is S ₁ )=S ₂ n+Zn (signal is S ₂ ). Here, Zn is a random variable representing noise.

By taking the logarithm of both sides of the above equation (1.1) and rewriting it, the following equation (1.2) is obtained.

y=Σ{logP(xn−S ₂ n) −logP(xn−S ₁ n)}H ₁ 〓 H ₂ 0 ……(1・2) The optimal receiver of this invention is determined by the above maximum likelihood test formula (1 - The operation 2) is realized by the digital circuit described below.

<<Description of Embodiments>> The figure shows the configuration of an optimal receiver according to the present invention. A received signal x(t) is obtained by a filter 1 and an amplifier 2 from a signal applied to an input terminal IN. Further, from this received signal
CL is extracted. The period of the synchronous clock CL is equal to the 1-bit time width T of the transmitted data.

The received signal x(t) is sampled and digitized by the A/D conversion circuit 5,
The sample value xn is input to the subtraction circuit 7.

The synchronous clock CL is added to a synchronous timing circuit 4 consisting of a synchronous oscillation circuit, a synchronous frequency division counter, a decoder, etc., and this timing circuit 4 controls the A/D conversion circuit 5, the waveform data memory 6, and the output determination circuit 11. Such timing conditions are created.

The synchronous timing circuit 4 generates a signal having a frequency N times the frequency 1/T of the synchronous clock CL, and applies this signal to the A/D conversion circuit 5 as a timing signal. That is, the received signal x(t) is sampled N times during one data transmission time T. This sample value is xn (n=1, 2, . . . , N).

In addition, the synchronous timing circuit 4 has a frequency of 2N/
A signal of T is also generated, and this signal and a signal of frequency 1/T are applied as a timing signal to the output determination circuit 11.

Furthermore, the synchronous timing circuit 4 has an R bit (2 ^R =
2N) is stepped at a speed of interval T/2N, and the binary code goes around once every data transmission time T. This binary code output is the waveform memory 6
This becomes the address signal.

The waveform memory 6 stores data S _{1 n and S 2 n (} n=1, 2,
..., N) are stored. However, memory 6
Data S ₁ n and S ₂ n are stored alternately at 2N addresses. That is, data S ₁ n is stored at odd addresses, and data S ₂ n is stored at even addresses. When the memory 6 is addressed by the binary code output of the synchronization timing circuit 4, the synchronization signal waveform data S ₂ n and S ₁ n are read out alternately and input to the subtraction circuit 7.

The subtraction circuit 7 performs a digital operation of subtracting the output of the waveform memory 6 from the output of the A/D conversion circuit 5. That is, data xn-S ₂ n and data xn-S ₁ n are alternately output from the subtraction circuit 7, and this output becomes an address input to either the function table memory 9a or 9b via the bus switching circuit 8.

The switching circuit 8 on the address bus side and the switching circuit 10 on the data bus side of the function table memories 9a and 9b are as follows.
Controlled by CPU 12. The CPU 12 couples one of the function table memories 9a and 9b to itself, and couples the other to the subtraction circuit 7 and the output determination circuit 11.

Assume now that the function table memory 9a is coupled to the subtraction circuit 7 and the output determination circuit 11. In this case, the memory 9a stores the probability density function P(Z) of the noise of the target communication channel, which is determined as described later.
The function logP(Z) obtained by symmetrically transforming is stored in the form of a function table. The data in this function table is calculated in advance by another computer in the initial state, but in the actual operating state, it is a value created and modified by the CPU 12.
Note that the function data here may be data of a function obtained by appropriately approximating or transforming logP(Z).

When the function table memory 9a is addressed with the output of the subtraction circuit 7, the data logP(xn−S ₂ n)
and data logP(xn-S ₁ n) are read out alternately from the memory 9a. This data is transferred to the bus switching circuit 10.
The signal is input to the output determination circuit 11 via. The output determination circuit 11 receives data sequentially read out from the function table memory 9a and determines the received signal x(t).
The total calculation of the above formula (1.2) is performed every data transmission time T, and the value y of the total result is set to 0.
A signal indicating whether y is smaller than 0 or larger than 0, that is, demodulated data RD is output.

During the reception/demodulation operation described above, CPU1
2 is the output of the subtraction circuit 7 (sample value of the received signal)
xn, synchronization signal sample values S ₁ n, S ₂ n) and demodulated data RD output from the output judgment circuit 11, and based on these, measure and analyze the noise state during reception for a certain period of time. . At the same time,
Based on the analyzed and measured noise state, a new function table suitable for the noise state is created in the other unused function table memory 9b for demodulation operation. Analysis and measurement of a series of noise conditions
Once the function table creation process is complete,
The CPU 12 switches the bus switching circuits 8 and 10 simultaneously.

Then, the function table memory 9b is connected to the subtraction circuit 7 and the output judgment circuit 11, and after this, the function table memory 9b
A maximum likelihood test is performed according to the latest function table logP(Z) of b, and demodulated data RD is created. At this time as well, the CPU 12 performs the above-described analysis and measurement of the noise state and creates the function table, and updates the function table in the memory 9a that is not used for demodulation.

By repeating the above operations, the receiving operation is always performed by maximum likelihood test using an appropriate function table in accordance with changes in the noise state, and optimal reception can always be achieved.

As a function table, logP(xn−S ₂ n)−
Using the function data of logP(xn−S ₁ n) or its approximate function data, this table is divided into xn, S ₂ n,
It may also be configured to subtract by S ₁ n and accumulate this data. In addition, data S ₂ n and data from the waveform data memory are
S ₁ n may be configured to be read simultaneously and in parallel.

<<Effects of the Invention>> The main factor that limits the demodulation speed of the optimal receiver according to the present invention is the operating speed of the memory used as the function table, and all other accompanying simple processing can be executed within that time. be done. Therefore, direct real-time calculations can be performed even on carriers at high frequency levels. Further, by increasing the number of sampling times N for maximum likelihood testing, it is possible to sufficiently increase the transmission quality.

Since the probability density function of the noise is fed back to the receiver circuit as an operating parameter by storing the function data in the form of a table in the memory, no external adjustment is required and the operation is extremely stable. Further, the noise state measurement analysis and function table creation processing performed in parallel with the demodulation operation do not require high speed, and can be easily performed using a general microprocessor. In this way, the function table creation process is performed in parallel with the demodulation operation, and the function table used for the demodulation operation is instantly updated to a new one when the process is completed, so the noise state is always up-to-date. A maximum likelihood test can be performed based on the matched function data, and highly reliable demodulation operation can be realized.

The optimal receiver of this invention can be a two-phase PSK (phase shift keying), a binary FSK (frequency shift keying), or a modified version thereof, as long as a synchronization signal (synchronization timing) can be obtained. Even if the modulation method is different, it can be widely supported by changing the contents of the waveform data memory that sets the synchronization signal waveform.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a noise-following type synchronous general-purpose optimum receiver according to an embodiment of the present invention. x(t)...Received signal, xn...Sample value of received signal, 3...Synchronization extraction circuit, 4...Synchronization timing circuit, 5...A/D conversion circuit, 6...Waveform memory, S ₁ n , S ₂ n……Sample value of synchronization signal waveform,
7... Subtraction circuit, 8, 10... Bus switching circuit,
9a, 9b...Function table memory, 11...Output determination circuit, 12...CPU, RD...Demodulated data.

Claims (1)

[Claims] 1. Probability density function P of noise on the target communication channel
(Z) and performs a maximum likelihood test using a statistical method based on the function P(Z) to obtain demodulated data. Function table memory that stores data of modified or approximate functions, or functions that are part of the maximum likelihood test formula including these, in the form of a table; and digitized sample values of received signal waveforms and synchronization signal waveforms to a table access circuit that reads the corresponding function data by addressing the table memory; an output determination circuit that performs a maximum likelihood test determination for each data transmission based on the data read from the function table memory to obtain demodulated data; A noise state analysis circuit that measures and analyzes the noise state being received based on the operating signals of the table access circuit and output determination circuit and creates a function table tailored to the noise state; and a function table created by this analysis circuit. A noise-following type synchronous general-purpose optimal receiver, comprising: table updating means for replacing the function table memory with the function table memory;