CN115347999B - Parallel symbol synchronization method and device, electronic equipment and storage medium - Google Patents
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- H—ELECTRICITY
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Abstract
The embodiment of the invention provides a parallel symbol synchronization method and device, electronic equipment and storage medium, and relates to the technical field of wireless communication and digital communication, wherein the method comprises the following steps: receiving and caching sampled data, converting the sampled data into parallel data, carrying out interpolation filtering processing on the parallel data to generate interpolation filtering data, carrying out timing error calculation and weighting calculation on the interpolation filtering data to generate a multipath timing error result and a weighting timing error result, carrying out loop filtering processing on the weighting timing error result to generate an NCO step value, processing the NCO step value, updating a reference index address, carrying out extraction processing and rate matching processing on the interpolation filtering data, and outputting symbol synchronization data. The method can accurately complete symbol synchronization work.
Description
Technical Field
The present invention relates to the field of wireless communications and digital communications technologies, and in particular, to a parallel symbol synchronization method and apparatus, an electronic device, and a storage medium.
Background
In the fields of wireless communication and digital communication, the performance of a symbol synchronization algorithm and the advantages and disadvantages of an implementation architecture directly affect the demodulation performance of a receiver and the stability of the whole system, a serial symbol synchronization algorithm in the prior art adopts an iterative calculation mode, mainly performs interpolation fitting, sampling error calculation and low-pass filtering steps, and each step of calculation needs to use the last calculation result, so that the delay of the serial symbol synchronization implementation mode is larger, and when a signal is received at a super high speed, the working clock of the system cannot be infinitely improved, so that the symbol synchronization work cannot be accurately completed.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, the invention provides a parallel symbol synchronization method and device, electronic equipment and storage medium, which can greatly improve the processing capacity of symbol synchronization without causing performance loss and realize ultra-high-speed symbol synchronization work.
To achieve the above object, a first aspect of an embodiment of the present invention provides that:
receiving sampling data and caching the sampling data;
converting the sampling data into parallel data according to a reference index address and a preset reading rule;
Performing interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
Performing timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
performing weighted calculation on the multipath timing error result according to a preset weighted calculation formula to generate a weighted timing error result;
Performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
updating the reference index address according to the NCO step value and a preset parameter updating formula;
Extracting the interpolation filtering data according to a preset extraction rule to generate extraction data;
And carrying out rate matching processing on the extracted data according to a rate matching rule, and outputting symbol synchronization data.
In some embodiments of the present invention, the converting the sampled data into parallel data according to the reference index address and a preset read rule includes:
taking the sampling data of four sampling points as a group of sampling group data;
Acquiring a plurality of groups of sample group data according to the interpolation quantity in the reference index address;
and converting the sampling group data into parallel data according to a preset reading rule.
In some embodiments of the present invention, the performing interpolation filtering processing on the parallel data according to a preset interpolation filtering formula, and generating interpolation filtered data includes:
Gating a plurality of interpolation filter channels according to the interpolation quantity;
Correspondingly inputting the parallel data into an interpolation filtering channel;
converting the parallel data into interpolation filtering data according to a preset interpolation filtering formula
In some embodiments of the present invention, the loop filtering the weighted timing error result according to a preset loop filtering formula, and generating an NCO step value includes:
performing filtering calculation on the weighted timing error result according to a preset loop filtering formula to obtain a filtering result;
And inputting the filtering result into a numerical control oscillator and performing stepping calculation to obtain the NCO stepping value.
In some embodiments of the present invention, the updating the reference index address according to the NCO step value and a preset parameter updating formula includes:
calculating the NCO stepping value according to a preset parameter updating formula to obtain the NCO phase value of the numerical control oscillator;
Transmitting the NCO phase value of the numerically controlled oscillator to the read control module;
and updating the reference index address according to the NCO phase value of the numerical control oscillator.
In some embodiments of the present invention, the decimating the interpolation filtered data according to a preset decimation rule, and generating decimated data includes:
Marking the interpolation filtered data in odd order as first data;
marking the interpolation filtered data of even order as second data;
Extracting the second data;
and selecting the first data to generate the extracted data.
In some embodiments of the present invention, the performing rate matching processing on the decimated data according to a rate matching rule, and outputting symbol synchronization data includes:
caching the extracted data;
Adjusting the time sequence of the extracted data;
Converting the extracted data into symbol synchronization data according to a preset rate;
and outputting the symbol synchronization data.
To achieve the above object, a second aspect of an embodiment of the present invention provides a parallel symbol synchronization device, including:
The data caching module is used for receiving sampling data and caching the sampling data;
The reading control module is used for converting the sampling data into parallel data according to the reference index address and a preset reading rule;
The parallel interpolation filtering module is used for carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
the timing error calculation module is used for carrying out timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
the weighting calculation module is used for carrying out weighting calculation on the multipath timing error results according to a preset weighting calculation formula to generate weighted timing error results;
The loop filtering module is used for carrying out loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
The parameter updating module is used for updating the reference index address according to the NCO step value and a preset parameter updating formula;
The extraction module is used for carrying out extraction processing on the interpolation filtering data according to a preset extraction rule to generate extraction data;
And the rate matching module is used for carrying out rate matching processing on the extracted data according to a rate matching rule and outputting symbol synchronization data.
To achieve the above object, a third aspect of an embodiment of the present invention provides an electronic device, including:
At least one memory;
At least one processor;
at least one program;
The program is stored in the memory, and the processor executes the at least one program to implement:
the parallel symbol synchronization method of the first aspect as described above.
To achieve the above object, a fourth aspect of the present invention proposes a storage medium that is a computer-readable storage medium storing computer-executable instructions for causing a computer to execute:
the parallel symbol synchronization method of the first aspect as described above.
The embodiment of the invention provides a parallel symbol synchronization method and device, electronic equipment and a storage medium, which are used for converting sampling data into parallel data according to a reference index address and a preset reading rule by receiving the sampling data and caching the sampling data; then carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data; performing timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result; carrying out weighted calculation on the multipath timing error result according to a preset weighted calculation formula to generate a weighted timing error result; performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value; updating a reference index address according to the NCO step value and a preset parameter updating formula; extracting the interpolation filtering data according to a preset extraction rule to generate extraction data; and carrying out rate matching processing on the extracted data according to a preset rate matching rule, and outputting symbol synchronization data. Therefore, the invention can solve the problem that the system working clock cannot be infinitely increased and the symbol cannot synchronously work when the ultra-high-speed signal receiving is carried out, and can effectively improve the accuracy of completing the symbol synchronous work.
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The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.
FIG. 1 is a flow chart of a parallel symbol synchronization method provided by an embodiment of the present invention;
FIG. 2 is a flow chart of a parallel symbol synchronization method provided by one embodiment of step S120 of FIG. 1;
FIG. 3 is a flow chart of a parallel symbol synchronization method provided by one embodiment of step S130 of FIG. 1;
FIG. 4 is a flow chart of a parallel symbol synchronization method provided by one embodiment of step S160 of FIG. 1;
FIG. 5 is a flow chart of a parallel symbol synchronization method provided by one embodiment of step S170 of FIG. 1;
FIG. 6 is a flow chart of a parallel symbol synchronization method provided by one embodiment of step S180 of FIG. 1;
FIG. 7 is a flow chart of a parallel symbol synchronization method provided by one embodiment of step S190 of FIG. 1;
FIG. 8 is a schematic diagram of a system architecture of a parallel symbol synchronization method according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of first and second is for the purpose of distinguishing between technical features only and not necessarily for the purpose of indicating or implying any particular order or precedence of such features or of indicating or implying any particular amount of such features.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
The embodiment of the invention provides a parallel symbol synchronization method and device, electronic equipment and storage medium, which are used for receiving sampling data and caching the sampling data, wherein symbol synchronization based on a Gardner algorithm generally needs to be sequentially processed by interpolation filtering, timing error estimation, loop filtering, a numerical control oscillator and the like, and fixed processing delay is needed when the symbol synchronization is realized. When facing to the ultra-high speed symbol rate, each clock can receive 1 or more sampling data, and the symbol synchronization module can only meet the synchronous work of the ultra-high speed symbol rate by adopting a parallel processing mode, and converts the sampling data into parallel data according to a reference index address and a preset reading rule; then carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data; performing timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result; carrying out weighted calculation on the multipath timing error result according to a preset weighted calculation formula to generate a weighted timing error result; performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value; updating a reference index address according to the NCO step value and a preset parameter updating formula; extracting the interpolation filtering data according to a preset extraction rule to generate extraction data; and carrying out rate matching processing on the extracted data according to a preset rate matching rule, and outputting symbol synchronization data. Therefore, the invention can solve the problem that the system working clock can not be infinitely increased and the symbol can not work synchronously when the ultra-high speed signal receiving is carried out, and can accurately complete the symbol synchronous work.
It should be noted that the numerically controlled oscillator (NCO, numerically controlled oscillator) is an important component of a software radio, a direct data frequency synthesizer (DDS, DIRECT DIGITAL synthesizer), a fast fourier transform (FFT, fast Fourier Transform), etc., and is also one of the main factors determining the performance of the oscillator, and is used to generate a controllable sine wave or cosine wave. With the improvement of chip integration level, the method is widely applied to the fields of signal processing, digital communication, modulation and demodulation, variable frequency speed regulation, guidance control, power electronics and the like.
Embodiments of the present invention will be further described below with reference to the accompanying drawings.
Fig. 1 is an optional flowchart of a parallel symbol synchronization method provided in an embodiment of the present invention, where the method in fig. 1 may include, but is not limited to, steps S110 to S190.
Step S110, receiving sampling data and caching the sampling data;
step S120, converting the sampling data into parallel data according to the reference index address and a preset reading rule;
Step S130, performing interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
step S140, performing timing error calculation on the interpolation filter data according to a preset timing error formula to generate a multi-path timing error result;
step S150, carrying out weighted calculation on the multipath timing error result according to a preset weighted calculation formula to generate a weighted timing error result;
step S160, loop filtering processing is carried out on the weighted timing error result according to a preset loop filtering formula, and an NCO step value is generated;
Step S170, updating a reference index address according to the NCO step value and a preset parameter updating formula;
Step S180, extracting the interpolation filtering data according to a preset extraction rule to generate extraction data;
Step S190, carrying out rate matching processing on the extracted data according to a preset rate matching rule, and outputting symbol synchronization data. In step S110 of some embodiments, sample data is received and buffered. In some embodiments, the data buffering module buffers the received data, and the buffered data is used for subsequent parallel symbol synchronization calculation. Minimum buffer length = symbol rate x oversampling multiple x parallel channel number. The proper value range of the over-sampling multiple is more than 2 and less than or equal to 4, and the default value is 4. If the over-sampling multiple is higher, the input data can be processed by downsampling once.
In step S120 of some embodiments, the sampled data is converted into parallel data according to the reference index address and a preset read rule. In some embodiments, the reference index address includes a numerically controlled oscillator NCO, N IF reference index addresses m k, where k=1, 2 … N IF, and a fractional interval μ k, where the preset reading rule is to read N IF sets of sampled data from the data buffer and output the sampled data to the interpolation filter module, where each set has IQ data with 4 sampling points, and the data is { x (m k-2),x(mk-1),x(mk),x(mk +1) }.
In step S130 of some embodiments, interpolation filtering processing is performed on the parallel data according to a preset interpolation filtering formula, so as to generate interpolation filtered data. The parallel data generated in step S120 is subjected to interpolation filtering processing using a second-order piecewise parabolic method and a cubic interpolation method. Thereby generating interpolation filtered data.
In step S140 of some embodiments, timing error calculation is performed on the interpolation filtered data according to a preset timing error formula, so as to generate a multi-path timing error result. In some embodiments, the timing error is calculated using a Gardner error detection algorithm. The algorithm requires 2 sampling points per symbol period, namely an optimal sampling point y (n) and a sampling point y (n-1/2) between the two optimal sampling points to calculate a first timing error e (n), and the first timing error is shown in a formula (1):
e (n) =e { y * (n-1/2) ×y (n) -y (n-1) ] } formula (1)
When BPSK or QPSK modulation is used, the first timing error calculation formula can be written as:
e(n)＝yI(n-1/2)*[yI(n)-yI(n-1)]+yQ(n-1/2)*[yQ(n)-yQ(n-1)] Formula (2)
Y I (n) and y Q (n) are values of two paths I, Q of the sampling point at the time of modulation.
In step S150 of some embodiments, the multi-path timing error result is weighted according to a preset weight calculation formula to generate a weighted timing error result. In some embodiments, because of the parallel symbol synchronization architecture, the timing error module uses the N IF data from the interpolation filter output to calculate N IF/2 timing error values. The first timing error value needs to be weighted and calculated, and a value is finally obtained and used as a second timing error value of the group of sampling points and is output to the loop filter. Common error weighting methods may use mean calculation methods or window function filtering methods.
In step S160 of some embodiments, loop filtering is performed on the weighted timing error result according to a preset loop filtering formula to generate an NCO step value. In some embodiments, the filtering is performed on the timing error result obtained by calculating the sampling data, so as to filter out jitter and high-frequency components of the timing error, and the filtered NCO step value is used to update the NCO step value ω (n) of the numerically controlled oscillator NCO in the interpolation controller. Loop filters typically use a second order filter and the NCO step value is calculated by a preset loop filter formula.
In step S170 of some embodiments, the reference index address is updated according to the NCO step value and the preset parameter update formula. In some embodiments, the reference index address is updated according to the NCO step value obtained in step S160 and the preset parameter updating formula, the step is subtracted from the stored value of the NCO at each sampling time, and when the value of the memory is less than 0, the value of the register is added with 1, and the NCO overflows once, and at this time, an interpolation calculation is needed. The updated data includes numerically controlled oscillator NCO, N IF reference index addresses m k, where k=1, 2 … N IF, and a fractional interval μ k, from which the reference index addresses are further updated.
In step S180 of some embodiments, the interpolation filter data is decimated according to a preset decimation rule to generate decimated data. In some embodiments, the predetermined decimation rule is to decimate the output sample data of the interpolation filter by a factor of 2. The sampling data output by the interpolation filter is sequentially extracted to obtain odd numbered sampling points, and the odd numbered sampling points are the optimal sampling points.
In step S190 of some embodiments, the decimated data is rate matched according to a preset rate matching rule, and symbol synchronization data is output. In some embodiments, the preset rate matching rule is to buffer and time sequence the multiple paths of data, perform rate conversion, and output according to a single symbol rate.
The embodiment of the invention provides a parallel symbol synchronization method, which comprises 3 functional modules: the system comprises a data buffer module, a parallel symbol synchronization module and a rate matching module, wherein the data buffer module is used for buffering input data, the parallel symbol synchronization module is used for carrying out multipath parallel signal processing on the data to be synchronized, the multipath parallel signal processing comprises interpolation filtering, timing error calculation, error weighting, loop filtering, parameter updating and the like, the rate matching module is used for carrying out buffer and rate matching processing on multipath optimal sampling points which are simultaneously output by the parallel symbol synchronization module, and the synchronized data is output according to the symbol rate required by the system. The parallel symbol synchronization method provided by the embodiment of the invention can solve the problem that the system working clock cannot be infinitely improved and the symbol cannot synchronously work when the ultra-high-speed signal receiving is carried out.
Referring to fig. 2, in some embodiments, step S120 may include, but is not limited to, steps S210 to S230;
Step S210, taking the sampling data of four sampling points as a group of sampling group data;
step S220, acquiring a plurality of groups of sampling group data according to the interpolation quantity in the reference index address;
step S230, the sample group data is converted into parallel data according to a preset reading rule.
Specifically, in step S210 of some embodiments, sampling data of four sampling points is taken as a set of sampling group data, and four sampling data is taken as a set; in step S220 of some embodiments, sets of sample set data are obtained based on the number of interpolations in the base index address where there are N IF base index addresses m k. N IF groups of data are sequentially read from the data cache, and each group of 4 sampling point data are sequentially read. In step S230 of some embodiments, sample group data is converted into parallel data according to preset read rules. In a parallel arrangement, N IF sets of data are sent to the first N IF channels of interpolation filtering for interpolation computation. The parallel symbol synchronization method provided by the embodiment of the steps of the invention can extract the sampling data and output the sampling data to the interpolation filter N IF channels for interpolation calculation in a parallel arrangement mode.
Referring to fig. 3, in some embodiments, step S130 may include, but is not limited to, steps S310 through S330;
Step S310, gating a plurality of interpolation filter channels according to the interpolation quantity;
step S320, inputting the parallel data into the interpolation filter channel correspondingly;
step S330, the parallel data is converted into interpolation filtering data according to a preset interpolation filtering formula.
Interpolation filtering is to perform interpolation fitting on data, and perform interpolation calculation by using adjacent 4 sampling data corresponding to the reference index provided by the read control module and the fractional interval mu k, specifically, in step S310 of some embodiments, a plurality of interpolation filtering channels are selected according to the interpolation number; the parallel interpolation filtering module adopts a parallel processing architecture, instantiates N IF interpolation filtering channels according to the interpolation quantity, and each channel adopts a Farrow structure and a pipeline mode. In step S320 of some embodiments, the parallel data is input to the interpolation filter path correspondingly; the parallel data is input to the N IF interpolation filter channels after the instantiation, and in step S330 of some embodiments, the parallel data is converted into interpolation filter data according to a preset interpolation filter formula. The preset interpolation filter is shown in formulas (3) and (4):
Where T s is the sample clock period, T n is the interpolated clock period, h IF (i) is the coefficient of the interpolation filter, x (m kTs) is the input of the interpolation filter, it is the sample value at a fixed sample interval T s, y (kT n) is the output of the filter, m k is the base point of the interpolation, and μ k is the fractional interval. The parallel data can be subjected to interpolation filtering processing by the parallel symbol synchronization method provided by the embodiment of the steps.
Referring to fig. 4, in some embodiments, step S160 may include, but is not limited to, steps S410 through S420;
step S410, filtering calculation is carried out on the weighted timing error result according to a preset loop filtering formula, and a filtering result is obtained;
Step S420, inputting the filtering result into a numerical control oscillator and performing stepping calculation to obtain an NCO stepping value.
Specifically, in step S410 of some embodiments, filtering calculation is performed on the weighted timing error result according to a preset loop filtering formula to obtain a filtering result; in some specific embodiments, filtering the timing error result obtained by calculating the sampling data to filter out jitter and high-frequency components of the timing error to obtain a filtering result; in step S420 of some embodiments, inputting the filtering result into the numerically controlled oscillator and performing step calculation to obtain an NCO step value; the filtering result is used to realize the update of the NCO step value omega (n) of the digital oscillator NCO in the interpolation controller. Loop filters typically use a second order filter, expressed as shown in equation (5):
ω (n) =ω (n-1) +c 1[e(n)-e(n-1)]+c2 e (n) formula (5)
Where c 1 and c 2 are configurable filter coefficients. If the term c 1 is removed, the filter becomes a first order loop filter. By the parallel symbol synchronization method provided by the embodiment of the above steps of the present invention, the error data for which timing error and weighting calculation have been performed can be subjected to filtering processing.
Referring to fig. 5, in some embodiments, step S170 may include, but is not limited to, steps S510 through S530;
Step S510, calculating an NCO stepping value according to a preset parameter updating formula to obtain an NCO phase value of the numerical control oscillator;
Step S520, transmitting NCO phase value of the numerical control oscillator to a reading control module;
step S530, updating the reference index address according to the NCO phase value of the numerical control oscillator.
Specifically, in step S510 of some embodiments, the NCO step value is calculated according to a preset parameter update formula, so as to obtain the NCO phase value of the numerically controlled oscillator; when serial symbol synchronization is performed, a preset parameter updating formula is used for calculating an NCO stepping value to obtain a numerical control oscillator NCO phase value, and numerical control oscillator NCO phase value updating comprises numerical control oscillator NCO and N IF reference index addresses m k, wherein k=1, 2 … N IF and a decimal interval mu k. First, a numerical control oscillator calculation formula is used, as shown in formula (6):
η (n+1) = [ η (n) - ω (n) ] mod (1) formula (6)
Where η (n) is the phase value of the current sample time of the NCO memory, ω (n) is the NCO step value, and η (n+1) is the phase value of the next sample point. The NCO range is [0,1]. The stored value of NCO at each sampling time is subtracted by a step, when the value of the memory is smaller than 0, the value of the register is added with 1, NCO overflows once, and interpolation calculation is needed at the moment. The symbol synchronization algorithm ensures that the corresponding output is the optimal sampling point or the middle point between the two optimal sampling points when the NCO is 0 by adjusting the step. Each time the NCO overflows, an interpolated fractional interval is calculated from the NCO memory current value and the step as shown in equation (7):
μ=η (n)/ω (n) formula (7)
When parallel symbol synchronization is implemented, the parameter updating module needs to calculate N IF reference index addresses m k and corresponding decimal intervals μ k needing interpolation in N B (N B＝NS*Nchan) samples in the current buffer module at a time. In a specific implementation, the range of NCO is modified to be [0, N B ], and the numerical control oscillator update formula is shown as formula (8):
η (n m+1)＝[η(nm)-ω(n)*m]mod(1) m＝1,2,…NB formula (8)
When the NCO memory value η (n m) is smaller than the step ω (n) ×m, it indicates that the NCO will overflow at the next time of the current sampling time, and interpolation calculation is needed at this time, the corresponding reference difference index m k is recorded as m, and the decimal interval μ k is calculated as shown in formula (9):
Mu k＝η(nm)/omega (n) formula (9)
From this, it can be derived that the numerically controlled oscillator NCO phase value contains the numerically controlled oscillator NCO, N IF reference index addresses m k, where k=1, 2 … N IF, and also the fractional interval μ k.
In step S520 of some embodiments, the numerically controlled oscillator NCO phase value is transmitted to a read control module; the calculated updated numerically controlled oscillator NCO phase value is transmitted to a read control module. In step S530 of some embodiments, updating the reference index address according to the numerically controlled oscillator NCO phase value; and updating the reference index address according to the calculated and updated NCO phase value of the numerical control oscillator.
Referring to fig. 6, in some embodiments, step S180 may include, but is not limited to, steps S610 through S640;
step S610, marking the interpolation filtering data with odd order as first data;
step S620, marking the interpolation filtered data in even order as second data;
Step S630, the second data is extracted;
step S640, the first data is selected to generate extraction data.
The symbol synchronization of the scheme of the invention is based on the Gardner algorithm, and two sampling points are needed in each symbol period, so that the output of the interpolation filtering module comprises an optimal sampling point and an intermediate sampling point between the two sampling points, the output sampling point data of the interpolation filter is required to be subjected to 2 times extraction operation, and the output interpolation filtering data is subjected to marking and extraction operation. In step S610 of some embodiments, the interpolation filtered data for the odd order is marked as first data. In step S620 of some embodiments, the interpolation filtered data for the even order is marked as second data. In step S630 of some embodiments, the second data is decimated, and the even order interpolation filtered data is decimated. In step S640 of some embodiments, the first data is selected, the decimated data is generated, and the interpolation filtered data of the odd order is selected.
Referring to FIG. 7, in some embodiments, step S190 may include, but is not limited to, steps S710 through S740
Step S710, caching the extracted data;
Step S720, adjusting the time sequence of the extracted data;
Step S730, converting the extracted data into symbol synchronization data according to a preset rate;
in step S740, symbol synchronization data is output.
In step S710 of some embodiments, the extracted data is cached, and the extracted data is cached first; in step S720 of some embodiments, the timing of the extracted data is adjusted, and since multiple paths of synchronized extracted data are output in parallel after each processing, the multiple paths of extracted data need to be processed in timing; in step S730 of some embodiments, the extracted data is converted into symbol synchronization data according to a preset rate, and the multiple paths of extracted data are converted into symbol synchronization data by performing the preset rate conversion; in step S740 of some embodiments, symbol synchronization data is output. The parallel symbol synchronization method provided by the embodiment of the invention can ensure that the output symbol synchronization data keep the same speed.
The embodiment of the invention also provides a parallel symbol synchronization device, which can realize the parallel symbol synchronization method, and the device comprises the following steps:
The data caching module is used for receiving the sampling data and caching the sampling data;
The reading control module is used for converting the sampling data into parallel data according to the reference index address and a preset reading rule;
The parallel interpolation filtering module is used for carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
the timing error calculation module is used for carrying out timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
The weighting calculation module is used for carrying out weighting calculation on the multipath timing error results according to a preset weighting calculation formula to generate weighted timing error results;
The loop filtering module is used for carrying out loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
the parameter updating module is used for updating the reference index address according to the NCO step value and a preset parameter updating formula;
The extraction module is used for carrying out extraction processing on the interpolation filtering data according to a preset extraction rule to generate extraction data;
and the rate matching module is used for carrying out rate matching processing on the extracted data according to a preset rate matching rule and outputting symbol synchronization data.
The specific implementation manner of the parallel symbol synchronization device in this embodiment is substantially identical to the specific implementation manner of the parallel symbol synchronization method described above, and will not be described herein.
Fig. 8 is a schematic diagram of a system architecture for performing a parallel symbol synchronization method according to an embodiment of the present invention. In the example of fig. 8, the system architecture includes a DBUF data buffer module 801, an RCTR read control module 802, a PIF parallel interpolation filter module 803, a CTE timing error calculation module 804, an ME weight calculation module 805, an LF loop filter module 806, a PUP parameter update module 807, a DD decimation module 808, and an RM rate matching module 809. The DBUF data buffer module 801 is connected to the RCTR read control module 802, the RCTR read control module 802 is connected to the PIF parallel interpolation filter module 803 and the PUP parameter update module 807, the PIF parallel interpolation filter module 803 is connected to the CTE timing error calculation module 804 and the DD extraction module 808, the CTE timing error calculation module 804 is connected to the ME weighting calculation module 805, the LF loop filter module 806 is connected to the PUP parameter update module 807, the PUP parameter update module 807 is connected to the RCTR read control module 802, and the DD extraction module 808 is connected to the RM rate matching module 809.
In some embodiments, the buffer module stores the input data when the input data valid signal i_symbol_vld is 1. The data buffer is realized by adopting a shift register mode, and the requirement that the subsequent calculation module can read the sampling data of the multi-bit address at one time to perform parallel operation can be met by adopting the shift register mode for storage.
In some embodiments, according to N IF reference index addresses m k calculated by the parameter updating module, where k=1, 2 … N IF, N IF sets of sample data are sequentially read from the data buffer, and each set of 4 sample point data is sent to the first N IF channels of interpolation filtering for interpolation calculation.
In some embodiments, the parallel interpolation filtering module adopts a parallel processing architecture to instantiate N chan interpolation filtering channels, and each channel adopts a Farrow structure and a pipeline mode to perform filtering calculation according to formulas (1) and (2). The read control module inputs N IF sets of sample group data each time, uses the first N IF channels to calculate, and uses the corresponding position 1 of the enable state register chan_en_state corresponding to the used channel, and uses the unused channel to correspond to the position 0.
In some embodiments, the timing error calculation module performs timing error calculation on N IF parallel data input each time according to formula (3), so as to obtain N IF/2 multipath timing error results.
In some embodiments, N IF/2 multipath timing error results from the timing error calculation are weighted, multiplied by a set of weighting coefficients. The weighting coefficient can be calculated and determined through simulation, and a register is used for storing the coefficient value in the FPGA, so that the calculation complexity is reduced.
In some embodiments, the loop filter performs a filtering calculation on the weighted timing error result of each input according to equation (5), and the output ω (n) of the filter can be used as a step parameter of the numerically controlled oscillator NCO for parameter update calculation of the next set of data.
In some embodiments, according to the input NCO step values, the reference index position m k of the N IF sets of data to be interpolated in the next set of cache data and the corresponding interpolation fractional interval parameter μ k of each set are calculated according to formulas (8) and (9), and output to the read control module and the interpolation calculation module to perform the reading and interpolation filtering operation of the next set of data.
In some embodiments, the interpolation filter data output in parallel by the interpolation filter module is marked and extracted. The first data output by normal operation of interpolation filtering starts with a1 for the odd order and a 0 for the even order. And outputting the data marked as 1, namely finishing the operation of 2 times of extraction.
In some embodiments, the decimation module works in parallel, and outputs N OUT pieces of optimal sampling point data each time, and since the number of points output each time is not fixed in parallel processing, N OUT is about N IF/2, the rate matching module needs to finish buffering the data input in parallel, adjust the time sequence, and output according to the symbol rate.
The embodiment of the disclosure also provides an electronic device, including:
At least one memory;
At least one processor;
at least one program;
The program is stored in the memory and the processor executes at least one program to implement the parallel symbol synchronization method of the present invention as described above. The electronic device can be any intelligent terminal including a mobile phone, a tablet Personal computer, a Personal digital assistant (PDA for short), a vehicle-mounted computer and the like.
Referring to fig. 9, fig. 9 illustrates a hardware structure of an electronic device according to another embodiment, the electronic device includes:
The processor 901 may be implemented by a general purpose CPU (Central ProcessingUnit ), a microprocessor, an application specific integrated circuit (ApplicationSpecificIntegratedCircuit, ASIC), or one or more integrated circuits, etc. for executing related programs to implement the technical solution provided by the embodiments of the present invention;
The memory 902 may be implemented in the form of a ROM (read only memory), a static storage device, a dynamic storage device, or a RAM (random access memory). The memory 902 may store an operating system and other application programs, and when the technical solutions provided in the embodiments of the present disclosure are implemented by software or firmware, relevant program codes are stored in the memory 902, and the processor 901 invokes a parallel symbol synchronization method for performing the embodiments of the present disclosure;
an input/output interface 903 for inputting and outputting information;
The communication interface 904 is configured to implement communication interaction between the device and other devices, and may implement communication in a wired manner (e.g. USB, network cable, etc.), or may implement communication in a wireless manner (e.g. mobile network, WIFI, bluetooth, etc.);
A bus 905 that transfers information between the various components of the device (e.g., the processor 901, the memory 902, the input/output interface 903, and the communication interface 904);
Wherein the processor 901, the memory 902, the input/output interface 903 and the communication interface 904 are communicatively coupled to each other within the device via a bus 905.
The disclosed embodiments also provide a storage medium that is a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the above-described parallel symbol synchronization method.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The embodiments described in the embodiments of the present invention are for more clearly describing the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention, and those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present invention are equally applicable to similar technical problems.
It will be appreciated by those skilled in the art that the solutions shown in fig. 1-7 are not limiting on the embodiments of the invention and may include more or fewer steps than shown, or certain steps may be combined, or different steps.
The above described apparatus embodiments are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Those of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
The terms "first," "second," "third," "fourth," and the like in the description of the application and in the above figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including multiple instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a magnetic disk, or an optical disk, or other various media capable of storing a program.
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and are not thereby limiting the scope of the claims of the embodiments of the present invention. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and spirit of the embodiments of the present invention shall fall within the scope of the claims of the embodiments of the present invention.
Claims (7)
1.A method of parallel symbol synchronization, comprising:
receiving sampling data of a plurality of sampling points in a clock, and caching the sampling data;
taking the sampling data of four sampling points as a group of sampling group data;
acquiring a plurality of groups of sampling group data according to the interpolation quantity in the reference index address;
Converting the sampling group data into parallel data according to a preset reading rule;
Performing interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
Performing timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
performing weighted calculation on the multipath timing error result according to a preset weighted calculation formula to generate a weighted timing error result;
Performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
updating the reference index address according to the NCO step value and a preset parameter updating formula;
Marking the interpolation filtered data in odd order as first data;
marking the interpolation filtered data of even order as second data;
Extracting the second data;
Selecting the first data to generate extraction data;
caching the extracted data;
Adjusting the time sequence of the extracted data;
Converting the extracted data into symbol synchronization data according to a preset rate;
and outputting the symbol synchronization data.
2. The parallel symbol synchronization method according to claim 1, wherein the performing interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtered data includes:
Gating a plurality of interpolation filter channels according to the interpolation quantity;
Correspondingly inputting the parallel data into an interpolation filtering channel;
and converting the parallel data into interpolation filtering data according to a preset interpolation filtering formula.
3. The parallel symbol synchronization method according to claim 2, wherein the loop filtering the weighted timing error result according to a preset loop filtering formula to generate an NCO step value includes:
performing filtering calculation on the weighted timing error result according to a preset loop filtering formula to obtain a filtering result;
And inputting the filtering result into a numerical control oscillator and performing stepping calculation to obtain the NCO stepping value.
4. The parallel symbol synchronization method of claim 3, wherein updating the reference index address according to the NCO step value and a preset parameter update formula comprises:
calculating the NCO stepping value according to a preset parameter updating formula to obtain the NCO phase value of the numerical control oscillator;
transmitting the NCO phase value of the numerical control oscillator to a reading control module;
and updating the reference index address according to the NCO phase value of the numerical control oscillator.
5. A parallel symbol synchronization apparatus, comprising:
the data caching module is used for receiving sampling data of a plurality of sampling points in one clock and caching the sampling data;
the reading control module is used for taking the sampling data of the four sampling points as a group of sampling group data; acquiring a plurality of groups of sampling group data according to the interpolation quantity in the reference index address; converting the sampling group data into parallel data according to a preset reading rule;
The parallel interpolation filtering module is used for carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
the timing error calculation module is used for carrying out timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
the weighting calculation module is used for carrying out weighting calculation on the multipath timing error results according to a preset weighting calculation formula to generate weighted timing error results;
The loop filtering module is used for carrying out loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
The parameter updating module is used for updating the reference index address according to the NCO step value and a preset parameter updating formula;
A decimation module for marking the interpolation filtered data in odd order as first data; marking the interpolation filtered data of even order as second data; extracting the second data; selecting the first data to generate extraction data;
The rate matching module is used for caching the extracted data; adjusting the time sequence of the extracted data; converting the extracted data into symbol synchronization data according to a preset rate; and outputting the symbol synchronization data.
6. An electronic device, comprising:
At least one memory;
At least one processor;
at least one program;
The program is stored in the memory, and the processor executes the at least one program to implement:
A parallel symbol synchronization method as claimed in any one of claims 1 to 4.
7. A storage medium that is a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions for causing a computer to perform:
A parallel symbol synchronization method as claimed in any one of claims 1 to 4.
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| US7340024B1 (en) * | 2003-10-22 | 2008-03-04 | L3 Communications Corporation | Parallel fractional interpolator with data-rate clock synchronization |
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