CN115347999A - Parallel symbol synchronization method and device, electronic equipment and storage medium - Google Patents
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Abstract
The embodiment of the invention provides a parallel symbol synchronization method and device, electronic equipment and a storage medium, which relate to the technical field of wireless communication and digital communication, and the method comprises the following steps: receiving and caching the sampled data, converting the sampled data into parallel data, performing interpolation filtering processing on the parallel data to generate interpolation filtering data, performing timing error calculation and weighting calculation on the interpolation filtering data to generate a multi-path timing error result and a weighting timing error result, performing loop filtering processing on the weighting timing error result to generate an NCO stepping value, processing the NCO stepping value, updating a reference index address, performing extraction processing and rate matching processing on the interpolation filtering data, and outputting symbol synchronization data. The method can accurately finish symbol synchronization work.
Description
Technical Field
The present invention relates to the field of wireless communication and digital communication technologies, and in particular, to a parallel symbol synchronization method and apparatus, an electronic device, and a storage medium.
Background
In the field of wireless communication and digital communication, the performance of a symbol synchronization algorithm and the quality of a realization framework directly influence the demodulation performance of a receiver and the stability of the whole system, the serial symbol synchronization algorithm in the prior art adopts an iterative computation mode and mainly carries out the steps of interpolation fitting, sampling error computation and low-pass filtering, and the last computation result is used in each step of computation, so that the delay of the serial symbol synchronization realization mode is larger, and when a super-high-speed signal is received, the working clock of the system cannot be infinitely increased, so that the symbol synchronization work cannot be accurately completed.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the invention provides a parallel symbol synchronization method and device, electronic equipment and a storage medium, which can greatly improve the processing capacity of symbol synchronization without causing performance loss and can realize ultrahigh-speed symbol synchronization.
To achieve the above object, a first aspect of an embodiment of the present invention provides a method, including:
receiving sampling data and caching the sampling data;
converting the sampling data into parallel data according to a reference index address and a preset reading rule;
carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
performing timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
performing weighted calculation on the multi-path timing error result according to a preset weighted calculation formula to generate a weighted timing error result;
performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
updating the reference index address according to the NCO stepping value and a preset parameter updating formula;
extracting the interpolation filtering data according to a preset extraction rule to generate extraction data;
and carrying out rate matching processing on the extracted data according to a rate matching rule, and outputting symbol synchronization data.
In some embodiments of the present invention, the converting the sample data into parallel data according to a reference index address and a preset reading rule includes:
taking the sampling data of four sampling points as a group of sampling group data;
acquiring a plurality of groups of the sampling group data according to the interpolation number in the reference index address;
and converting the sampling group data into parallel data according to a preset reading rule.
In some embodiments of the present invention, the performing interpolation filtering processing on the parallel data according to a preset interpolation filtering formula, and generating interpolation filtering data includes:
gating a plurality of interpolation filtering channels according to the interpolation quantity;
inputting the parallel data into an interpolation filtering channel correspondingly;
converting the parallel data into interpolation filtering data according to a preset interpolation filtering formula
In some embodiments of the present invention, the performing loop filtering on the weighted timing error result according to a preset loop filtering formula, and generating the NCO step value includes:
filtering and calculating the weighted timing error result according to a preset loop filtering formula to obtain a filtering result;
and inputting the filtering result into a numerical control oscillator and carrying out stepping calculation to obtain the NCO stepping value.
In some embodiments of the present invention, the updating the reference index address according to the NCO step value and a preset parameter update formula includes:
calculating the NCO stepping value according to a preset parameter updating formula to obtain an NCO phase value of the numerical control oscillator;
transmitting the numerically controlled oscillator NCO phase value to the read control module;
and updating the reference index address according to the NCO phase value of the numerical control oscillator.
In some embodiments of the present invention, the decimating the interpolation filtered data according to a preset decimation rule, and generating decimated data includes:
labeling the interpolation filtered data in odd order as first data;
marking the interpolation filtered data of even order as second data;
extracting the second data;
and selecting the first data to generate the extracted data.
In some embodiments of the present invention, the performing rate matching processing on the extracted data according to a rate matching rule, and outputting symbol synchronization data includes:
caching the extracted data;
adjusting the time sequence of the extracted data;
converting the extracted data into symbol synchronization data according to a preset rate;
and outputting the symbol synchronization data.
To achieve the above object, a second aspect of the embodiments of the present invention provides a parallel symbol synchronization apparatus, including:
the data caching module is used for receiving the sampling data and caching the sampling data;
the reading control module is used for converting the sampling data into parallel data according to a reference index address and a preset reading rule;
the parallel interpolation filtering module is used for carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
the timing error calculation module is used for calculating the timing error of the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
the weighted calculation module is used for carrying out weighted calculation on the multi-path timing error result according to a preset weighted calculation formula to generate a weighted timing error result;
the loop filtering module is used for performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
the parameter updating module is used for updating the reference index address according to the NCO stepping value and a preset parameter updating formula;
the extraction module is used for extracting the interpolation filtering data according to a preset extraction rule to generate extraction data;
and the rate matching module is used for carrying out rate matching processing on the extracted data according to a rate matching rule and outputting symbol synchronization data.
In order to achieve the above object, a third aspect of an embodiment of the present invention provides an electronic device, including:
at least one memory;
at least one processor;
at least one program;
the programs are stored in a memory, and a processor executes the at least one program to implement:
the parallel symbol synchronization method of the first aspect as described above.
To achieve the above object, a fourth aspect of the present invention proposes a storage medium which is a computer-readable storage medium storing computer-executable instructions for causing a computer to execute:
the parallel symbol synchronization method of the first aspect as described above.
The embodiment of the invention provides a parallel symbol synchronization method and device, electronic equipment and a storage medium, wherein sampling data are received and cached, and the sampling data are converted into parallel data according to a reference index address and a preset reading rule; then, carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data; performing timing error calculation on the interpolated filtering data according to a preset timing error formula to generate a multi-path timing error result; performing weighted calculation on the multi-path timing error result according to a preset weighted calculation formula to generate a weighted timing error result; performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value; updating a formula according to the NCO stepping value and a preset parameter, and updating a reference index address; extracting the interpolation filtering data according to a preset extraction rule to generate extraction data; and carrying out rate matching processing on the extracted data according to a preset rate matching rule, and outputting symbol synchronization data. Therefore, the problems that the system working clock can not be infinitely improved and the symbols can not work synchronously when signals are received at ultrahigh speed can be solved, and the accuracy of completing symbol synchronization can be effectively improved through the method and the device.
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The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a flow chart of a parallel symbol synchronization method provided by an embodiment of the present invention;
FIG. 2 is a flowchart of a parallel symbol synchronization method provided by one embodiment of step S120 in FIG. 1;
FIG. 3 is a flowchart of a parallel symbol synchronization method provided by one embodiment of step S130 in FIG. 1;
FIG. 4 is a flowchart of a parallel symbol synchronization method provided by one embodiment of step S160 in FIG. 1;
FIG. 5 is a flowchart of a parallel symbol synchronization method provided by one embodiment of step S170 in FIG. 1;
FIG. 6 is a flowchart of a parallel symbol synchronization method provided by one embodiment of step S180 in FIG. 1;
FIG. 7 is a flowchart of a parallel symbol synchronization method provided by one embodiment of step S190 in FIG. 1;
FIG. 8 is a diagram illustrating a system architecture of a parallel symbol synchronization method according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the description to first and second is only used for distinguishing technical features, the description should not be interpreted as indicating or implying any relative importance or implying any number of indicated technical features or implying any order of indicated technical features.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
The embodiment of the invention provides a parallel symbol synchronization method and device, electronic equipment and a storage medium, wherein sampling data are received and buffered, symbol synchronization based on a Gardner algorithm generally needs to be sequentially processed by interpolation filtering, timing error estimation, loop filtering, a numerical control oscillator and the like, and fixed processing delay is needed when the symbol synchronization is realized. When the ultrahigh-speed symbol rate is faced, each clock can receive 1 or more sampling data, the symbol synchronization module can meet the synchronization work of the ultrahigh-speed symbol rate only by adopting a parallel processing mode, and the sampling data are converted into parallel data according to a reference index address and a preset reading rule; then, carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data; performing timing error calculation on the interpolated filtering data according to a preset timing error formula to generate a multi-path timing error result; performing weighted calculation on the multi-path timing error result according to a preset weighted calculation formula to generate a weighted timing error result; performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value; updating a reference index address according to an NCO stepping value and a preset parameter updating formula; extracting the interpolation filtering data according to a preset extraction rule to generate extraction data; and carrying out rate matching processing on the extracted data according to a preset rate matching rule, and outputting symbol synchronization data. Therefore, the problems that the system working clock can not be infinitely increased and the symbols can not work synchronously when signals are received at ultrahigh speed can be solved, and the symbol synchronization can be accurately finished through the method and the device.
It should be noted that an NCO (numerically controlled oscillator) is an important component of a software radio, a Direct Digital Synthesizer (DDS), a Fast Fourier Transform (FFT), etc., and is also one of the main factors determining the performance of the NCO, and is used for generating a controllable sine wave or cosine wave. Along with the improvement of the integration level of the chip, the chip is more and more widely applied to the fields of signal processing, digital communication, modulation and demodulation, variable frequency speed regulation, guidance control, power electronics and the like.
The embodiments of the present invention will be further explained with reference to the drawings.
Fig. 1 is an alternative flowchart of a parallel symbol synchronization method according to an embodiment of the present invention, where the method in fig. 1 may include, but is not limited to, steps S110 to S190.
Step S110, receiving sampling data and caching the sampling data;
step S120, converting the sampling data into parallel data according to the reference index address and a preset reading rule;
step S130, carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
step S140, performing timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
step S150, performing weighted calculation on the multi-path timing error result according to a preset weighted calculation formula to generate a weighted timing error result;
step S160, performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
step S170, updating a formula according to the NCO stepping value and a preset parameter, and updating a reference index address;
step S180, extracting the interpolation filtering data according to a preset extraction rule to generate extraction data;
and step S190, carrying out rate matching processing on the extracted data according to a preset rate matching rule, and outputting symbol synchronization data. In step S110 of some embodiments, sample data is received and buffered. In some embodiments, the data buffering module buffers the received data, and the buffered data is used for subsequent parallel symbol synchronization calculation. Minimum buffer length = symbol rate oversampling multiple parallel channel number. The oversampling multiple suitably ranges from greater than 2 to equal to or less than 4, and is 4 by default. If the oversampling multiple is higher, the input data can be firstly processed by one-time downsampling.
In step S120 of some embodiments, the sample data is converted into parallel data according to the reference index address and a preset reading rule. In some embodiments, the reference index address comprises a numerically controlled oscillator NCO, N IF A base index address m k Wherein k =1,2 \8230N IF Also fractional spacing mu k The preset reading rule is to read N from the data cache IF Group sampling data and outputting to interpolation filter module, each group has 4 samplingIQ data of a sample point, the data being { x (m) k -2),x(m k -1),x(m k ),x(m k +1)}。
In step S130 of some embodiments, the parallel data is processed by interpolation filtering according to a preset interpolation filtering formula to generate interpolation filtering data. The parallel data generated in step S120 is subjected to interpolation filtering processing using a second-order piecewise parabolic method and a cubic interpolation method. Thereby generating interpolated filtered data.
In step S140 of some embodiments, the interpolated filtered data is subjected to timing error calculation according to a preset timing error formula, so as to generate a multi-path timing error result. In some embodiments, a Gardner error detection algorithm is used to calculate the timing error. The algorithm needs 2 sampling points in each symbol period, namely an optimal sampling point y (n) and a sampling point y (n-1/2) between the two optimal sampling points to calculate a first timing error e (n), and formula (1) shows:
e(n)＝e{y * (n-1/2)*[y(n)-y(n-1)]equation (1)
When using BPSK or QPSK modulation, the first timing error calculation formula can be written as:
e(n)＝y I (n-1/2)*[y I (n)-y I (n-1)]+y Q (n-1/2)*[y Q (n)-y Q (n-1)]formula (2)
y I (n) and y Q And (n) is the value of the two paths of I and Q of the sampling point during modulation.
In step S150 of some embodiments, the multipath timing error results are weighted according to a preset weighting calculation formula, so as to generate weighted timing error results. In some embodiments, the timing error module uses N of the interpolated filtered output due to the parallel symbol synchronization architecture IF Calculating to obtain N IF 2 timing error values. The first timing error value is weighted to obtain a value as a second timing error value of the group of sampling points, and the value is output to the loop filter. The commonly used error weighting method can use a mean calculation method or a window function filtering method.
In step S160 of some embodiments, the weighted timing error result is loop-filtered according to a preset loop-filtering formula to generate an NCO step value. In some embodiments, the timing error result obtained by calculating the sampling data is filtered to filter out jitter and high-frequency components of the timing error, and the filtered NCO step value is used to update the NCO step value ω (n) of the numerically-controlled oscillator NCO in the interpolation controller. The loop filter usually uses a second-order filter, and the NCO step value is calculated by a preset loop filtering formula.
In step S170 of some embodiments, the reference index address is updated according to the NCO step value and the preset parameter update formula. In some embodiments, the base index address is updated according to the NCO step value obtained in step S160 and the preset parameter update formula, the step is subtracted from the stored value of the NCO at each sampling time, and when the value of the memory is less than 0, the NCO is added by 1 and overflows once, and at this time, an interpolation calculation is required. The updated data includes numerically controlled oscillator NCO, N IF A base index address m k Wherein k =1,2 \ 8230n IF Also fractional intervals of μ k The base index address is further updated by the above data.
In step S180 of some embodiments, the interpolation filter data is decimated according to a preset decimation rule, so as to generate decimated data. In some embodiments, the predetermined decimation rule is to perform a decimation operation by 2 times on the output sample data of the interpolation filter. Sampling data output by the interpolation filter is extracted in sequence to output odd-numbered sampling points, and the output is the optimal sampling point.
In step S190 of some embodiments, the extracted data is subjected to rate matching according to a preset rate matching rule, and symbol synchronization data is output. In some embodiments, the preset rate matching rule is to perform buffering and timing processing on multiple paths of data, perform rate conversion, and output the data at a single symbol rate.
The embodiment of the invention provides a parallel symbol synchronization method, which comprises 3 functional modules: the system comprises a data caching module, a parallel symbol synchronization and rate matching module, wherein the data caching module is used for caching input data, the parallel symbol synchronization module is used for carrying out multi-channel parallel signal processing on the data to be synchronized, the multi-channel parallel signal processing comprises interpolation filtering, timing error calculation, error weighting, loop filtering, parameter updating and the like, the rate matching module is used for caching and rate matching multi-channel optimal sampling points output by the parallel symbol synchronization module at the same time, and the synchronized data are output according to a symbol rate required by the system. The parallel symbol synchronization method provided by the embodiment of the steps can solve the problems that the system working clock can not be infinitely increased and the symbols can not work synchronously when signals are received at ultrahigh speed, and can accurately complete symbol synchronization work.
Referring to fig. 2, in some embodiments, step S120 may include, but is not limited to including, steps S210 to S230;
step S210, taking the sampling data of the four sampling points as a group of sampling group data;
step S220, acquiring a plurality of groups of sampling group data according to the interpolation number in the reference index address;
in step S230, the sampling group data is converted into parallel data according to a preset reading rule.
Specifically, in step S210 of some embodiments, the sampling data of four sampling points is taken as a group of sampling group data, and the sampling data of four sampling points is taken as a group; in step S220 of some embodiments, sets of sample group data are obtained according to the interpolation number in the reference index address, where there is N IF A base index address m k . Sequentially reading N from data cache IF Group data, 4 sample points data per group. In step S230 of some embodiments, the sample group data is converted into parallel data according to a preset reading rule. In a regular way of parallel arrangement, N is IF Group data sending to the first N of interpolation filtering IF Each channel performs an interpolation calculation. Through the parallel symbol synchronization method provided by the embodiment of the steps above, the sampling data can be extracted and output to the interpolation filter N in a parallel arrangement mode IF Each channel performs an interpolation calculation.
Referring to fig. 3, in some embodiments, step S130 may include, but is not limited to including, steps S310 to S330;
step S310, a plurality of interpolation filtering channels are gated according to the interpolation quantity;
step S320, inputting the parallel data into the interpolation filtering channel correspondingly;
step S330, converting the parallel data into interpolation filtering data according to a preset interpolation filtering formula.
The interpolation filtering is to perform interpolation fitting on the data, and the adjacent 4 sample data and decimal interval mu corresponding to the reference index provided by the reading control module are used k Performing interpolation calculation, specifically, in step S310 of some embodiments, gating several interpolation filtering channels according to the number of interpolations; the parallel interpolation filtering module adopts a parallel processing architecture and instantiates N according to the interpolation number IF And each interpolation filtering channel adopts a Farrow structure and a pipeline mode. In step S320 of some embodiments, the parallel data is correspondingly input to the interpolation filtering channel; instantiating parallel data corresponding input IF In some embodiments, in step S330, the parallel data is converted into interpolation filtering data according to a predetermined interpolation filtering formula. The preset interpolation filtering is as shown in equations (3) and (4):
wherein, T s Is the sampling clock period, T n Is the interpolated clock period, h IF (i) Is the coefficient of the interpolation filter, x (m) k T s ) Is the input of an interpolation filter, which is at a fixed sampling interval T s Sampled value of (c), y (kT) n ) Is the output of the filter, m k Is the base point of the interpolation, mu k Are decimal intervals. Parallel symbol synchronization method provided by embodiments of the above steps of the present inventionIn this way, the parallel data may be subjected to interpolation filtering processing.
Referring to fig. 4, in some embodiments, step S160 may include, but is not limited to including, steps S410 to S420;
step S410, filtering calculation is carried out on the weighted timing error result according to a preset loop filtering formula, and a filtering result is obtained;
and step S420, inputting the filtering result into the numerical control oscillator and performing step calculation to obtain an NCO step value.
Specifically, in step S410 of some embodiments, the weighted timing error result is filtered according to a preset loop filtering formula to obtain a filtering result; in some embodiments, the filtering result is obtained by filtering out jitter and high frequency components of the timing error by filtering the timing error result obtained by calculating the sampling data; in step S420 of some embodiments, the filtering result is input to the digital controlled oscillator and step calculation is performed to obtain an NCO step value; the filter result is used to update the NCO step value ω (n) of the numerically controlled oscillator NCO in the interpolation controller. The loop filter usually uses a second-order filter, and the expression is shown in formula (5):
ω(n)＝ω(n-1)+c 1 [e(n)-e(n-1)]+c 2 e (n) formula (5)
Wherein c is 1 And c 2 Are configurable filter coefficients. If c is removed 1 The filter then becomes a first order loop filter. By the parallel symbol synchronization method provided by the embodiment of the above steps of the invention, filtering processing can be performed on error data which is subjected to timing error and weighting calculation.
Referring to FIG. 5, in some embodiments, step S170 may include, but is not limited to including, steps S510 through S530;
step S510, calculating an NCO stepping value according to a preset parameter updating formula to obtain an NCO phase value of a numerically-controlled oscillator;
step S520, transmitting the phase value of the NCO of the numerical control oscillator to a reading control module;
step S530, the reference index address is updated according to the NCO phase value of the numerical control oscillator.
Specifically, in step S510 in some embodiments, an NCO step value is calculated according to a preset parameter update formula, so as to obtain an NCO phase value of the numerically controlled oscillator; when serial symbol synchronization is carried out, the NCO stepping value is calculated by using a preset parameter updating formula to obtain the NCO phase value of the numerical control oscillator, and the updating of the NCO phase value of the numerical control oscillator comprises the NCO and N of the numerical control oscillator IF A base index address m k Wherein k =1,2 \ 8230n IF Also fractional intervals of μ k . First, using a numerically controlled oscillator calculation formula, as shown in formula (6):
η (n + 1) = [ η (n) - ω (n) ] mod (1) formula (6)
Where η (n) is the phase value of the NCO memory at the current sampling instant, ω (n) is the NCO step value, and η (n + 1) is the phase value of the next sampling point. The NCO range is [0,1]. The step is subtracted from the value stored in the NCO at each sampling moment, when the value of the memory is less than 0, the value of the register is added with 1, the NCO overflows once, and at the moment, interpolation calculation needs to be carried out. The symbol synchronization algorithm ensures that the corresponding output is the optimal sampling point or the intermediate point between two optimal sampling points when the NCO is 0 by adjusting the stepping. Every time the NCO overflows, the interpolated decimal interval is derived from the NCO memory current value and the step calculation, as shown in equation (7):
μ = η (n)/ω (n) formula (7)
When the parallel symbol synchronization is realized, the parameter updating module needs to calculate N in the current cache module at a time B A (N) B ＝N S *N chan ) N present in a sample requiring interpolation IF A base index address m k And its corresponding fractional interval mu k . In a specific implementation, the NCO range is modified to [0,N' B ]The numerical control oscillator update formula is shown as formula (8):
η(n m+1 )＝[η(n m )-ω(n)*m]mod(1) m＝1,2,…N B formula (8)
When NCO memory value eta (n) m ) When the sampling time is less than the step omega (n) m, the NCO at the next moment which represents the current sampling moment overflows, at the moment, interpolation calculation needs to be carried out, and the corresponding NCOReference difference index m k Notation m, fractional interval μ k The calculation formula is shown in formula (9):
μ k ＝η(n m ) Formula (/ ω (n) (9))
The numerical control oscillator NCO phase value can be obtained by the method, and comprises numerical control oscillator NCO, N IF A base index address m k Wherein k =1,2 \ 8230n IF Also fractional intervals of μ k 。
In step S520 of some embodiments, the numerically controlled oscillator NCO phase value is transmitted to the read control module; and transmitting the calculated and updated numerical control oscillator NCO phase value to a reading control module. In step S530 of some embodiments, the reference index address is updated according to the numerically controlled oscillator NCO phase value; and updating the reference index address according to the numerically-controlled oscillator NCO phase value updated by calculation.
Referring to fig. 6, in some embodiments, step S180 may include, but is not limited to including, steps S610 through S640;
step S610, the interpolation filtering data in odd order is marked as first data;
step S620, mark the interpolation filtering data of even order as the second data;
step S630, extracting the second data;
in step S640, the first data is selected and extracted to generate extracted data.
The symbol synchronization of the scheme of the invention is based on the Gardner algorithm, each symbol period needs two sampling points, so the output of the interpolation filtering module comprises the optimal sampling point and the intermediate sampling point between the two sampling points, 2 times of extraction operation needs to be carried out on the output sampling point data of the interpolation filter, and the marking and extraction operation is carried out on the output interpolation filtering data. In step S610 of some embodiments, the odd-order interpolated filtered data is marked as first data. In step S620 of some embodiments, the even-order interpolated filtered data is marked as second data. In step S630 of some embodiments, the second data is decimated, and the even-order interpolated filtered data is decimated. In step S640 of some embodiments, the first data is selected out, decimated data is generated, and odd-order interpolated filtered data is selected out.
Referring to FIG. 7, in some embodiments, step S190 may include, but is not limited to including, steps S710-S740
Step S710, caching the extracted data;
step S720, adjusting the timing sequence of the extracted data;
step S730, converting the extracted data into symbol synchronization data according to a preset rate;
and step S740, outputting the symbol synchronization data.
In step S710 in some embodiments, the data is cached and extracted, and the extracted data is cached first; in step S720 of some embodiments, the timing of the extracted data is adjusted, and since multiple paths of the extracted data after synchronization are output in parallel after each processing, the multiple paths of the extracted data need to be subjected to timing processing; in step S730 of some embodiments, the extracted data is converted into symbol synchronization data according to a preset rate, and the multi-channel extracted data is converted into symbol synchronization data by performing preset rate conversion; in step S740 of some embodiments, symbol synchronization data is output. The parallel symbol synchronization method provided by the embodiment of the above steps of the invention can keep the consistent rate of the output symbol synchronization data.
The embodiment of the invention also provides a parallel symbol synchronization device, which can realize the parallel symbol synchronization method, and the device comprises:
the data caching module is used for receiving the sampled data and caching the sampled data;
the reading control module is used for converting the sampling data into parallel data according to the reference index address and a preset reading rule;
the parallel interpolation filtering module is used for carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
the timing error calculation module is used for calculating the timing error of the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
the weighted calculation module is used for carrying out weighted calculation on the multi-path timing error result according to a preset weighted calculation formula to generate a weighted timing error result;
the loop filtering module is used for performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
the parameter updating module is used for updating the reference index address according to the NCO stepping value and a preset parameter updating formula;
the extraction module is used for extracting the interpolation filtering data according to a preset extraction rule to generate extraction data;
and the rate matching module is used for carrying out rate matching processing on the extracted data according to a preset rate matching rule and outputting symbol synchronization data.
The specific implementation of the parallel symbol synchronization apparatus of this embodiment is substantially the same as the specific implementation of the parallel symbol synchronization method, and is not described herein again.
As shown in fig. 8, fig. 8 is a schematic diagram of a system architecture for performing a parallel symbol synchronization method according to an embodiment of the present invention. In the example of fig. 8, the system architecture includes a DBUF data caching module 801, an RCTR read control module 802, a PIF parallel interpolation filtering module 803, a CTE timing error calculation module 804, an ME weighting calculation module 805, an LF loop filtering module 806, a PUP parameter update module 807, a DD decimation module 808, and an RM rate matching module 809. The DBUF data caching module 801 is connected to the RCTR reading control module 802, the RCTR reading control module 802 is connected to the PIF parallel interpolation filtering module 803 and the PUP parameter updating module 807, the PIF parallel interpolation filtering module 803 is connected to the CTE timing error calculation module 804 and the DD extraction module 808, the CTE timing error calculation module 804 is connected to the ME weighting calculation module 805, the LF loop filtering module 806 is connected to the PUP parameter updating module 807, the PUP parameter updating module 807 is connected to the RCTR reading control module 802, and the DD extraction module 808 is connected to the RM rate matching module 809.
In some embodiments, when the input data valid signal I _ symb _ vld is 1, the buffer module stores the input data. The data cache is realized by adopting a shift register mode, and the requirement that a subsequent computing module can read sampling data of a multi-bit address at one time for parallel operation can be met by adopting the shift register mode for storage.
In some embodiments, N is calculated according to the parameter update module IF A base index address m k Wherein k =1,2 \ 8230n IF Sequentially reading N from the data cache IF Groups of sample data, 4 sample points per group, are sent to the first N of the interpolation filters IF Each channel performs an interpolation calculation.
In some embodiments, the parallel interpolation filter module employs a parallel processing architecture, instantiating N chan And each interpolation filtering channel adopts a Farrow structure and a pipeline mode and carries out filtering calculation according to the formulas (1) and (2). Each time the reading control module inputs N IF Group sample group data, N before use IF Each channel is calculated, and the corresponding position 1 of the enable status register chan _ en _ state of the used channel and the corresponding position 0 of the unused channel are calculated.
In some embodiments, the timing error calculation module calculates N for each input IF The parallel data is calculated according to the formula (3) to obtain N IF 2 multipath timing error results.
In some embodiments, N is calculated for timing error IF The/2 multipath timing error results are weighted and multiplied by a set of weighting coefficients. The weighting coefficients can be calculated and determined through simulation, and the coefficient values are stored in a register in the FPGA, so that the calculation complexity is reduced.
In some embodiments, the loop filter performs filtering calculation according to equation (5) on the weighted timing error result of each input, and the output ω (n) of the filter can be used as the step parameter of the numerically controlled oscillator NCO for the parameter update calculation of the next set of data.
In some embodiments, based on the input NCO step value, the next set of buffered data to be interpolated N is calculated according to equations (8) and (9) IF Reference index position m of group data k And each group of corresponding innerFractional insertion interval parameter mu k And the data are output to a reading control module and an interpolation calculation module to carry out reading and interpolation filtering operations of the next group of data.
In some embodiments, the interpolation filter data output in parallel by the interpolation filter module is subjected to a marking and extraction operation. The first data output from normal operation is interpolated and filtered, with odd numbered ones being labeled 1 and even numbered ones being labeled 0. And outputting the data marked as 1, namely completing the operation of 2 times of extraction.
In some embodiments, the decimation module operates in parallel, outputting N at a time OUT The number of output points per time of parallel processing is not fixed, N OUT Is about N IF And about/2, the rate matching module needs to buffer the data input in parallel, adjust the time sequence and output the data according to the symbol rate.
An embodiment of the present disclosure further provides an electronic device, including:
at least one memory;
at least one processor;
at least one program;
programs are stored in the memory and the processor executes at least one of the programs to implement the parallel symbol synchronization method of the present invention as described above. The electronic device can be any intelligent terminal including a mobile phone, a tablet computer, a Personal Digital Assistant (PDA for short), a vehicle-mounted computer and the like.
Referring to fig. 9, fig. 9 illustrates a hardware structure of an electronic device according to another embodiment, where the electronic device includes:
the processor 901 may be implemented by a general-purpose CPU (Central processing unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits, and is configured to execute a relevant program to implement the technical solution provided in the embodiment of the present invention;
the memory 902 may be implemented in a ROM (read only memory), a static memory device, a dynamic memory device, or a RAM (random access memory). The memory 902 may store an operating system and other application programs, and when the technical solution provided by the embodiments of the present disclosure is implemented by software or firmware, the relevant program codes are stored in the memory 902 and called by the processor 901 to execute the parallel symbol synchronization method according to the embodiments of the present disclosure;
an input/output interface 903 for implementing information input and output;
a communication interface 904, configured to implement communication interaction between the device and another device, where communication may be implemented in a wired manner (e.g., USB, network cable, etc.), and communication may also be implemented in a wireless manner (e.g., mobile network, WIFI, bluetooth, etc.);
a bus 905 that transfers information between various components of the device (e.g., the processor 901, memory 902, input/output interface 903, and communication interface 904);
wherein the processor 901, the memory 902, the input/output interface 903 and the communication interface 904 enable a communication connection within the device with each other through a bus 905.
The embodiment of the present disclosure also provides a storage medium, which is a computer-readable storage medium, and the computer-readable storage medium stores computer-executable instructions, which are used to make a computer execute the parallel symbol synchronization method.
The memory, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. Further, the memory may include high speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and these remote memories may be connected to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The embodiment described in the embodiment of the present invention is for more clearly illustrating the technical solution of the embodiment of the present invention, and does not constitute a limitation to the technical solution provided in the embodiment of the present invention, and it is known to a person skilled in the art that, with the evolution of the technology and the occurrence of a new application scenario, the technical solution provided in the embodiment of the present invention is also applicable to similar technical problems.
It will be appreciated by those skilled in the art that the solutions shown in fig. 1 to 7 do not constitute a limitation of the embodiments of the present invention, and may include more or less steps than those shown, or combine some steps, or different steps.
The above described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, may be located in one place, or may be distributed over a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
One of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
The terms "first," "second," "third," "fourth," and the like in the description of the application and the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes multiple instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing programs, such as a usb disk, a portable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and the scope of the embodiments of the present invention is not limited thereby. Any modifications, equivalents and improvements that may occur to those skilled in the art without departing from the scope and spirit of the embodiments of the present invention are intended to be within the scope of the claims of the embodiments of the present invention.
Claims (10)
1. A method for parallel symbol synchronization, comprising:
receiving sampling data and caching the sampling data;
converting the sampling data into parallel data according to a reference index address and a preset reading rule;
carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
performing timing error calculation on the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
performing weighted calculation on the multi-path timing error result according to a preset weighted calculation formula to generate a weighted timing error result;
performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
updating the reference index address according to the NCO stepping value and a preset parameter updating formula;
extracting the interpolation filtering data according to a preset extraction rule to generate extraction data;
and carrying out rate matching processing on the extracted data according to a preset rate matching rule, and outputting symbol synchronization data.
2. The parallel symbol synchronization method according to claim 1, wherein said converting the sampled data into parallel data according to a reference index address and a preset reading rule comprises:
taking the sampling data of four sampling points as a group of sampling group data;
acquiring a plurality of groups of the sampling group data according to the interpolation number in the reference index address;
and converting the sampling group data into parallel data according to a preset reading rule.
3. The method for synchronizing parallel symbols according to claim 2, wherein said performing interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtered data comprises:
gating a plurality of interpolation filtering channels according to the interpolation quantity;
inputting the parallel data into an interpolation filtering channel correspondingly;
and converting the parallel data into interpolation filtering data according to a preset interpolation filtering formula.
4. The method for parallel symbol synchronization according to claim 3, wherein said performing loop filtering on the weighted timing error result according to a preset loop filtering formula to generate an NCO step value comprises:
filtering calculation is carried out on the weighted timing error result according to a preset loop filtering formula, and a filtering result is obtained;
and inputting the filtering result into a numerically controlled oscillator and performing step calculation to obtain the NCO step value.
5. The method for parallel symbol synchronization according to claim 4, wherein the updating the reference index address according to the NCO step value and a predetermined parameter updating formula comprises:
calculating the NCO stepping value according to a preset parameter updating formula to obtain an NCO phase value of the numerical control oscillator;
transmitting the numerically controlled oscillator NCO phase value to a reading control module;
and updating the reference index address according to the NCO phase value of the numerical control oscillator.
6. The method for parallel symbol synchronization according to claim 5, wherein said decimating the interpolated filtered data according to a preset decimation rule to generate decimated data comprises:
labeling the interpolation filtered data of odd order as first data;
marking the interpolation filtered data of even order as second data;
extracting the second data;
and selecting the first data to generate the extracted data.
7. The method for parallel symbol synchronization according to claim 6, wherein said performing rate matching processing on said extracted data according to a preset rate matching rule and outputting symbol synchronization data comprises:
caching the extracted data;
adjusting the time sequence of the extracted data;
converting the extracted data into symbol synchronization data according to a preset rate;
and outputting the symbol synchronization data.
8. A parallel symbol synchronization apparatus, comprising:
the data caching module is used for receiving the sampling data and caching the sampling data;
the reading control module is used for converting the sampling data into parallel data according to a reference index address and a preset reading rule;
the parallel interpolation filtering module is used for carrying out interpolation filtering processing on the parallel data according to a preset interpolation filtering formula to generate interpolation filtering data;
the timing error calculation module is used for calculating the timing error of the interpolation filtering data according to a preset timing error formula to generate a multi-path timing error result;
the weighting calculation module is used for performing weighting calculation on the multipath timing error results according to a preset weighting calculation formula to generate weighted timing error results;
the loop filtering module is used for performing loop filtering processing on the weighted timing error result according to a preset loop filtering formula to generate an NCO stepping value;
the parameter updating module is used for updating the reference index address according to the NCO stepping value and a preset parameter updating formula;
the extraction module is used for extracting the interpolation filtering data according to a preset extraction rule to generate extraction data;
and the rate matching module is used for carrying out rate matching processing on the extracted data according to a preset rate matching rule and outputting symbol synchronization data.
9. An electronic device, comprising:
at least one memory;
at least one processor;
at least one program;
the programs are stored in a memory, and a processor executes the at least one program to implement:
the parallel symbol synchronization method of any of claims 1 to 7.
10. A storage medium that is a computer-readable storage medium having stored thereon computer-executable instructions for causing a computer to perform:
the parallel symbol synchronization method of any one of claims 1 to 7.
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| US7340024B1 (en) * | 2003-10-22 | 2008-03-04 | L3 Communications Corporation | Parallel fractional interpolator with data-rate clock synchronization |
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