JPS6066546A - Synchronous general optimum receiver of noise following-up type - Google Patents

Synchronous general optimum receiver of noise following-up type

Info

Publication number
JPS6066546A
JPS6066546A JP17469383A JP17469383A JPS6066546A JP S6066546 A JPS6066546 A JP S6066546A JP 17469383 A JP17469383 A JP 17469383A JP 17469383 A JP17469383 A JP 17469383A JP S6066546 A JPS6066546 A JP S6066546A
Authority
JP
Japan
Prior art keywords
function
circuit
data
function table
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17469383A
Other languages
Japanese (ja)
Other versions
JPH042027B2 (en
Inventor
Toshihiko Namekawa
滑川 敏彦
Norihiko Morinaga
森永 規彦
Kenji Yamauchi
健次 山内
Nobuo Yasuda
信夫 安田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP17469383A priority Critical patent/JPS6066546A/en
Publication of JPS6066546A publication Critical patent/JPS6066546A/en
Publication of JPH042027B2 publication Critical patent/JPH042027B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To realize a high-reliability demodulating operation by performing the generating processing of a function table in parallel with the demodulating operation and updating the function table used for the demodulating operation to a new table when this processing is completed and performing the maximum likelihood test on a basis of functional data matched to the latest noise state. CONSTITUTION:The output of a subtracting circuit 7 and demodulated data RD outputted from an output discriminating circuit 11 are read into a CPU12, and the CPU12 measures and analyzes a receiving noise state for a certain time on a basis of them. Simultaneously, a new function table matched to this noise state is generated in another function table memory 9b which is not used for the demodulating operation. When a series of analysis and measurement of the noise state and the generation processing of the function table are completed, the CPU12 switches bus switching circuits 8 and 10 simultaneously. Then, the function table memory 9b is connected to the subtracting circuit 7 and the output discriminating circuit 11, and hereafter, the maximum likelihood test is operated in accordance with the latest function table logP(Z) in the memory 9b, and the demodulated data RD is generated.

Description

【発明の詳細な説明】 (発明の分野) この発明(J、ディジタル信シ3(ム送系にインパルス
性雑音が及ばず影響を改善覆るために、夕・J象とηる
通信路のインパルス性汀γ5の確・V密度関数(p、d
、f)を測定分析し、それをパラメータとして使用して
受信側単独で伝送性(’I夕改jハする同期系の最適受
信(幾。
DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) This invention (J. The definite V density function (p, d
, f), and use it as a parameter to determine the optimal reception of the synchronous system that achieves the transmittance ('I) on the receiving side alone.

(発明の背訂)) 続開的手法による最適受信賎は、対象どするi′1[音
のモデル化と合わせて保々に検問されている。
(Revised version of the invention)) The optimum reception level using the subsequent method is constantly being checked in conjunction with the modeling of the target i′1[sound.

しかし何れの場合も、それぞれ対Z!どじだ鉗高のtデ
ル化方法に従って受信1幾回路を検問しており、どのよ
うな雑音のモデル化においても安定に動作づる汎用最適
受信機は、大型コンピユータによる仮想受信機としてし
か存在しなかった。
However, in either case, each vs. Z! A general-purpose optimal receiver that operates stably in any type of noise modeling exists only as a virtual receiver using a large computer. Ta.

例えば、Q適量信我を実現するためにまず雑音のモデル
化理論を検討し、N音の確率密度関数P(Z)を、物]
!I!的に処理しやづい簡略式に展開して、その簡略式
をそのまま電子回路に置き換えて行くか、あるいはその
1ii1略式の演算処理をマイクロプロセッサで行なう
構成が考えられている。
For example, in order to realize Q-appropriate belief, first consider the modeling theory of noise, and then calculate the probability density function P(Z) of N sounds by
! I! Consideration has been given to developing a simplified formula that is easier to process and directly replacing the simplified formula with an electronic circuit, or to perform arithmetic processing of the simplified formula using a microprocessor.

このような設ム1では、釘1昌モデ′ルが明らかになり
、簡略式がめられた場合には、その簡略式に対応した最
適受信1幾が伯られるが、それらは雑音モデル毎に異な
る構成もしく(よ異なる演算アルゴリズムを持つ8蟹が
ある。また、最尤検定の演算をアナログ回路で行なうも
のでは、演算処理速度(J速いか、どうしても動作パラ
メータの5シ定箇所か多くなるため、この方式に適用で
きる演算式自体に人さ−なゐり限か加わるという欠点が
ある。J、た、マイクし」プロセッ→ノヲ用いてソフト
ウェア的に演算処理を行なうものでは、回路774成を
複層1にけずに複雑なンμi篇も行なえるのでj商1目
づるilHp式にス・1する制限はあまりない。しかし
演算アルゴリズムが複雑化すると、その処理速度が制限
され、大口)間で動作させるには非常に低速のデータ通
イ3にしか対応できないという欠点がある。
In such a setup 1, if the nail model is clarified and a simplified formula is found, the optimal reception model corresponding to the simplified formula can be calculated, but these differ depending on the noise model. There are 8 types with very different calculation algorithms.In addition, in the case where the calculation of maximum likelihood test is performed using an analog circuit, the calculation processing speed (J is faster, or there are inevitably more 5 points of operation parameters) However, this method has the disadvantage that only a few people are added to the arithmetic expressions that can be applied to this method. Since it is possible to perform complex n μi operations without breaking the multilayer 1, there are not many restrictions on using the j quotient 1 mz ilHp formula.However, as the arithmetic algorithm becomes more complex, its processing speed is limited and large The drawback is that it can only support very low-speed data communication.

何れにしても上述したJζうな統J1的手法にJ、る最
適受信□は、その統計的条(4か成立づるとさにのみ7
rl適に動作づる。従って、前(;?となる条件の入力
には非常に21:意する必要があり、そのため統に1的
条件の把]屋には雑音状態の長時間の測定にJ、り平均
化したデータが採用され、子のような平均的な条件下で
最適をめるようになってしまう。
In any case, the optimal reception □ in the above-mentioned Jζ una system J1 method is only 7
rl works properly. Therefore, it is necessary to be extremely careful when inputting conditions such as is adopted, and the optimum is found under average conditions like children.

このことは逆に言うと、通(ffi回線の和音状態か1
笈つかの異なるパターンの状態をとり<4がら変化りる
場合、その平均状態について(コ最適と/、「るか、個
々のパターンについては必ずしし最適に(Jならないと
いうことである。
To put it the other way around, this can be said to be
If the states of different patterns are changed from <4, then the average state will be (J) and/or (J).

常に最適に動作づる最適受信1幾を実現りるには、動作
中に通信回線の雑音状態をモニタし、l/Cδ1的条件
を判定する鵬能を持ち、ぞの判定結果を最尤検定のパラ
メータとしてフィードバックづることが必要となる。し
かし従来は、このことを現実的に実Jlj容易な回路で
もって(jなえるような回路方〕(は仝く提案されてい
なかった。
In order to achieve optimal reception that always operates optimally, it is necessary to have the ability to monitor the noise state of the communication line during operation, determine the l/Cδ1 condition, and apply the determination result to the maximum likelihood test. It is necessary to provide feedback as a parameter. However, in the past, this has not been proposed using a circuit that is actually easy to implement.

(発明の[1的) この発明の目的は、メモリを多用した簡単なディジタル
回路により高速に最尤検定の演算処理が行なえ、かつ、
受イ3動作中に雑音状態を測定分析し、その結果を逐次
演緯部にノイードバックづ゛ることにより、通13路の
f、1I8−状態の変動に追従して常に最適受信が行な
えるようにした雑音追従形同期式汎用IQ適受信1幾を
提供することにある。
(Object 1 of the Invention) An object of the present invention is to perform maximum likelihood test calculation processing at high speed with a simple digital circuit that uses a large amount of memory, and
By measuring and analyzing the noise state during the receiving 3 operation and sequentially feeding back the results to the processing section, it is possible to always perform optimal reception by following the fluctuations in the f, 1I8- state of the 13th path. The object of the present invention is to provide a noise-following type synchronous general-purpose IQ appropriate reception system.

(発明の構成) 上記の目的を辻成り−るために、この発明は、雑音の確
率密度間pl!IP(Z)、その変形または近似関数、
あるいはこれらを含む最尤検定式の一部をなづ一関故の
データをデープルの形で記憶づる関数アーブルメモリと
、受信信号波形および同期信号波形のディジタル化され
たザンブル値で上記関数テーブルメ[りをアドレッシン
グしてり1応づる関数データを渥み出づテーブル7?ク
セス回路と7、−1−記関数デーブルメモリから院み出
されるデータに某づいて1データ伝送毎に最尤検定の判
定を4−j <;い、復調テ′−夕を1’7る出力判定
回路と、上記テーブルアクセス回路および出力判定回路
の動伯fl Qに基づいて受信中の雑音状態を測定分析
し、その雑音状態に合わせた関数テーブルを作成りる2
I目°″1状態分析回路と、この分析回路で作成された
関数デープルを上記関数デーブルメ[りに置さ]うtえ
るテーブル更新手段とを備えることを特徴とづる。
(Structure of the Invention) In order to achieve the above-mentioned objects, the present invention provides a method for achieving the noise probability density pl! IP(Z), its transformation or approximation function,
Alternatively, you can create the above function table using a function memory that stores part of the maximum likelihood test formula including these in the form of a daple, and digitized zamble values of the received signal waveform and synchronization signal waveform. Table 7? Based on the data retrieved from the access circuit and the function table memory, the maximum likelihood test is performed for each data transmission. Measure and analyze the noise state during reception based on the output judgment circuit, the above-mentioned table access circuit, and the output judgment circuit's motion frequency fl Q, and create a function table tailored to the noise state.2
The present invention is characterized by comprising a one-state analysis circuit and table updating means for placing the function table created by the analysis circuit in the function table.

(発明の理論向背■]) 一般に、3=1象とする着1音の確−t−密度関数(1
1d、f)がP(z)−4’与えられる場合、同I’l
1式の最適受信ill CL、データ1ピッ1−の11
1間幅1の間に2値の同期信号S+(し)、Sこ (+
1と受イ1τ(11号χ(1)をN回す−ンブリングし
、式(−1・1)に表わされる操作で最尤検定を行なう
ことににって実現されることが良く知られている。
(Backwards from the theory of invention)) In general, the probability-t-density function (1
1d, f) is given P(z)-4', then the same I'l
1 set of optimal reception ill CL, data 1 pin 1-11
Binary synchronization signals S+ (shi), Sko (+
It is well known that this can be achieved by combining 1 and 1τ (No. 11 χ(1) N times) and performing a maximum likelihood test using the operation expressed in equation (-1・1). There is.

小さいとさ・に仮説1〜l+ (S+が送られlζ)を
選択し、Δか1Jメ上のどきは仮説H2(Szが送られ
た)を選択づることを式(1・1)は示している。
Equation (1.1) shows that hypotheses 1 to l+ (S+ is sent and lζ) are selected when the value is small, and hypothesis H2 (Sz is sent) is selected when Δ or 1J is above. .

J、た、X 11は受信16日波のη番目のサンプル俯
であり、S11]・5211は同期信号のη番目のサン
プル俯て゛、 In =S l n +Z n (イ言分が5t)=S
2n+Zn(信号が82) なる関係にdつる。ここでZ nは雑品を表わす41「
率変数である。
J, T, X 11 is the ηth sample of the received 16th wave, S11]・5211 is the ηth sample of the synchronization signal, In = S l n + Z n (I word is 5t) = S
The relationship is 2n+Zn (signal is 82). Here, Z n is 41, which represents miscellaneous goods.
is a rate variable.

前記式(1・1)の両辺の対数をとって出換えると次式
(1・2)がまる。
By taking the logarithms of both sides of the above equation (1.1) and replacing them, the following equation (1.2) is obtained.

y−Σ(f!、ogP(χII −32n )1 −1agP (Xn −3+ n ) )50 −(1
・2)2 この発明の最適量(g機は上記の最尤検定式(1・2)
の操作を、次に述べるディジタル回路にて実現さけるも
のである。
y−Σ(f!, ogP(χII −32n )1 −1agP (Xn −3+ n ) )50 −(1
・2)2 The optimum amount of this invention (g machine is the maximum likelihood test formula (1.2) above)
This operation is realized by the digital circuit described below.

(実施例の説明) 図はこの弁明にJ、る最適受信(幾のtM成を示してい
る。入力端子INの印加信号からフィルタ1および増幅
器2によって受信信号χ(1〉がjIlらねる。また、
この受信信号χ([)から同期抽iJ1回路3によって
その伝送速度を示ヅ同ilI]クロックOLが抽出され
る。同期クロックCLの周期tit伝IZデータの1ピ
ッl−0;’j間幅丁に古しい。
(Description of the Embodiment) The figure shows the optimal reception (tM configuration) according to this explanation.The received signal χ(1> is routed from the signal applied to the input terminal IN by the filter 1 and the amplifier 2). Also,
From this received signal χ([), a synchronous extraction iJ1 circuit 3 extracts a clock OL indicating the transmission speed. The period of the synchronization clock CL is 1 bit l-0 of the IZ data; 'j is extremely old.

受信信号χ([)はA 、、、−’ D変換回路5によ
つ−Cリンブリングされるとともにディジタル化され、
そのサンプル俯X nが減算回路7に入力される。
The received signal χ([) is subjected to −C rimbling and digitized by the A, , , −′ D conversion circuit 5,
The sample elevation Xn is input to the subtraction circuit 7.

同期クロックOLは、同門発振回路・同期式分周カウン
タ・デコーダなど力口らなる同期タイミング回路4に加
えられ、このタイミング回路4に」、って△/D変換回
路5.波形データメモリ6、出力判定回路11等のタイ
ミング条イ′1が1′「られる。
The synchronous clock OL is applied to a synchronous timing circuit 4 consisting of a synchronized oscillation circuit, a synchronous frequency dividing counter, a decoder, etc. The timing line '1' of the waveform data memory 6, output determination circuit 11, etc. is set to '1'.

同期タイミング回路4は同期り[」ツクCLの周波数1
/′TのN倍の周波数の信号を作り、これを△/D変換
回路5のタイミング(5号どじて印加づる。つまり受信
信号χ(1)は、その1デ一タ伝送肋間T中にN回すン
ブリングされる。このり′ンブル値がIn(++=1.
2.・・・、N)である。
The synchronous timing circuit 4 is synchronized with the frequency 1 of the synchronous CL.
A signal with a frequency N times /'T is created and applied to the △/D conversion circuit 5 at the timing (No. 5). In other words, the received signal χ(1) is It is assembled N times.This multiple number is In(++=1.
2. ..., N).

また同期タイミング回路4は、周波数が2N/下の信号
も作り、この信号°1b1b数1/Tの信号を出ツノ判
定回路11のタイミング(a号どして印加する。
The synchronous timing circuit 4 also generates a signal with a frequency of 2N/lower, and applies this signal with a frequency of 1/T to the output horn determination circuit 11 at the timing (a).

また同期タイミング回路4は、Rピッ1〜(21′−2
N)の2進」−ド化出力を、間隔T / 2 Nの速度
で歩進し、1デ一タ伝送時間丁毎に2進コートを一巡さ
ける。この2進コード出力は波形メモリ6の)7ド1ノ
ス信号どなる。
Further, the synchronous timing circuit 4 operates at R pins 1 to (21'-2).
The binary encoded output of N) is stepped at a speed of interval T/2 N, and one binary code is skipped every 1 data transmission time. This binary code output becomes the )7 do 1 NOS signal of the waveform memory 6.

波形メ[す6には、同期信号S IJ3よびSzの1周
lit]分の波形を等間1:呂にN点でサンプリングし
てディジタル化したデータSinおよび5211(n=
1.2.・・・、N>が格納されている。ただし、メモ
リ6の2N個のアドレスにデータ3 InどS 2 n
が交t7に格納されている。つまりデータS1[)が奇
数アドレスに格納され、データ5211が偶数−ノ′ド
レスに格納され−Cいる。同期タイミング回路4の2進
」−ド出力でメモリ6がアドレッシングされると、同期
信号波形データS211 、3111か交nに読み出さ
れ減算回路7に人力さ4する。
The waveform method 6 contains data Sin and 5211 (n=
1.2. ..., N> are stored. However, data 3 IndS 2 n is stored in 2N addresses of memory 6.
is stored at intersection t7. That is, data S1[) is stored at an odd numbered address, and data 5211 is stored at an even numbered address -C. When the memory 6 is addressed by the binary output of the synchronization timing circuit 4, the synchronization signal waveform data S211, 3111 or n is read out and input to the subtraction circuit 7 manually.

減算回路7は、△/′D変換回路5の出力から波形メモ
リ6の出ツノを減算ηるディジタル演c?I’c ?−
Jなう。つまりデータX1l−8211とデータχ11
Sinが減弁回路7から交I7に出力され、この出りが
パス切替回路8を介して関数テープルメしり9aまたは
9bの何れかのアミルレス人力どなる。
The subtraction circuit 7 subtracts the output of the waveform memory 6 from the output of the Δ/'D conversion circuit 5 and performs a digital operation c? I'c? −
J now. In other words, data X1l-8211 and data χ11
Sin is outputted from the valve reduction circuit 7 to the AC I7, and this output is passed through the path switching circuit 8 to the output of either the function table 9a or 9b.

関数テーブルメモリ9a、91+のアドレスバス1則の
切替回路8どデータバス側の切替回路1013.lCP
U12によって制御される。C1つU12i。[、関数
テーブルメモリ9a 、9bの何れか一方を白身に結合
し、他の一方を減樟回−゛87と出力判定回?811に
結合りる。
Function table memory 9a, 91+ address bus 1 rule switching circuit 8, data bus side switching circuit 1013. lCP
Controlled by U12. One C U12i. [, either one of the function table memories 9a and 9b is combined with the white, and the other one is reduced to 87 and output judgment times? Connects to 811.

いま、関数デープルメモリ9aかj賎イ回路?と七ツノ
判定回路11に結合されているとづる。この1易合メモ
リ9aには、後述づるようにめられ/、:;1象とする
通信路の眉1音の確率密痘関数1)(Z)を対数変換し
た関数ゑOすP(Z)が関数/’−−ゾルD形でδI2
憶されている。この関数デーゾルの−7−タは、初期状
態においては予め他のコンピュータにJ、ってδ1算さ
れることになるが、実動作状態にてはCI) U 12
によって作成・修正された値である。なJ3、ここでの
関数デ゛−夕はj2ooP(Z)を適宜に近似したり変
形した関数のデータであっても良い。
Now, is it the function double memory 9a or the circuit? It is said that it is coupled to the seven-horn determination circuit 11. This 1-input memory 9a contains a function obtained by logarithmically transforming the probability function 1) (Z) of the eyebrow 1 sound of the communication channel as 1 object, as described below. ) is a function /'--sol D form δI2
It is remembered. In the initial state, the -7-ta of this function desol will be calculated in advance by another computer as J, but in the actual operating state, CI) U 12
This is a value created and modified by . J3, the function data here may be data of a function obtained by appropriately approximating or transforming j2ooP(Z).

鍼(′>回路7の出力で関数テーブルメモリ9aがアド
レッシングされるど、データAoaP(Xn−8zn)
どデータRogP (Xn −9) n )がメモリ9
aから交互に読み出される。このデータはバス切替回路
10を介して出力判定回路11に入力される。出力判定
回路11は、関数テーブルメモリ9aから順次読み出さ
れるデータを受()て、受信信号X(をンの1デ一タ伝
送時l1iIT毎に前記の式(1・2)の総削演痒を行
ない、がっ、その総剖結果の値yを0と比較し、yがo
にり小さいが0以上かを示づ信号、すなわI5復調デー
タRDを出力する。
When the function table memory 9a is addressed by the output of the circuit 7, the data AoaP (Xn-8zn)
The data RogP (Xn −9) n) is stored in memory 9.
are read out alternately from a. This data is input to the output determination circuit 11 via the bus switching circuit 10. The output determination circuit 11 receives the data sequentially read out from the function table memory 9a, and performs a total calculation of the equations (1 and 2) every l1iIT when transmitting one data of the received signal X(). Then, compare the gross autopsy result value y with 0, and find that y is o.
A signal indicating whether the value is smaller than or equal to 0, ie, I5 demodulated data RD, is output.

上jホした受信・復調動作中において、cpu i2は
減弊回路7の出力(受信信号のサンプル値χ夕を含む)
と出ツノη′り定回路11h)ら出ツノされる復調デー
タRDとを取込み、これらに基づい(受信中の雑音状態
を一定時間測定分l7−Slる。Jた同1il11に、
分析測定される雑音状態に基づいて、復調動作に使用さ
れていないbう−1)の関数フーーゾルメモリ9LIに
その雑音状態に見合った関29.テーブルを新たに作成
する。一連の着1音状態の分(h測定・関数デープルの
作成処理が完了したならば、CI−’U12はバス切替
回路8ど10を同1ll)[こ1.lJ?今える。
During the reception and demodulation operations described above, CPU i2 outputs the output of the attenuation circuit 7 (including the sample value χ of the received signal).
and the demodulated data RD output from the output η′ constant circuit 11h), and based on these, the noise state during reception is measured for a certain period of time l7-Sl.
Based on the analyzed and measured noise conditions, the function fusol memory 9LI that is not used for the demodulation operation is assigned a function corresponding to the noise conditions. Create a new table. For a series of one-tone ringing states (when h measurement and function daple creation processing are completed, the CI-'U 12 switches the bus switching circuits 8 and 10 to the same level) [this 1. LJ? I can do it now.

すると関数デープルメモリ9bが減紳回路7ど出力判定
回路11に結合され、この1狡(Jメーしり9bの最新
の関数デープルゑouP’(Z)に(Iηつて最尤検定
の演粋がなされ、復調データR1〕か作られる。CPU
124よ、このときもまノζ前述した眉1?等状態の分
析測定・関数デープルの作成処JjPをi’j ’Jい
、復調動作に使われていイ2いメ[す9aの関数デープ
ルを更新づ゛る。
Then, the function daple memory 9b is connected to the reduction circuit 7 and the output judgment circuit 11, and the derivation of the maximum likelihood test is obtained by adding (Iη demodulated data R1] is created.CPU
124, at this time also the eyebrow 1 mentioned above? Isostate analysis measurement/function daple creation process JjP is used to update the function daple in step 9a used in the demodulation operation.

以上の動作を繰り返し、着1名状態の変化(J追従して
常に適切な関数テーブルを使用した最尤イσj定による
受信動作が行なわれ、常に最適受信を実現υることかで
さ−る。
By repeating the above operation, the reception operation is performed according to the maximum likelihood constant σj by following the change in the status of the recipient (J) and always using an appropriate function table, thereby always achieving optimal reception υ. .

なJ3関数−1−プルどして、ゑogp(Xn−82n
 ) −Jl!ogP (Xn −S + n )の関
数テ′−夕あるいはその近似関数データを用い、このテ
ーブルをχ++ 、 S 211 、 S + nで引
き、のデータを累計する構成としても良い。J、た波形
データメモリからデータ32 nと511)が同時に並
列的に読み出されるJ、うに4j11成してもよい。
J3 function-1-pull and eogp(Xn-82n
) -Jl! It is also possible to use the function table of ogP (Xn - S + n) or its approximate function data, to draw this table by χ++, S211, S + n, and to accumulate the data. The data 32n and 511) may be simultaneously read out in parallel from the waveform data memory.

(発明の効果) この発明にJ、る最適受信(戊の復調動作の速度を制限
する主な要素は、関数デープルとして使用するメモリの
動作速度であり、他の付随した簡単な9fi J!I!
 +i仝Cその面間以下で実行できる。従って高い周波
数レヘルのキA・リアぐも直接実111間演算ができる
。また、最尤検定のIζめのサンプリング回数Nを贈り
ことで伝送品質を充分に高くづることか可1止である。
(Effects of the Invention) The main factor limiting the speed of the optimal reception (demodulation operation) of this invention is the operation speed of the memory used as a function double, and other accompanying simple 9fi J!I !
+i仝C Can be executed with less than that distance. Therefore, it is possible to directly perform calculations between the key A and the real 111 at a high frequency level. Furthermore, it is only possible to make the transmission quality sufficiently high by giving the Iζth sampling number N of the maximum likelihood test.

211音の41r %−密度関数を動作パラメータどし
て受信(幾回路にフィードバックすることが、関数デー
タをテーブルの形てメモリに記悦りることC”、’K 
3れるため、外部調整が全く不要て・(19す、(すく
め−(l定に動作づる。また、復調動作と並tj シー
’ニーなさ4′シる雑音状態の測定分11i・関数デ〜
ツルのI’l−1戊′4哩はそれ(Jと畠速性を必要と
されないのて、−flu的なマイクロプロセツリを用い
て容易に1フイfうことができる。このように復調動作
と卯行して関数1−ブルの作成処理を行ない、その処理
か完了し、に時点で囚助に復調動作に使用さ1する関数
テーブルが新たなものに更新されるので、j;;に最新
の211旨状態に見合った関数f−タに早ついて最尤検
定か行なえ、信l!1ri1iの高い1(周動1′1か
実現て・ハる。
Receiving the 41r%-density function of the 211 sound as an operating parameter (feeding it back to the circuit is to record the function data in the memory in the form of a table)
3, there is no need for external adjustment at all.(19)(shrug-(l) It operates at a constant rate.In addition, the measured noise state 11i/function de~
Tsuru's I'l-1 戊'4哩 can be easily converted to 1F using a -flu-like microprocessor, since it (J and speed is not required.) In tandem with the operation, the process of creating function 1-bull is performed, and when that process is completed, the function table used for the demodulation operation is updated to a new one. Then, quickly find the function f-ta that corresponds to the latest 211 effect state, perform a maximum likelihood test, and realize that the high 1 (period 1'1) of belief l!1ri1i is realized.

この発明の最適受信(代(よ、IE i!II に−舅
(間開タイミング)が得られる4gらり、K、m (t
、l P SK (lイノ11]シフ1ヘキーインク)
でdうってし、211白F S l〈(周波数シフ1−
1−インク)−(あつCム、あるい(Jでれjうを変形
し!、:変1i14方式τあ−)でし、同1!1j仁シ
j?ル形を設定する波形データメしりの内容を変更51
にとで幅広く対応づることができる。
The optimum reception (interval timing) of this invention can be obtained at 4g, K, m (t
, l P SK (l Ino 11] Schiff 1 Heki Ink)
Then, 211 white F S l (frequency shift 1-
1 - Ink) - (Ats Cm, or (J derej to transform!,: Change 1i14 method τA-), and the same 1! Change the contents of 51
It can be used in a wide range of ways.

【図面の簡単な説明】[Brief explanation of drawings]

図(まこの発明の〜実施例による雑音追従形同期式汎用
最適量1z貼の(jl)戒を示タブロック図である。
FIG. 1 is a block diagram illustrating a (jl) rule for a noise-following type synchronous general-purpose optimum quantity 1z according to an embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] (1)対象とづる通イΔ路の雑音のルイ「率畜1宴関数
P(7)を把握し、その+3!]数P(Z)に基づいて
統81的な手法により最尤検定を行なって復調データを
得る最適受信故であって、 ■酋の確率密麿関vlp < z > 、その変形また
は近似関数、あるいはこれらを含む最尤検定式の一部を
なt [!]数のデータをテーブルの形で記憶する関数
テーブルメモリと、 受信信号波形d’) J:び同+!II信号波形のディ
ジタル化されたサンプル値で上記関数テーブルメモリを
アドレッシングして対応づる関数データを読み出1デー
プルアクセス回路と、 」二乙己関数デープルメモリから読み出されるデータに
基づいて1データ伝送毎に最尤検定の判定を行ない、復
調データを得る出力判定回路と、上記テーブルアクセス
回路および出力判定回路の動作信号に基づいて受信中の
届?イ状態を測定か(rr L、その雑音状態に合わせ
た関数テーブルを作成するM音状態分析回路と、 この分析回路で作成さtt、 IJII!] tシーノ
ープルを一1記関数テーブルメモリに首き1%えるアー
ブル史新手段ど。 を備えることを特徴とづる7[1音)D従形同1す1式
(1・L用最適量信観。
(1) Understand the probability function P(7) of the noise of the target and the delta path, and perform the maximum likelihood test using a systematic method based on the +3!] number P(Z). In order to obtain the demodulated data by performing optimal reception, ■ the probability density function vlp < z >, its modification or approximation function, or a part of the maximum likelihood test formula including these, of the number t [!] A function table memory stores data in the form of a table, and the received signal waveform d') Addresses the function table memory with digitized sample values of the received signal waveform d') and reads the corresponding function data. an output determination circuit that performs a maximum likelihood test determination for each data transmission based on the data read from the two-order function diple memory and obtains demodulated data; and the table access circuit and output. Is the notification being received based on the operation signal of the judgment circuit? Measure the A state (rr L, M sound state analysis circuit that creates a function table tailored to the noise state, and the M sound state analysis circuit created by this analysis circuit tt, IJII!). Havre history new means to increase by 1% etc. 7 [1 note) D subordinate form 1 and 1 set (1/L optimal quantity belief view).
JP17469383A 1983-09-21 1983-09-21 Synchronous general optimum receiver of noise following-up type Granted JPS6066546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17469383A JPS6066546A (en) 1983-09-21 1983-09-21 Synchronous general optimum receiver of noise following-up type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17469383A JPS6066546A (en) 1983-09-21 1983-09-21 Synchronous general optimum receiver of noise following-up type

Publications (2)

Publication Number Publication Date
JPS6066546A true JPS6066546A (en) 1985-04-16
JPH042027B2 JPH042027B2 (en) 1992-01-16

Family

ID=15983022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17469383A Granted JPS6066546A (en) 1983-09-21 1983-09-21 Synchronous general optimum receiver of noise following-up type

Country Status (1)

Country Link
JP (1) JPS6066546A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364447A (en) * 1986-09-04 1988-03-22 Nec Corp Signal receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364447A (en) * 1986-09-04 1988-03-22 Nec Corp Signal receiver

Also Published As

Publication number Publication date
JPH042027B2 (en) 1992-01-16

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