JPH0420145U - - Google Patents
Info
- Publication number
- JPH0420145U JPH0420145U JP6092290U JP6092290U JPH0420145U JP H0420145 U JPH0420145 U JP H0420145U JP 6092290 U JP6092290 U JP 6092290U JP 6092290 U JP6092290 U JP 6092290U JP H0420145 U JPH0420145 U JP H0420145U
- Authority
- JP
- Japan
- Prior art keywords
- detection signal
- abnormality detection
- function section
- abnormality
- processing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims description 11
- 238000001514 detection method Methods 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 230000008054 signal transmission Effects 0.000 claims description 4
- 230000010365 information processing Effects 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 claims 2
- 230000005540 biological transmission Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案を実施した情報処理装置の全体
構成図、第２図は本考案装置の動作を表わすフロ
ーチヤート、第３図は本考案装置の動作の例を説
明するための図である。
１……中央処理装置、１１……読込手段、１２
……書込手段、２……周辺処理装置、２１……周
辺処理装置固有機能部、２２……異常検出機能部
、２３……異常検出信号送出機能部、２４……異
常状態指示機能部、２５……異常検出信号送出禁
止機能部、Ｂ……並列バス。
FIG. 1 is an overall configuration diagram of an information processing device implementing the present invention, FIG. 2 is a flowchart showing the operation of the device of the present invention, and FIG. 3 is a diagram for explaining an example of the operation of the device of the present invention. . 1...Central processing unit, 11...Reading means, 12
. . . Writing means, 2 . . . Peripheral processing device, 21 . 25... Abnormality detection signal transmission prohibition function unit, B... Parallel bus.
Claims (1)
を介して接続される少なくとも１個以上の周辺処
理装置とからなり、各前記周辺処理装置から出力
される異常検出信号がワイアード・オアされ前記
中央処理装置が各前記周辺処理装置の異常を認識
する情報処理装置において、各前記周辺処理装置
に、当該周辺処理装置の異常を検出し内部異常検
出信号を出力する異常検出機能部と、前記内部異
常検出信号を前記並列バスへ送出する異常検出信
号送出機能部と、前記内部異常検出信号により当
該周辺処理装置が異常であることを設定する異常
状態指示機能部と、前記中央処理装置の指示によ
り前記異常検出信号送出機能部の前記異常検出信
号の送出を禁止する異常検出信号送出禁止機能部
とを設け、前記中央処理装置に、前記異常状態指
示機能部の内容を読み込む読込手段と、前記異常
検出信号送出禁止機能部に信号送出禁止を指示す
る書込手段とを設けたことを特徴とする情報処理
装置。 It consists of a central processing unit and at least one or more peripheral processing units connected to the central processing unit via a parallel bus, and the abnormality detection signal output from each peripheral processing unit is wired-ORed and sent to the central processing unit. In the information processing device in which the device recognizes an abnormality in each of the peripheral processing devices, each of the peripheral processing devices includes an abnormality detection function unit that detects an abnormality in the peripheral processing device and outputs an internal abnormality detection signal; an abnormality detection signal sending function section that sends a signal to the parallel bus; an abnormality indication function section that sets that the peripheral processing device is abnormal based on the internal abnormality detection signal; an abnormality detection signal transmission prohibition function section for prohibiting the transmission of the abnormality detection signal of the detection signal transmission function section, and a reading means for reading the contents of the abnormal state indication function section into the central processing unit; An information processing device comprising: a writing means for instructing a transmission prohibition function section to prohibit signal transmission.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6092290U JPH0420145U (en) | 1990-06-08 | 1990-06-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6092290U JPH0420145U (en) | 1990-06-08 | 1990-06-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420145U true JPH0420145U (en) | 1992-02-20 |
Family
ID=31588714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6092290U Pending JPH0420145U (en) | 1990-06-08 | 1990-06-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420145U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6152752A (en) * | 1984-08-23 | 1986-03-15 | Nippon Telegr & Teleph Corp <Ntt> | Fault display circuit |
-
1990
- 1990-06-08 JP JP6092290U patent/JPH0420145U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6152752A (en) * | 1984-08-23 | 1986-03-15 | Nippon Telegr & Teleph Corp <Ntt> | Fault display circuit |
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