JPH0419898A - Non-volatile memory provided with automatic read circuit - Google Patents

Abstract

PURPOSE:To reduce the load of a CPU and to improve the throughput of a system by providing an address counter to generate a read address, control signal generation part to control inside and outside write and read signals, and bus buffer to switch internal and external buses. CONSTITUTION:In order to automatically read out data written in advance, the data of address values to be generated by an address counter 4 are successively read out by instructing automatic read according to an automatic read control signal F, and an automatic read data latch signal E is outputted from a control signal generation part 5. During automatic read, the control signal generation part 5 inhibits write and read from the CPU, and the read signal of a non-volatile memory cell 2 is outputted by a memory cell driver 6 so as to read the data of the non-volatile memory cell. Thus, the load of the CPU can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a nonvolatile memory with an automatic read circuit.

[Conventional technology]

Conventionally, this type of nonvolatile memory has been comprised only of nonvolatile memory cells and their reading and writing circuits, and has not had a circuit for realizing an automatic read function.

[Problem to be solved by the invention]

In the conventional non-volatile memory described above, when setting parameters for data stored in the memory in various Ilo etc.
Since it does not have an automatic read circuit, it is necessary for the CPU to read the contents of the memory once and write it to each I10.
When the number of parameters increases or when a high-speed system recovery operation is required, the processing speed of the CPU may become a problem.

[Means to solve the problem]

The nonvolatile memory with an automatic read circuit of the present invention has an address counter that generates a read address, a control signal generator that controls internal and external write and read signals, and a path buffer that switches between internal and external buses. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 1 shows an address bus buffer 1 having a switching function, a nonvolatile memory cell 2, a data bus buffer 3 having a switching function, an address counter 4 operated by external write and read control signals from the CPU, cPU
A control signal is generated based on the control signal and the automatic read control signal, and the address bus buffer 1. Data bus buffer 3 consists of a control signal generator 5 that controls the memory cell driver 6.

Writing and reading from the CPU to memory cells is performed by the CPU.
In response to write and read control signals from the address bus buffers 1 and 1, the control signal generating section 5 generates control signals. Controls data bus buffer 3. This allows address bus buffer 1. The data bus buffer 3 is switched to the CPU side, and the volatile memory cell 2 is switched to the CPU address signal.
At the same time, the data bus buffer 3
Preparations are made to send data to data signal B. The memory cell driver 6 generates write and read signals for nonvolatile memory cells, and executes writing and reading from the nonvolatile memory cells.

On the other hand, when automatically reading pre-written data,
When automatic reading is instructed by the automatic reading control signal F, the address value data generated by the address counter 4 is read out sequentially, and the automatic reading data latch signal E is output from the control signal generating section 5. CPU during automatic reading
The control signal generator 5 prohibits writing and reading from the nonvolatile memory cell 2, and the memory cell driver 6 outputs a read signal for the nonvolatile memory cell 2 to read data from the nonvolatile memory cell.

〔Effect of the invention〕

As explained above, the present invention has the effect of reducing the load on the CPU and improving the processing capacity of the system by realizing the function of automatically reading the contents of non-volatile memory and setting it to each I10. Furthermore, when restarting the system due to a momentary power outage, etc., parameters can be set without going through the CPU, which has the effect of shortening the processing time of the CPU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Address bus buffer, 2...Nonvolatile memory cell, 3...Data bus buffer, 4...Address bus counter, 5...Control signal generator, 6...Memory cell driver, A...CPU address signal, B...
...CPU data signal, C...automatic read data signal, D...CPU write and read control signal, E...automatic read data latch signal, F...automatic read control signal.

Claims (1)

[Claims] A nonvolatile memory with an automatic read circuit, characterized by having an address counter that generates a read address, a control signal generator that controls internal and external write and read signals, and a bus buffer that switches between internal and external buses. .