JPH02216558A - Memory control system - Google Patents

Abstract

PURPOSE:To rewrite a memory without interrupting processing, and to promptly use a high-speed memory when necessary by simultaneously writing the same data to the high-speed memory and the low-speed memory. CONSTITUTION:When the high-speed memory is selected, an FF 6 is set by the signal of a processor 1, and at the time of reading, only the high-speed memory is selected and operated through AND gates 7 and 8 where a read command 14 is inputted. At the time of writing, both high-speed memory 3 and low-speed memory 4 are selected by a write command 13. Since the write speed of the two memories are different, the write data to the low-speed memory 4 are temporarily stored into a buffer 5. When the low-speed memory 4 is selected, since the FF 6 is reset, only the low-speed memory 4 is operated at the time of reading, and the both high-speed memory 3 and low-speed memory 4 are operated at the time of writing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control system, and particularly to a memory control system for switching equipment.

[Conventional technology]

Conventionally, this type of memory control system has not had a means for instructing two types of memories with different speeds to write the same data at the same time.

[Problem to be solved by the invention]

In the conventional memory control method described above, when selecting and using memories with different speeds according to instructions from the processor, data transfer operations between the memories are required because the contents of the two types of memories are not identical. However, the disadvantage is that memory switching cannot be performed quickly.

[Means to solve the problem]

The memory control method of the present invention has different speeds.

In a memory control method for controlling a high-speed memory, a flip-flop is set and reset by a Bromo, Su instruction, a write instruction means for instructing writing of the same data into both the low-speed and high-speed memories at the same time; A buffer is added to the low-speed memory to temporarily store the write address and data, and based on the values of the buffer and the buffer, only one of the low-speed and high-speed memories is enabled to start the read operation. The present invention is characterized in that it comprises a reading activation means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of the present invention.

The memory control circuit 2 is connected to the memory control circuit 2 via the bus 100, and the memory control circuit 2 receives the address 11 and the data 1.
2 and the write instruction 13 are input to the high speed memory 3 and are also input to the low speed memory 4 via the buffer 5. Set and go signals 15. from memory 111IJ control circuit 2. Set by reset signal 16.

The output of the flip-flop 6 to be reset is directly inputted to the AND circuit 7 as a memory selection signal 17, and also inputted to the AND circuit 8 via an inverter, and the other input of each AND circuit 7.8 is inputted directly to the AND circuit 7. A read instruction 14 output from the memory control circuit 2 is connected. The output of the AND circuit 7 and the write instruction 13 are input to the OR circuit 9,
The output of the OR circuit 9 is input to the high speed memory 3 as a high speed memory enable signal 18. Further, the output of the AND circuit 8 and the write instruction 13 are input to the OR circuit 10, and the OR circuit l
The output of O is input to the low speed memory 4 as a low speed memory enable signal 19.

Next, the operation of this embodiment will be explained.

First, when a high-speed memory is selected, a memory selection command including instructions from Bromo and Sl is input to the memory control circuit 2 via the bus 100, and a set signal 15 sets FlipFlo and Pro. . When the flip-flop 6 is set, during a read operation, the read instruction 14 outputted along with the address 11 is passed through the AND circuit 7 where the output condition is met to enable and read only the high-speed memory 3, and start the operation. do. In addition, during a write operation, both the high speed memory 3 and the low speed memory 40 are enabled through the OR circuit 9 and IO, and the write operation is started, regardless of the value of the flip 70 knob 6. However, at this time, since the speeds of both memories are different, by temporarily storing the address and data in the buffer 5 for writing to the low-speed memory 4, the processor l can increase the speed to match the speed of the high-speed memory 3. can perform actions.

Next, when the selection is switched to a low-speed memory, a memory selection command based on the command is input from the bromo 1 to the memory control circuit 2 via the bus 100, and the olfactory set signal 16
The shift flip-flop 6 is reset. Furi, Pflop 6. Lyceum.

When the read operation is performed, the output condition of the AND circuit 8 is satisfied and only the low-speed memory 3 is enabled, and the read operation is started. Also, during a write operation, since the values of FRI, PRO, and PRO are not concerned, the write operation to both the high-speed memory 3 and the low-speed memory 4 is started in exactly the same way as when the above-mentioned 7-lip-flop 6 is set. .

〔Effect of the invention〕

In the case of an exchange system or the like that needs to continuously execute real-time processing without interruption, system continuity and flexibility to withstand temporary high loads are required. Incidentally, the faster the memory, the higher the power consumption during operation than when it is not in operation, and depending on the environmental conditions of the system, continuous use of high-speed memory may lead to failures due to temperature rise.

As explained above, by writing the same data to high-speed memory and low-speed memory at the same time, the present invention can perform memory switching without interrupting processing, and can quickly use high-speed memory only when needed. Therefore, it is possible to realize an exchange with high load carrying capacity and high reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1...Bromo, Su, 2...Memory control circuit, 3...High speed memory, 4...Low speed memory, 5...Birth . F, 6...Fri, Pflo, P, 7.8...
...AND circuit, 9,10...OR circuit, 1
00... Bus. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In a memory control method for controlling low-speed and high-speed memories with different speeds, a flip-flop is set and reset by a processor instruction, and write instruction means for instructing writing of the same data into both the low-speed and high-speed memories at the same time. a buffer added to the low-speed memory to temporarily store the write address and data; and a read operation by activating only one of the low-speed and high-speed memories based on the value of the flip-flop. 1. A memory control system comprising: a reading activation means for activating a memory control method.