JPH04196441A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent short circuits and current leaks by providing the edge of a polycrystalline silicon with a side wall and by sputtering a high melting point metal over the whole semiconductor substrate to react with Si and by etching the high melting point metal on the side wall under reaction of this metal with Si. CONSTITUTION:A side wall 107 is formed at the edge of a gate electrode, and P(phosphorus) or As(arsenic) ions 108 are implanted into an N-channel region, and B(boron) or BF2 ions into a P-channel region to form a source-drain high- doped diffusion layer 111. Thereafter, the whole silicon substrate is etched with the gases of SF6 and flon 114. After sputtering a high melting point metal Ti, Ti and Si are reacted by annealing so that the unreacted high melting point metal on an SiO2 is removed by wet etching. This process can prevent gate-source and gate-drain short circuits and current leaks.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an MO3 type semiconductor device, and particularly to a method of forming a gate electrode.

[Prior Art] A conventional method for forming sidewalls of a gate electrode is to form a gate electrode made of polycrystalline silicon on a gate insulating film formed on a semiconductor substrate, and then form a sidewall in an etched portion of the gate electrode. , Ti (
Forms silicide such as titanium). Thereafter, unreacted metal on the sidewalls was removed by wet etching.

[Problems to be Solved by the Invention] However, when a side wall is provided on a polycrystalline silicon film in this way, the convergence of the side wall is approximately 0 when the thickness of the polycrystalline silicon film is 4500 mm. , about 2 μm, and the apex of the sidewall is at the same level as or lower than the surface of the polycrystalline silicon.

Therefore, after sputtering a high melting point metal such as Ti (titanium) and forming silicide and polycide through heat treatment, the removal of unreacted high melting point metal is not complete, and the high melting point metal or 5i02 There is a problem in that short circuits between the gate and the source and between the gate and the drain are likely to occur due to particles such as reactants.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which defects are less likely to occur by preventing short circuits and current leaks between the gate and the source and between the gate and the train. It is in.

[Means for Solving the Problems] The present invention includes a step of depositing polycrystalline silicon on a gate insulating film formed on an element formation region on a semiconductor substrate, and a step of depositing polycrystalline silicon on a region that will become a gate electrode of a MOS transistor. a step of etching the polycrystalline silicon so as to leave a side wall; and a step of providing a sidewall in the etched portion of the polycrystalline silicon;
A step of etching the polycrystalline silicon again, a step of sputtering a high melting point metal over the entire surface of the semiconductor substrate, a step of reacting the high melting point metal with Si (silicon) by heat treatment, and a step of etching the high melting point metal on the side wall by wet etching. The method is characterized in that it includes a step of etching the metal.

[Example] FIGS. 1A to 1I are cross-sectional views of a semiconductor substrate in an example of the present invention, and steps related to gate electrode formation will be described in detail below.

First, a LOCOS 102 is formed on a semiconductor substrate 101, and an activated region and a non-activated region are divided. (1st
Figure (a)) Next, the semiconductor substrate was subjected to steam oxidation at a temperature of 850°C for 2 hours.
0 minutes, silicon oxide film 103 with a film thickness of 200,
form. (Figure 1(b)) Then 1. Polycrystalline silicon 1! by CVD method! After depositing P (phosphorous) ions 105, which are N-type impurity ions, on a semiconductor substrate to a thickness of 7000, P (phosphorous) ions 105 are diffused into the polycrystalline silicon film 104. (Fig. 1(C)) Then, the gate electrode region made of the polycrystalline silicon film is buttered by photolithography, and the polycrystalline silicon film is heated to 100 mTo with gases of SF6 and Freon 114.
Etching is carried out under a pressure of rr. (Figure 1(d)
) Next, in order to form a low-temperature impurity diffusion layer 106 in the source and drain regions near the gate electrode, As is added at a concentration of 10110l2" to 10"cm-2 in the N channel region.
(Arsenic) or P (phosphorus) ions of 1°5 are implanted (Fig. 1(e)).
BF2 ions or B (boron) ions are implanted at a concentration of nn-2 to 10 cm-.

Then, after depositing a 5i02 film which will become a sidewall by CVD, tri-etching is performed to form a sidewall 107 in the etched portion of the gate electrode. , (FIG. 1(f)) Next, in order to form the high concentration impurity diffusion layers 111 for the source and drain, a 1°" cm-
P (phosphorus) or A with a seed degree of 2 to 10” cm-2
Implantation of s (arsenic) ions 108 is performed (Figure 1 (g))
, 1015cm-2~101 in the P channel region
*Ion implantation of B (boron) or BF2 at a concentration of Cm-2 is performed.

Thereafter, the entire surface of the silicon substrate is etched using gases of SF6 and Freon 114 under a pressure of 100 mTorr to reduce the thickness of the polycrystalline silicon film to about 4000 mTorr. At this time, the surface of the side wall that is etched at the same time is only slightly etched.

Then, after sputtering high melting point metal Ti (titanium), lamp annealing is performed at 700°C to 750°C.
By reacting i (titanium) and Si (silicon), Ti-
5ilicide and Ti-Polycide are formed.

Next, perform wet etching by passing ammonia water,
Remove unreacted high melting point metal on 5i02.

(FIG. 1(h)) After depositing the glabellar membrane, it is formed in the same manner as in the case of forming a normal MOS transistor. (1st
(Figure (i)) In this way, in the formed semiconductor device, the top of the sidewall made of 5i02 of the etched gate electrode portion is higher than the surface of the polycrystalline silicon, and the convergence of the sidewall is also compared to the conventional one. Therefore, it is difficult to form a path for causing a short circuit between the gate and the source or between the gate and the drain due to particles made of Ti (titanium) or a reaction product of Ti and 5i02.

[Effects of the Invention] As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to prevent short circuits between the gate and source, gate and drain of a MOS transistor, and current leakage. This has the effect of increasing product yield and device reliability.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(1) are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention. 101 , , , , , Semiconductor substrate 102 , , ,
,,,,LOG O5103,,,,,,,Silicon oxide film 104.113,,,Polycrystalline silicon 105.
108. ,, N-type ion 106.109 ,,, Low concentration diffusion layer 107.11
1. Side wall 110. High temperature diffusion layer 112.
, , , , T i -S i l i c i d
e114 , , , , , T i -P o l
i c i d e115 , , , , , 8 or more applicants Seiko Epson Co., Ltd. Representative Patent attorney Kizobe Suzuki (and 1 other person) Figure 1 (d) Figure 1 (e) Figure 1 (f)

Claims (1)

[Claims] A step of depositing polycrystalline silicon on a gate insulating film formed on an element formation region on a semiconductor substrate, and a step of depositing MOS
a step of etching the polycrystalline silicon so as to leave a region that will become a gate electrode of a transistor; a step of providing a side wall at an edge portion of the polycrystalline silicon; a step of etching the polycrystalline silicon again; It is characterized by comprising the steps of sputtering a high melting point metal onto the entire surface of the substrate, causing the high melting point metal to react with Si (silicon) by heat treatment, and etching the high melting point metal on the side wall by wet etching. A method for manufacturing a semiconductor device.