JPH04196166A - Semiconductor non-volatile memory and its writing method - Google Patents

Abstract

PURPOSE:To produce a non-volatile memory which allows writing only once by applying high negative voltage on the source of an n-channel MOS transistor and breaking the junction between a drain and a substrate. CONSTITUTION:Information writing is performed by applying a voltage Vpp, which causes the potential difference Vds (Vdd-Vpp) between a source 112 connected through a bit line 115 and a drain 111 to exceed the drain withstand voltage of a transistor 101, on a terminal 105 and by breaking the junction between the drain 111 and a substrate electrode 114. At that time, since current flows from a diode 103 to the source 112 through resistances 104 and 102, the potential of a gate 113 turns on the transistor 101. As for the information reading, a condition that the potential of the bit line 115 is higher than (Vdd-Vss)/2 is displayed by '1', and the condition lower is displayed by '0'. From the transistor 101, the '1' is outputted since the drain and the source are short- circuited, and from a non-written transistor, the '0' is read.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only semiconductor nonvolatile memory that can be written only once, and a writing method therefor.

[Conventional technology]

In semiconductor integrated circuits, it is possible to improve yields and stabilize performance by correcting manufacturing variations such as transistor threshold voltages and storing changes in operating conditions using memory elements that can be written only by -degrees. conversion is being carried out.

Memory elements that can be written only once are mainly laser fuse blowing type, electric fuse blowing type, and junction breaking type PROM (Programma-aMe).
R, ead OnlyMemory).

[Problem to be solved by the invention]

However, the laser fuse blowing type requires a special device for laser generation to write information, and it is also expensive because it requires opening two holes in the passivation film for the fuse to form a laser entrance window. . In the electric fuse blowing type, the writing of information itself physically destroys polysilicon, etc., so there are problems such as generation of silicon debris and deterioration of the passivation film.

Junction destruction type requires a large amount of current to write information, so the voltage applied during writing is large, and to prevent write current leakage, the semiconductor element is required to have a withstand voltage higher than the write voltage. This has the disadvantage of complicating the process.

Therefore, the purpose of the present invention is to provide a non-volatile memory that can be written only once, which does not cause generation of silicon waste or deterioration of the passivation film, and does not require high voltage resistance of peripheral elements, and which has a simple manufacturing process, and a writing method therefor. It provides:

[Means to solve the problem]

In order to achieve the above object, the nonvolatile memory of the present invention employs the structure and writing method described below.

(a) An n-channel MO8+- transistor that is a memory element, a first resistor connected between the gate and source of this n-channel MO8I- transistor, and an n-channel M
A memory cell is constituted by a second resistor and a diode connected between the gate of the OS + - transistor and the low potential of the drive power source of the semiconductor device.

(b) An n-channel MOS transistor which is a memory element, a bit line connected to the source of this n-channel MOS transistor, and a resistor connected between this bit line and a word line, A memory cell is constituted by connecting the gate terminal G-1 to the low potential of the driving power source of the semiconductor device.

(c) The resistor constituting the memory cell is composed of at least one of a diffused resistor and a polysilicon resistor.

) Connect the drain of the n-channel MOS transistor, which is a memory element, to the high potential of the drive power supply of the semiconductor device,
Writing is performed by applying a high negative voltage, which is a write voltage, to the source of the n-channel MOS transistor.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a part of the circuit of a memory cell which is an embodiment of the semiconductor nonvolatile memory of the present invention. In FIG. 1, an n-channel MOS transistor (hereinafter referred to as a memory transistor) 101, which is a memory element, is composed of a drain 111, a source 112, a gate 116, and a substrate electrode 114. gate 116 and source 112
A first resistor 102 is connected between them, and a gate 116 is connected to a low potential (hereinafter referred to as ss) of a driving power source for the semiconductor device via a second resistor 104 and a diode 106. The tune-in 111 is connected to a high potential (hereinafter referred to as ■dd) of a driving power source for the semiconductor device. Further, when writing information to the memory transistor 101, a negative high write voltage (hereinafter referred to as Vpp) is supplied from the outside with a offset terminal 105, which is connected to the source 112 via a bit line 115. A third resistor 106 connects the bit line 115 and the word line 116 .

The operation of the semiconductor nonvolatile memory configured as described above will be described below.

Information is written using the potential difference between the source 112 and drain 111, which are connected to the terminal 105 via the pictogram line 115.
da (Vdd-Vpp) is the memory transistor 10
This is done by applying V p p which is equal to or higher than the drain breakdown voltage of the memory transistor 101 from an external power source to the terminal 105 to cause junction breakdown between the drain and the substrate of the memory transistor 101 . Due to this junction breakdown, the drain 111 and source 112 of the memory transistor 101 are electrically short-circuited through the substrate electrode 114. During this write, a high negative voltage VpP is applied to the source 112, so the diode 1 [
13 is in the forward direction and current flows.

From this 7g8, a diode 103, a second resistor 104,
When a current flows through the path to the first resistor 102 and the source 112, the resistance of the diode 103 is the first
Since the potential of the gate 116 is sufficiently small compared to the resistor 102 and the second resistor 104, the potential of the gate 116 changes from V, @-0.6V to Vl'l
It can take any value between 1. That is, it is possible to make the potential difference between the gate 116 and the source 112 higher than the threshold voltage of the memory transistor 101. Therefore, writing can be performed with the memory transistor 101 in the on state. On the other hand, VPI is input to the write terminal 105.
When + is not applied, the diode 103 does not go in the forward direction even if the potential of the word line 116 is V a s, so the memory transistor 101 is turned off. Further, when the potential of the word line 116 is dd, the diode 103 is in a reverse bias state, so no leakage current flows.

Next, regarding the information read operation, when the potential of the bit line 115 is higher than (■dd-■511)/2 and the potential of the word line 116 is set to yes for information reading, from the memory transistor whose junction has been destroyed, Since the drain and source are short-circuited, 1 is output from the bit line 115, and 0 is read as information from the non-written memory transistor whose junction is not broken.

In the circuit diagram of FIG. 1, the mechanism by which the drain 111 and source 112 of the memory transistor 101 are brought into conduction will be explained as follows.

The drain breakdown voltage of a general enhancement type n-channel Mos transistor is determined by avalanche breakdown of the drain-substrate junction, electric field concentration at the surface due to the influence of the gate, and parasitic bipolar operation involving minority carrier injection. The mechanism of bond failure itself is bond failure type F.
It is the same as ROM. That is, during writing, the drain is reverse biased with a voltage higher than the drain breakdown voltage, causing breakdown and current flowing. Since most of the voltage is applied to the thin junction interface, heat loss at the junction is also large, and the temperature of a part of the non-uniform junction rises rapidly due to thermal runaway, leading to breakdown.

Junction destruction type PR and OM that destroy the diode junction are:
While only the avalanche breakdown of the PN junction determines the breakdown voltage, in a memory transistor, multiple effects reduce the drain breakdown voltage as described above. FIG. 3 shows the relationship between the drain breakdown voltage and the gate voltage with reference to the source potential. It is a well-known fact that the drain breakdown voltage is the lowest when the gate voltage is about 1/2 of the drain voltage.

Furthermore, from FIG. 3, it is clear that the drain breakdown voltage becomes the largest under the condition where the gate voltage is 0. This drain breakdown voltage approximately corresponds to the reverse pressure of the PN junction of the semiconductor device.

It is clear that if writing is performed with the memory transistor in the on state as in the present invention, it is not necessary to increase the breakdown voltage of the peripheral semiconductor elements. Also, the first resistor 1 in FIG.
If the sizes of 02 and the second resistor 104 are appropriately selected,
It is possible to perform writing in a state where the drain breakdown voltage is the lowest.

FIG. 2 shows a partial circuit diagram of a memory cell, which is an embodiment of a semiconductor nonvolatile memory according to another embodiment of the present invention. In FIG. 2, a memory transistor 201, which is an n-channel MOS transistor, is composed of a drain 211, a source 212, a gate 216, and a substrate electrode 214.

The gate 216 is connected to ■IIs, and the drain 211 is connected to ■IIs.
connected to dd. Write terminal 205 is connected to source 212 via bit line 215. A resistor 206 connects the focus line 215 and the word line 216.

The operation of the semiconductor nonvolatile memory configured as described above will be described below. Similar to the embodiment in FIG. 1, when ■pp is applied to the write terminal 205, the potential difference between the gate 216 and the source 212 is yes VII
p, and the gate voltage is higher than the threshold voltage of the memory transistor 201, so the memory transistor 201
Writing is performed in the on state.

Writing to the memory cell shown in FIG. 2 is not performed when the drain breakdown voltage is at its lowest. However, as is clear from FIG. 3, even in the memory cell shown in FIG. 2, the drain breakdown voltage is lowered by about 5 μm compared to the off state of the memory transistor. Furthermore, writing must be performed while limiting excessive current to prevent dielectric breakdown of the memory transistor. The memory transistor 201 has dielectric breakdown and the drain 2
If 11 and gate 216 are short-circuited, ■dd, drain 2
11, through the gate 216 and the path of V s a.
Leakage current flows.

The range of current values for writing information without causing dielectric breakdown is:
- For example, P well concentration 1.9X10”aj□mS/
cr&, source and drain concentration 12×1020a
toms/7, when an n-channel MOS transistor with a gate oxide film thickness of 3Qnm, a gate length of 2μm, and a gate width of 10μm is used as a memory cell, ds is 14V.
At this time, the current value ranges from 60mA to 150mA. On the other hand, in the memory cell of FIG.
If the dielectric breakdown occurs in the drain 111 and the drain 113, the diode 106 becomes reverse biased and no leakage current flows.

However, the memory cell of FIG.
does not require. Therefore, it is advantageous for increasing the degree of integration of semiconductor devices.

Note that the resistors constituting the memory cells are composed of diffused resistors or polysilicon resistors.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, there is no generation of silicon debris or deterioration of the passivation film, and therefore no deterioration of the characteristics of the semiconductor element occurs. Further, there is no need to increase the voltage resistance of peripheral semiconductor elements. Furthermore, the structure is the same as a normal n-channel MO8, making it possible to obtain a writable non-volatile memory, and if applied to an integrated circuit consisting of a MOS transistor, the manufacturing method will be simple and there will be no increase in manufacturing costs. The effect is very strong.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a nonvolatile memory in an embodiment of the present invention, FIG. 2 is a circuit diagram showing a nonvolatile memory in another embodiment, and FIG. 3 is an example of writing information in the nonvolatile memory of the present invention. 2 is a graph showing the relationship between drain breakdown voltage and gate voltage of a memory transistor. 101.201...n-channel MOS transistor (memory transistor), 102...first resistor, 106...diode, 104...second resistor , 111.211...Drain, 112.212
......Source, 116.216...Gate. ■dd dd 211,. 2141 Yu=-m-■ ＼ 212 ↓/ SS

Claims (1)

[Scope of Claims] (1) An n-channel MOS transistor which is a memory element, a first resistor connected between the gate and source of the n-channel MOS transistor, and a first resistor connected between the gate and source of the n-channel MOS transistor;
A semiconductor nonvolatile memory characterized in that a memory cell is configured by a second resistor and a diode connected between the gate of an S transistor and a low potential of a drive power source for a semiconductor device. (2) comprising an n-channel MOS transistor as a memory element, a bit line connected to the source of the n-channel MOS transistor, and a resistor connected between the bit line and the word line; A semiconductor nonvolatile memory characterized in that a memory cell is configured by connecting a gate to a low potential of a driving power source of a semiconductor device. (3) The semiconductor nonvolatile memory according to claim 1 or 2, wherein the resistor constituting the memory cell is comprised of at least one of a diffused resistor and a polysilicon resistor. (4) Connecting the drain of the n-channel MOS transistor, which is a memory element, to the high potential of the drive power supply of the semiconductor device,
A writing method for a semiconductor nonvolatile memory, characterized in that writing is performed by applying a high negative voltage as a writing voltage to the source of the n-channel MOS transistor.