JP4316693B2 - Semiconductor resistance device and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of a semiconductor resistance device and a control method thereof, and more particularly, a yield of a semiconductor integrated circuit is corrected by correcting manufacturing variations such as resistance and changing operating conditions using a memory element that can be written only once in a semiconductor integrated circuit. Regarding improvement and stabilization of performance.
[0002]
[Prior art]
FIG. 6 is a circuit diagram showing a conventional technique in a semiconductor resistance device including a circuit for adjusting the resistance value of a resistance array based on information stored in a laser fuse blown programmable read only memory (PROM).
[0003]
As shown in FIG. 6, the semiconductor resistance device has eight resistors 81, 82, 83, 84, 85, 86, 87, 88 connected in series, and eight MOSs connected in parallel to the eight resistors. Transistors 91, 92, 93, 94, 95, 96, 97, 98 and a decoder 80 are included.
[0004]
The memory block 70 has three laser fuse blown PROM elements 71, 72, 73 that connect one end to the high potential of the power supply, one end connected to the laser fuse blown PROM element, and the other end to the low potential of the power supply. And inverters 77, 78, 79 whose output voltage is determined by the potential at the connection point between the laser fuse blown PROM element and the comparison resistor.
[0005]
The semiconductor resistance device inputs the outputs from the inverters 77, 78, 79 of the memory block 70 to the decoder 80, and turns on one of the MOS transistors 91, 92, 93, 94, 95, 96, 97, 98. By doing so, eight types of resistance values can be selected.
[0006]
For example, if the laser fuse blown-type PROM elements 71, 77, 73 of the memory block 70 are not blown, the output voltages of the inverters 77, 78, 79 are all the low potential of the power supply voltage, and the MOS transistor 91 is turned “ON”. The decoder 80 is controlled so as to be in a state. As a result, the semiconductor resistance device has the resistance value of the resistor 81.
[0007]
Further, when the laser fuse blown PROM elements 72 and 73 are blown, the output of the inverter 77 becomes a low potential of the power supply voltage, the outputs of the inverters 78 and 79 become the high potential of the power supply voltage, and the decoder 80 is turned on. Thus, the MOS transistor 94 is turned on, and the resistance value is a value obtained by adding the resistance 81, the resistance 82, the resistance 83, and the resistance 84.
[0008]
As the memory element which can be written only once, in addition to the laser fuse blown PROM element described above, there are PROM elements such as an electric fuse blown type and a junction breakdown type.
[0009]
[Problems to be solved by the invention]
However, in order to read the information stored in the memory block 70 and determine the state of each memory element, as shown in FIG. 6, the comparison resistors 74, 75, and 76 and inverters 77, 78, and 79 are required. There is a drawback that the area of the integrated circuit is increased.
[0010]
Furthermore, since the power source, the laser fuse PROM elements 71, 72, 73 and the comparison resistors 74, 75, 76 constitute a closed circuit, a current always flows.
Therefore, in order to suppress the current consumption of the semiconductor integrated circuit, it is necessary to add a data latch circuit (not shown in FIG. 6).
[0011]
Further, the laser fuse blown PROM element is irradiated with laser light for writing information. Therefore, a dedicated device for generating laser light is required, and further, a passivation film on the fuse PROM element must be opened to form a laser light incident window.
For this reason, the area of the semiconductor integrated circuit is increased, the cost is increased, and there is a disadvantage that the mounting form is limited in order to write information after mounting.
[0012]
Further, the electric fuse blown PROM element writes information by physically destroying polysilicon or the like constituting the PROM element. Therefore, there are problems such as generation of silicon scraps and deterioration of the passivation film.
[0013]
The junction destruction type PROM element writes information by passing an electric current to destroy the junction. For this reason, since a large amount of current is required for writing information, the voltage applied at the time of writing is large, and the elements constituting the semiconductor integrated circuit must have a withstand voltage higher than the writing voltage in order to prevent leakage of the writing current. And
For this reason, there exists a fault that the manufacturing process for forming becomes complicated.
[0014]
In addition, the electric fuse blown PROM element and the junction breakdown type PROM element apply a high voltage to the memory element, and thermally destroy a portion to which most of the voltage is applied in a path through which a large current flows in the memory element. Write information.
For this reason, the magnitude of the resistance value that can be inserted between the memory element and the write voltage terminal is limited.
[0015]
Therefore, it is difficult to select and write an electrical fuse blown PROM element or a junction breakdown PROM element using a general MOS transistor as an address transistor.
[0016]
[Object of invention]
Therefore, the object of the present invention is to prevent generation of silicon scraps and deterioration of the passivation film, and further, it is not necessary to increase the breakdown voltage of the elements constituting the semiconductor integrated circuit, the manufacturing process is simple, and no readout circuit is required. A semiconductor resistance device that does not consume current to read written information and a control method thereof.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, the semiconductor resistance device of the present invention employs the following structure and control method.
[0018]
  The semiconductor resistance device of the present invention connects a plurality of resistors in series.One end is connected to a predetermined potentialAt the connection point between the resistor array and multiple resistors in the resistor arrayA plurality of memory elements having one end connected and the other end connected to a predetermined potential, and a plurality of address transistors for selectively writing information to each of the plurality of memory elements.Memory cell, MeThe memory element is set as a resistor by writing information in the memory element, and the resistance value of the resistor array connected in parallel is selected.
[0019]
  Semiconductor resistance device of the present inventionofResistor arrayHas alternately a plurality of low sheet resistance regions and a plurality of high sheet resistance regions respectively constituting a plurality of resistors on a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrateIt is characterized by that.
[0020]
  Semiconductor resistance device of the present inventionThe memory element includes a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate, a memory oxide film provided on the polycrystalline silicon wiring, and a polycrystalline silicon electrode provided on the memory oxide film.Electrically writable only onceNameMori elementTossIt is characterized by that.
[0021]
  Semiconductor resistance device of the present inventionThe control method ofMultiple resistors connected in seriesOne end is connected to the high potential of the driving voltage of the semiconductor deviceAt the connection point between the resistor array and multiple resistors in the resistor arrayA plurality of memory elements having one end connected and the other end connected to a high potential of a driving voltage, and a plurality of address transistors for selectively writing information to each of the plurality of memory elementsA memory cell havingMemory elementProvided on field oxide film on semiconductor substrateThe first electrode connected to the connection point of the resistors of the resistor array, the memory oxide film provided on the surface of the first electrode, the first electrode in contact with only the memory oxide film and connected to the high potential of the drive voltage A method of controlling a semiconductor resistance device having a memory element that has two electrodes and is electrically writable only once,
  By applying a write voltage to the first electrode of the memory element to which information is written, the memory oxide film is caused to break down and become a resistor, and a constant voltage is applied to the first electrode of the non-selected memory element to prevent writing. By selecting the resistance value of the resistance array to be connected in parallel,.
[0022]
  Semiconductor resistance device of the present inventionIn this control method, the constant voltage is a voltage lower than the breakdown voltage between the high potential of the drive voltage or the high potential of the drive voltage and the write voltage.It is characterized by that.
[0023]
  Semiconductor resistance device of the present inventionIn the control method ofMultiple resistors connected in seriesOne end is connected to the high potential of the driving voltage of the semiconductor deviceA resistor array;A P-channel MOS transistor having a drain connected to the other end of the resistor array and a source connected to the high potential of the drive voltage;At the connection point between multiple resistors in the resistor arrayA plurality of memory elements having one end connected and the other end connected to a high potential of a driving voltage, and a plurality of address transistors for selectively writing information to each of the plurality of memory elements.A memory cell,Memory elementProvided on the field oxide film on the semiconductor substrateThe first electrode connected to the connection point of the resistors of the resistor array, the memory oxide film provided on the surface of the first electrode, the first electrode in contact with only the memory oxide film and connected to the high potential of the drive voltage Two electrodes,Electrically writable only onceNameMori element andA method for controlling a semiconductor resistance device, comprising:
  By applying a write voltage to the first electrode of the memory element to which information is written, the memory oxide film is caused to break down to become a resistor, and both ends of the resistor array are set to a high potential of the drive voltage, thereby selecting a non-selected memory element. A resistor array connected in parallel by applying a voltage smaller than a breakdown voltage obtained by dividing the potential difference between the high potential of the drive voltage and the write voltage to the first electrode by a resistor constituting the resistor array to prevent writing. Select resistance value of.
[0039]
[Action]
In the semiconductor resistance device of the present invention, when a user forcibly applies an overvoltage from the outside to a memory oxide film that insulates a first electrode and a second electrode of an arbitrary memory element and causes permanent destruction. The first electrode and the second electrode are brought into conduction.
Then, the resistance value of the resistor array can be arbitrarily selected by setting the current to flow only through the memory element in the conductive state.
[0040]
Therefore, after manufacturing the semiconductor integrated circuit, selection information of the resistance array is stored in one memory element that obtains a resistance value that meets the specifications.
Since the selection information directly forms a path through which the current of the resistor array flows, the reading circuit and the data latch circuit which are conventionally required are not required, and the semiconductor resistance device of the present invention consumes the current necessary for the operation of these circuits. The resistance value can be set to an optimum value.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an optimal embodiment for carrying out a semiconductor resistance device of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor resistance device according to an embodiment of the present invention. Hereinafter, an embodiment of the present invention will be described with reference to FIG.
[0042]
[Description of Semiconductor Resistance Device: FIG. 1]
As shown in FIG. 1, the semiconductor resistance device of the present invention comprises four resistors 29, 30, 31, and 32 connected in series, one end of which is a high potential of the operating voltage of the semiconductor integrated circuit (hereinafter referred to as Vdd). The resistor array 8 connected to the three, the three memory cells 1, 2, 3 connected in parallel to the three connection points 33, 34, 35 in the resistor array 8, the address control circuit 4, and the program voltage is supplied from the outside. The Vm terminal 5 for applying a high negative write voltage (hereinafter referred to as Vm), the address signal input terminal 7 and the program mode input terminal 6 is used.
The address control circuit 4 is connected via a pull-down resistor 36 to a low potential (hereinafter referred to as Vss) of the operating voltage of the semiconductor integrated circuit.
[0043]
Memory cells 1, 2, 3 have memory elements 10, 11, 12 connecting electrodes 13, 15, 17 to Vdd and electrodes 14, 16, 18 to connection points 33, 34, 35 of resistor array 8, respectively. The connection portions of the drain electrodes of the P-channel MOS transistors 19, 20, 21 and the N-channel MOS transistors 22, 23, 24 are connected to the connection points 33, 34, 35 of the resistor array 8.
The gate electrodes of the P-channel MOS transistors 19, 20 and 21 are connected to signal lines 25, 26 and 27 from the address control circuit 4, respectively. On the other hand, the gate electrodes of the N-channel MOS transistors 22, 23, 24 are connected to the three signal lines 28 from the address control circuit 4 so that the same control can be performed.
The P channel MOS transistors 19, 20, and 21 and the N channel MOS transistors 22, 23, and 24 constitute an address transistor.
[0044]
The memory elements 10, 11, and 12 are constituted by memory elements having a read-only metal-insulating film-metal structure that can be electrically written only once. FIG. 2 shows a cross-sectional structure of this metal-insulating film-metal memory element. FIG. 2 is a cross-sectional view showing a memory element according to an embodiment of the present invention.
[0045]
As shown in FIG. 2, a field oxide film 42 is provided on a semiconductor substrate 41, and a first electrode 43 made of polycrystalline silicon is provided on the field oxide film 42.
Further, a memory oxide film 44 that is a thin silicon oxide film formed on the surface of the first electrode 43 and a second electrode 45 made of polycrystalline silicon provided on the memory oxide film 44 are provided. Furthermore, an aluminum wiring 47 for setting the potential of the first electrode 43 and the second electrode 45 is provided through a contact hole provided in the interlayer insulating film 46.
[0046]
As a method of manufacturing a memory element having a metal-insulating film-metal structure in the present invention, polycrystalline silicon constituting a gate electrode in a general complementary field effect transistor (CMOS transistor) manufacturing process is formed on the entire surface, and impurities are formed. This is the same as the processing step up to the injection step.
That is, the gate electrode of the MOS transistor and the first electrode 43 may be formed of the same polycrystalline silicon. Here, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 41 by a chemical vapor deposition apparatus, and pattern formation is not performed.
[0047]
Next, a thin silicon oxide film is formed on the first electrode 43 by thermal oxidation to form a memory oxide film 44. Thereafter, polycrystalline silicon is further formed by chemical vapor deposition, impurity implantation is performed to form a predetermined conductive layer, and a polycrystalline silicon which is the first electrode 43 material as shown in FIG. Patterning is performed so as to leave the second electrode 45 on the silicon film.
[0048]
Next, the first electrode 43 and the gate electrode of the MOS transistor are pattern-formed using a photoetching method. Subsequently, a general CMOS transistor manufacturing process for forming the interlayer insulating film 46 after forming the gate electrode of polycrystalline silicon, forming contact holes, and forming the aluminum wiring 47 is performed.
[0049]
Thus, the patterning of the gate electrode of the MOS transistor and the first electrode 43 is performed after the second electrode 45 is patterned. For this reason, the pattern dimension of the gate electrode of the MOS transistor is not reduced, and there is no generation of etching residue of polycrystalline silicon, which is a material for forming the second electrode 45.
[0050]
In addition, making the memory element before forming the source region and the drain region does not increase the diffusion distance between the source region and the drain region due to heat treatment when forming the memory oxide film 44. That is, there is no influence on the MOS transistor characteristics due to the formation of the memory element.
[0051]
Information is written in the memory element by setting the potentials of the first electrode 43 and the second electrode 45 so that an electric field of 8 MV / cm or more is applied to the memory oxide film 44. This is performed by causing permanent destruction of the first electrode 43 and the second electrode 45.
[0052]
On the other hand, when the memory oxide film 44 provided between the first electrode 43 and the second electrode 45 is in a potential state that does not cause dielectric breakdown, the first electrode 43 and the second electrode 45 remain in an insulated state. is there.
[0053]
By controlling the potentials of the first electrode 43 and the second electrode 45 in this way, the state can be changed to two stable states, ie, a conductive state and an insulating state, and thus operates as a memory element.
[0054]
[Resistance array resistance setting explanation: Fig. 2]
Next, a method for setting the resistance value of the resistor array 8 of FIG. 1 that meets the specifications after manufacturing the semiconductor integrated circuit device will be described with reference to FIG.
[0055]
The resistance value of the resistance array 8 can be selected from four types of resistance values by bringing one of the memory elements 10, 11, 12 constituting the memory cells 1, 2, 3 into a conductive state. That is, this corresponds to writing resistance value setting information in the memory elements 10, 11, and 12.
[0056]
To write data to the memory element, first, an external power supply set to the Vss voltage is connected to the Vm terminal 5.
A signal “1” is input to the program mode input terminal 6 to set the address control circuit 4 to the write mode. An address signal is input to the address input terminal 7 to select a write destination memory element.
[0057]
Next, a negative high write voltage (Vm voltage) is applied to the Vm terminal 5 for a predetermined time as the output voltage of the external power supply, and the memory oxide film of the selected memory element is subjected to dielectric breakdown to perform writing.
[0058]
The operating state of the P-channel MOS transistors 19, 20, 21 and the N-channel MOS transistors 22, 23, 24 in the memory cells 1, 2, 3 when the Vm voltage is applied to the Vm terminal 5 is A case where writing is performed will be described below as an example.
Here, however, the resistance values of the P channel MOS transistors 19, 20, 21 and the N channel MOS transistors 22, 23, 24 in the “ON” state are the resistance values of the resistors 29, 30, 31, 32 of the resistor array 8. It is assumed to be sufficiently smaller than.
[0059]
Vdd is applied from the address control circuit 4 via the signal line 25 to the gate electrode of the P channel MOS transistor 19 of the memory cell 1, and the P channel MOS transistor 19 is in the “off” state.
On the other hand, the Vm voltage is applied to the gate electrodes of the P-channel MOS transistors 20 and 21 of the memory cells 2 and 3 via the signal lines 26 and 27 from the address control circuit 4. “On” state.
[0060]
Vdd is applied from the address control circuit 4 via the signal line 28 to the N-channel MOS transistors 22, 23, 24 so as to be always “ON” in the write mode.
[0061]
At this time, the potential of the electrode 14 of the memory element 10 becomes Vm because the P-channel MOS transistor 19 is in the “off” state.
Therefore, since the potential of the electrode 13 of the memory element 10 is Vdd, information is written by applying a voltage higher than the dielectric breakdown voltage to the memory oxide film.
On the other hand, the potentials of the electrodes 15 and 17 of the memory elements 11 and 12 are Vdd, but the potentials of the electrodes 16 and 18 are not Vm because the P-channel MOS transistors 20 and 21 are conductive. That is, since a voltage higher than the dielectric breakdown voltage is not applied to the memory oxide film, it remains in a non-written state.
[0062]
Here, the potentials of the electrodes 16 and 18 of the memory elements 11 and 12 can be set from Vdd to Vm depending on the on-resistance values of the P-channel MOS transistors 20 and 21 and the on-resistance values of the N-channel MOS transistors 23 and 24. .
For example, if the on-resistance values of the P-channel MOS transistors 20 and 21 and the on-resistance values of the N-channel MOS transistors 23 and 24 are approximately the same, the potentials of the electrodes 16 and 18 of the memory elements 11 and 12 are (Vdd + Vm) / 2. Therefore, it is possible to apply a voltage sufficiently lower than the dielectric breakdown voltage to the memory oxide films of the memory elements 11 and 12.
[0063]
FIG. 9 shows the time course of the potentials of the electrodes 14, 16 and 18 of the memory elements 10, 11 and 12. In FIG. 9, the change in potential of the electrode 14 corresponds to the broken line 49, and the change in potential of the electrodes 16 and 18 corresponds to the broken line 64. The origin of the time axis is when the signal “1” is input to the program mode input terminal.
An address for selecting the memory cell 1 is set at time t0. At time t1, the external power source is switched from Vss to Vm voltage. At time t2, the memory oxide film of the memory element 10 breaks down and writing is completed. At time t3, the external power source is switched from the Vm voltage to Vss. In FIG. 9, Vbr represents the breakdown voltage.
[0064]
From time t0 to time t1, the electrode 14 of the selected memory element 10 is at the Vss potential, and the electrodes 16 and 18 of the non-selected memory element 11 and the non-selected memory element 12 are connected to the on-resistance value of the P-channel MOS transistors 20 and 21 and N It becomes a potential obtained by dividing resistance between Vdd and Vss by the on resistance values of the channel MOS transistors 23 and 24.
Similarly, from time t1 to time t2, the electrode 14 of the selected memory element 10 is at the Vm voltage, and the electrodes 16 and 18 of the non-selected memory elements 11 and 12 are the on-resistance values of the P-channel MOS transistors 20 and 21 and the N-channel MOS. Depending on the on resistance values of the transistors 23 and 24, the potential is divided by resistance between the Vdd and Vm voltages.
From time t2 to t3, since the memory oxide film of the memory element 10 is broken down, the electrode 13 and the electrode 14 are electrically connected, so Vdd is approximately indicated.
[0065]
On the other hand, the electrodes 16 and 18 of the non-selected memory elements 11 and 12 are resistance-divided between the Vdd and Vm voltages by the on-resistance values of the P-channel MOS transistors 20 and 21 and the on-resistance values of the N-channel MOS transistors 23 and 24. The potential remains.
After time t3, the electrode 14 of the written memory element 10 indicates Vdd, and the electrode 16 and the electrode 18 of the non-write memory element 11 and the non-write memory element 12 use the P channel to switch the external power source from the Vm voltage to Vss. The potential obtained by dividing resistance between Vdd and Vss by the ON resistance values of the MOS transistors 20 and 21 and the ON resistance values of the N-channel MOS transistors 23 and 24 appears again.
[0066]
In FIG. 9, the on-resistance values of the P-channel MOS transistors 20 and 21 and the N-channel MOS transistors 23 and 24 are Rp1 and Rn1 when the absolute value of the gate-source voltage is | Vss-Vdd | When the absolute value of the gate-source voltage of | Vm−Vdd | is Rp2, Rn2.
[0067]
Next, the operation of the semiconductor resistance device of the present invention after setting the resistance value will be described. The connection between the Vm terminal and the external power supply is disconnected, and the potential of the Vm terminal is set to Vss through the pull-down resistor 36.
A signal “0” is input to the program mode input terminal, the address control circuit 4 is set to the normal mode, and the P channel MOS transistors 19, 20, 21 are gated from the address control circuit 4 through signal lines 25, 26, 27. Vdd is applied to the electrodes, and the P-channel MOS transistors 19, 20, and 21 are turned off.
[0068]
On the other hand, Vss is applied from the address control circuit 4 via the signal line 28 to the gate electrodes of the N-channel MOS transistors 22, 23, and 24 to turn them off.
[0069]
Since writing is performed on the memory element 10, the memory oxide film of the memory element 10 is broken down, and the electrode 13 and the electrode 14 to which Vdd is applied are in a conductive state.
Therefore, a path through which current flows through the memory element 10 to the connection point 33 between the resistor 29 and the resistor 30 of the resistor array 8 is formed.
[0070]
On the other hand, since the memory oxide films of the memory elements 11 and 12 are not dielectrically broken, the electrode 15 and the electrode 16 and the electrode 17 and the electrode 18 are in a non-passing state.
[0071]
The resistance value R0 of the resistance array 8 at this time is obtained by calculating the resistance values of the resistors 29, 30, 31, and 32 as R1, R2, R3, and R4 and the resistance value after writing of the memory element 10 as R5.
R0 = R2 + R3 + R4 + R5 · R1 / (R1 + R5)
It becomes.
[0072]
As is apparent from the equation described before obtaining the adjusted resistance value, the resistance value R5 of the memory element 10 is compared with the resistance values R1, R2, R3, and R4 of the resistors 29, 30, 31, and 32. When it is sufficiently small, R0 which is the resistance value of the resistor array 8 can be approximated to (R2 + R3 + R4).
[0073]
Although the case where information is written to the memory element 10 has been described here, the case where data is written to the memory elements 11 and 12 can be performed in the same manner, and thus detailed description thereof is omitted.
[0074]
Therefore, in order to expand the setting range of the resistance value of the semiconductor resistance device and make the setting of the resistance value more accurate, it is necessary to reduce the resistance value of the memory element after writing and further reduce its variation.
[0075]
[Description of distribution of resistance value of memory element: FIG. 3]
Next, in the memory element in which the film thickness of the memory oxide film 44 shown in FIG. 2 is 5 nm, the gate width dimension of the P-channel MOS transistor of the memory cell is set under the write condition of Vm voltage of minus 10 V and Vm application time of 1 ms. FIG. 3 shows a distribution of resistance values of the memory element after writing when the amount of current passing through the memory element is changed when Vm is applied.
[0076]
In the graph of FIG. 3, the resistance value of the memory element is measured by applying a voltage of 1 V to the memory element after writing, measuring the flowing current value, and converting it to a resistance value.
[0077]
As is apparent from the graph of FIG. 3, when the current value passing through the memory element is 2 mA, the resistance value is distributed in the range of 600Ω to 1 KΩ. The average value of the resistance is 750Ω.
On the other hand, when the current value is 200 μA, the resistance value is distributed from 1.5 KΩ to 11 KΩ, the average resistance value is 3.73 KΩ, the distribution is shifted to the high resistance side compared to 2 mA, and The variation is also great.
[0078]
Next, during normal operation, the voltage applied to the memory element changes depending on the resistance value of the resistor array 8.
Therefore, in order to set the resistance value accurately, the resistance value of the memory element after writing needs to have a small voltage dependency. Therefore, the voltage dependence of the resistance value of the memory element after writing is shown in the graph of FIG.
[0079]
[Description of voltage dependence of resistance value of memory element after writing: FIG. 4]
In FIG. 4, curves 50, 51, and 52 indicate voltage dependences when the resistance value after writing of the memory element at 1 V is 800Ω, 10KΩ, and 50KΩ, respectively. As is apparent from this graph, the smaller the resistance value after writing at 1 V, the smaller the change in resistance value due to voltage. Particularly, in the curve 50, no change in resistance value is observed.
On the other hand, in the curve 52, when the applied voltage becomes smaller than 0.5V, the resistance value remarkably increases depending on the voltage.
[0080]
From the graphs of FIG. 3 and FIG. 4, the write condition of the memory element is that the current value penetrating the memory element when Vm is applied is 2 mA or more. By writing to the memory element under this condition, the resistance value of the memory element after writing is distributed to 1 KΩ or less, and there is almost no variation.
Further, no voltage dependence is observed in the resistance value of the memory element after writing. This indicates that the resistance value of the resistor array 8 shown in FIG. 1 can be adjusted accurately and stably.
[0081]
[Description of Planar Pattern Shape of Resistor Array of Semiconductor Resistance Device: FIG. 5]
Next, in the case where the resistor array of the semiconductor device according to the embodiment of the present invention is formed of polycrystalline silicon, a part of the planar pattern shape of the resistor 29, the resistor 30, and the memory cell 1 in FIG. Shown in plan view.
[0082]
In FIG. 5, the polycrystalline silicon wiring 63 is connected to the high sheet resistance regions 55 and 56 of 100Ω / □ to 1 MΩ / □ operating as the resistors 29 and 30 in FIG. 1, and to the Vdd via the aluminum wiring 60 and the contact holes. A low sheet resistance region 57 that operates as an electrode and a low sheet resistance region 54 that operates as a first electrode 43 constituting the memory element having a metal-insulating film-metal structure shown in FIG. 2 are provided. The low sheet resistance region 54 corresponds to the electrode 14 shown in FIG.
[0083]
A polycrystalline silicon electrode 53 that operates as the second electrode 45 in FIG. 2 is provided on the low sheet resistance region 54. Further, although not shown in FIG. 5, a memory oxide film formed on the surface of the polycrystalline silicon wiring 63 is provided. The low sheet resistance region 54, the memory oxide film, and the polycrystalline silicon electrode 53 constitute a memory element having a metal-insulating film-metal structure. The polycrystalline silicon electrode 53 corresponds to the electrode 13 in FIG.
[0084]
The polycrystalline silicon electrode 53 and the source electrode of the P-channel MOS transistor 61 are connected to Vdd by an aluminum wiring 58 through a contact hole.
[0085]
The low sheet resistance region 54, which is a high concentration impurity region, is connected to the drain electrodes of the P channel MOS transistor 61 and the N channel MOS transistor 62 by an aluminum wiring 59 through a contact hole.
[0086]
Thus, in the embodiment of the present invention, the high sheet resistance regions 55 and 56 of one polycrystalline silicon wiring 63 are used as resistance elements, and the low sheet resistance region 54 is used as the first electrode of the memory element.
As a result, wiring between the resistance element and the memory element can be omitted, so that the area of the semiconductor resistance device can be reduced.
[0087]
In the above-described embodiment of the present invention, the number of memory cells is three, but the number of cells may be increased. By increasing the number of cells, it is possible to further finely adjust the correction amount of the resistance value.
[0088]
An optimum embodiment for implementing a semiconductor resistance device according to a second control method of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram showing a semiconductor resistance device in an embodiment of the present invention. Hereinafter, an embodiment of the present invention will be described with reference to FIG.
[0089]
[Description of Semiconductor Resistance Device: FIG. 7]
As shown in FIG. 7, the semiconductor resistance device of the present invention is composed of four resistors 29, 30, 31, 32 connected in series, a resistor array 8 having one end connected to Vdd, and three resistors in the resistor array 8. Three memory cells 1, 2, 3 connected in parallel to the connection points 33, 34, 35, the address control circuit 4, and a Vm terminal for applying a high negative write voltage Vm for supplying a program voltage from the outside 5, an address signal input terminal 7, and a program mode input terminal 6.
The address control circuit 4 is connected to Vss through a pull-down resistor 36.
[0090]
Memory cells 1, 2, 3 have memory elements 10, 11 that connect their respective electrodes 13, 15, 17 to Vdd and connect electrodes 14, 16, 18 to connection points 33, 34, 35 of resistor array 8. , 12 and the drain electrode connection portions of the P-channel MOS transistors 19, 20, 21 and the N-channel MOS transistors 22, 23, 24, respectively, are connected to the connection points 33, 34, 35 of the resistor array 8. .
The gate electrodes of the P-channel MOS transistors 19, 20 and 21 are connected to signal lines 25, 26 and 27 from the address control circuit 4, respectively. The gate electrodes of the N channel MOS transistors 22, 23, 24 are connected to signal lines 37, 38, 39 from the address control circuit 4, respectively.
[0091]
P-channel MOS transistors 19, 20, and 21 and N-channel MOS transistors 22, 23, and 24 constitute an address transistor.
[0092]
[Description of Memory Element: FIG. 2]
The memory elements 10, 11, and 12 are constituted by memory elements having a read-only metal-insulating film-metal structure that can be electrically written only once. FIG. 2 shows a cross-sectional structure of this metal-insulating film-metal memory element. FIG. 2 is a cross-sectional view showing a memory element according to an embodiment of the present invention.
[0093]
As shown in FIG. 2, a field oxide film 42 is provided on a semiconductor substrate 41, and a first electrode 43 made of polycrystalline silicon is provided on the field oxide film 42.
Further, a memory oxide film 44 that is a thin silicon oxide film formed on the surface of the first electrode 43 and a second electrode 45 made of polycrystalline silicon provided on the memory oxide film 44 are provided. Furthermore, an aluminum wiring 47 for setting the potential of the first electrode 43 and the second electrode 45 is provided through a contact hole provided in the interlayer insulating film 46.
[0094]
As a method of manufacturing a memory element having a metal-insulating film-metal structure in the present invention, polycrystalline silicon constituting a gate electrode in a general complementary field effect transistor (CMOS transistor) manufacturing process is formed on the entire surface, and impurities are formed. This is the same as the processing step up to the injection step.
That is, the gate electrode of the MOS transistor and the first electrode 43 may be formed of the same polycrystalline silicon. Here, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 41 by a chemical vapor deposition apparatus, and pattern formation is not performed.
[0095]
Next, a thin silicon oxide film is formed on the first electrode 43 by thermal oxidation to form a memory oxide film 44. Thereafter, polycrystalline silicon is further formed by chemical vapor deposition, impurity implantation is performed to form a predetermined conductive layer, and a polycrystalline silicon which is the first electrode 43 material as shown in FIG. Patterning is performed so as to leave the second electrode 45 on the silicon film.
[0096]
Next, the first electrode 43 and the gate electrode of the MOS transistor are pattern-formed using a photoetching method. Subsequently, a general CMOS transistor manufacturing process for forming the interlayer insulating film 46 after forming the gate electrode of polycrystalline silicon, forming contact holes, and forming the aluminum wiring 47 is performed.
[0097]
Thus, the patterning of the gate electrode of the MOS transistor and the first electrode 43 is performed after the second electrode 45 is patterned. For this reason, the pattern dimension of the gate electrode of the MOS transistor is not reduced, and there is no generation of etching residue of polycrystalline silicon, which is a material for forming the second electrode 45.
[0098]
In addition, making the memory element before forming the source region and the drain region does not increase the diffusion distance between the source region and the drain region due to heat treatment when forming the memory oxide film 44.
That is, there is no influence on the MOS transistor characteristics due to the formation of the memory element.
[0099]
Information is written in the memory element by setting the potentials of the first electrode 43 and the second electrode 45 so that an electric field of 8 MV / cm or more is applied to the memory oxide film 44. This is performed by causing permanent destruction of the first electrode 43 and the second electrode 45.
[0100]
On the other hand, when the memory oxide film 44 provided between the first electrode 43 and the second electrode 45 is in a potential state that does not cause dielectric breakdown, the first electrode 43 and the second electrode 45 remain in an insulated state. is there.
[0101]
By controlling the potentials of the first electrode 43 and the second electrode 45 in this way, the state can be changed to two stable states, ie, a conductive state and an insulating state, and thus operates as a memory element.
[0102]
[Description of resistance value setting method: FIG. 7]
Next, a method for setting the resistance value of the resistor array 8 of FIG. 7 that meets the specifications after manufacturing the semiconductor integrated circuit device will be described with reference to FIG.
[0103]
The resistance value of the resistance array 8 can be selected from four types of resistance values by bringing one of the memory elements 10, 11, 12 constituting the memory cells 1, 2, 3 into a conductive state.
That is, this corresponds to writing resistance value setting information in the memory elements 10, 11, and 12.
[0104]
To write data to the memory element, first, an external power supply set to the Vss voltage is connected to the Vm terminal 5.
A signal “1” is input to the program mode input terminal 6 to set the address control circuit 4 to the write mode. An address signal is input to the address input terminal 7 to select a write destination memory element.
[0105]
Next, a negative high write voltage (Vm voltage) is applied to the Vm terminal 5 for a predetermined time as the output voltage of the external power supply, and the memory oxide film of the selected memory element is subjected to dielectric breakdown to perform writing.
[0106]
The operation of the P channel MOS transistors 19, 20, 21 and the N channel MOS transistors 22, 23, 24 in the memory cells 1, 2, 3 when the Vm voltage is applied to the Vm terminal 5 is written to the memory element 10. An example of performing the above will be described below.
[0107]
Vdd is applied from the address control circuit 4 via the signal line 25 to the gate electrode of the P channel MOS transistor 19 of the memory cell 1, and the P channel MOS transistor 19 is in the “off” state.
On the other hand, the Vss voltage is applied to the gate electrodes of the P-channel MOS transistors 20 and 21 of the memory cells 2 and 3 via the signal lines 26 and 27 from the address control circuit 4. “On” state.
[0108]
Further, Vdd is applied to the gate electrode of the N channel MOS transistor 22 from the address control circuit 4 via the signal line 37, and the N channel MOS transistor 22 is in the “ON” state.
Further, the Vm voltage is applied to the gate electrodes of the N channel MOS transistors 23 and 24 of the memory cells 2 and 3 via the signal lines 38 and 39 from the address control circuit 4, and the N channel MOS transistors 20 and 21 are connected to “ “Off” state.
[0109]
At this time, the potential of the electrode 14 of the memory element 10 becomes Vm because the P-channel MOS transistor 19 is “off” and the N-channel MOS transistor 22 is “on”.
Therefore, since the potential of the electrode 13 of the memory element 10 is Vdd, information is written by applying a voltage higher than the dielectric breakdown voltage to the memory oxide film.
[0110]
On the other hand, the potentials of the electrodes 16 and 18 of the memory elements 11 and 12 are Vdd because the P-channel MOS transistors 20 and 21 are “on” and the N-channel MOS transistors 23 and 24 are “off”.
Further, since the potentials of the electrodes 15 and 17 of the memory elements 11 and 12 are Vdd, a voltage higher than the dielectric breakdown voltage is not applied to the memory oxide film, so that it remains in a non-written state.
[0111]
FIG. 10 shows the time course of the potentials of the electrodes 14, 16 and 18 of the memory elements 10, 11 and 12. In FIG. 10, the potential change of the electrode 14 corresponds to the broken line 65, and the potential change of the electrode 16 and the electrode 18 corresponds to the broken line 66. The origin of the time axis is when the signal “1” is input to the program mode input terminal.
An address for selecting the memory cell 1 is set at time t0. At time t1, the external power source is switched from Vss to Vm voltage. At time t2, the memory oxide film of the memory element 10 breaks down and writing is completed. At time t3, the external power source is switched from the Vm voltage to Vss. In FIG. 10, Vbr represents the breakdown voltage.
[0112]
The electrode 14 of the selected memory element is Vss from time t0 to time t1, Vm voltage from time t1 to time t2, and the memory oxide film of the memory element 10 is broken down after time t2. Since it conducts, Vdd is approximately indicated.
On the other hand, the electrodes 16 and 18 of the unselected memory elements 11 and 12 always show Vdd during the write mode period.
[0113]
Next, the operation of the semiconductor resistance device of the present invention after setting the resistance value will be described.
The connection between the Vm terminal and the external power supply is disconnected, and the potential of the Vm terminal is set to Vss through the pull-down resistor 36.
The signal “0” is input to the program mode input terminal to set the address control circuit 4 to the normal mode, and the P channel MOS transistors 19, 20, and 21 are connected to the gate electrodes from the address control circuit 4 through the signal lines 25, 26, and 27. Vdd is applied to P-channel MOS transistors 19, 20, and 21 in the “off” state.
[0114]
On the other hand, Vss is applied from the address control circuit 4 to the gate electrodes of the N-channel MOS transistors 22, 23, and 24 via the signal lines 37, 38, and 39, thereby turning them off.
[0115]
Since writing is performed on the memory element 10, the memory oxide film of the memory element 10 is broken down, and the electrode 13 and the electrode 14 to which Vdd is applied are in a conductive state.
Therefore, a path through which current flows is formed through the memory element 10 to the connection point 33 between the resistor 29 and the resistor 30 of the resistor array 8.
[0116]
On the other hand, since the memory oxide films of the memory elements 11 and 12 are not dielectrically broken, the electrode 15 and the electrode 16 and the electrode 17 and the electrode 18 are in a non-passing state.
[0117]
The resistance value R0 of the resistance array 8 at this time is obtained by calculating the resistance values of the resistors 29, 30, 31, and 32 as R1, R2, R3, and R4 and the resistance value after writing of the memory element 10 as R5.
R0 = R2 + R3 + R4 + R5 · R1 / (R1 + R5)
It becomes.
[0118]
As is apparent from the equation described before obtaining the adjusted resistance value, the resistance value R5 of the memory element 10 is sufficiently larger than the resistance values R1, R2, R3, and R4 of the resistors 29, 30, 31, and 32. R0 which is the resistance value of the resistance array 8 can be approximated to (R2 + R3 + R4).
[0119]
Although the case where information is written to the memory element 10 has been described here, the case where data is written to the memory elements 11 and 12 can be performed in the same manner, and thus detailed description thereof is omitted.
[0120]
Therefore, in order to expand the setting range of the resistance value of the semiconductor resistance device and make the setting of the resistance value more accurate, it is necessary to reduce the resistance value of the memory element after writing and further reduce its variation.
[0121]
[Description of resistance value distribution of memory element after writing: FIG. 3]
Next, in the memory element in which the film thickness of the memory oxide film 44 shown in FIG. 2 is 5 nm, the gate width dimension of the P-channel MOS transistor of the memory cell is set under the write condition of Vm voltage of minus 10 V and Vm application time of 1 ms. FIG. 3 shows a distribution of resistance values of the memory element after writing when the amount of current passing through the memory element is changed when Vm is applied.
[0122]
In the graph of FIG. 3, the resistance value of the memory element is measured by applying a voltage of 1 V to the memory element after writing, measuring the flowing current value, and converting it to a resistance value.
[0123]
As is apparent from the graph of FIG. 3, when the current value passing through the memory element is 2 mA, the resistance value is distributed in the range of 600Ω to 1 KΩ. The average value of the resistance is 750Ω.
On the other hand, when the current value is 200 μA, the resistance value is distributed from 1.5 KΩ to 11 KΩ, the average resistance value is 3.73 KΩ, the distribution is shifted to the high resistance side compared to 2 mA, and The variation is also great.
[0124]
Next, during normal operation, the voltage applied to the memory element changes depending on the resistance value of the resistor array 8. Therefore, in order to set the resistance value accurately, the resistance value of the memory element after writing needs to have a small voltage dependency. Therefore, the voltage dependence of the resistance value of the memory element after writing is shown in the graph of FIG.
[0125]
[Description of voltage dependence of resistance value of memory element after writing: FIG. 4]
In FIG. 4, curves 50, 51, and 52 indicate voltage dependences when the resistance value after writing of the memory element at 1 V is 800Ω, 10KΩ, and 50KΩ, respectively.
As is apparent from this graph, the smaller the resistance value after writing at 1 V, the smaller the change in resistance value due to voltage. Particularly, in the curve 50, no change in resistance value is observed. On the other hand, in the curve 52, when the applied voltage becomes smaller than 0.5V, the resistance value remarkably increases depending on the voltage.
[0126]
From the graphs of FIG. 3 and FIG. 4, the write condition of the memory element is that the current value penetrating the memory element when Vm is applied is 2 mA or more. By writing to the memory element under this condition, the resistance value of the memory element after writing is distributed to 1 KΩ or less, and there is almost no variation.
Further, no voltage dependence is observed in the resistance value of the memory element after writing. This indicates that the resistance value of the resistor array 8 shown in FIG. 7 can be adjusted accurately and stably.
[0127]
In the above-described embodiment of the present invention, the number of memory cells is three, but the number of cells may be increased. By increasing the number of cells, it is possible to further finely adjust the correction amount of the resistance value.
[0128]
An optimum embodiment for implementing a semiconductor resistance device according to a third control method of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram showing a semiconductor resistance device in an embodiment of the present invention. Hereinafter, an embodiment of the present invention will be described with reference to FIG.
[0129]
[Description of Semiconductor Resistance Device: FIG. 8]
As shown in FIG. 8, the semiconductor resistance device of the present invention comprises four resistors 29, 30, 31, and 32 connected in series, a resistor array 8 having one end connected to Vdd, and three connections in the resistor array 8. Three memory cells 1, 2, 3 connected in parallel to the points 33, 34, 35, an address control circuit 4, a Vm terminal 5 for applying a program voltage Vm, an address signal input terminal 7, and a program mode An input terminal 6 and a P-channel MOS transistor 40 having a drain connected to the end point 9 of the resistor array 8 and a source connected to Vdd are configured.
The gate electrode of the P channel MOS transistor 40 is connected to the signal line 48 from the address control circuit 4. The address control circuit 4 is connected to Vss through a pull-down resistor 36.
[0130]
Memory cells 1, 2, 3 have memory elements 10, 11, 12 connecting electrodes 13, 15, 17 to Vdd and electrodes 14, 16, 18 to connection points 33, 34, 35 of resistor array 8, respectively. The connection portions of the drain electrodes of the N channel MOS transistors 22, 23, 24 are connected to the connection points 33, 34, 35 of the resistor array 8.
The gate electrodes of the N channel MOS transistors 22, 23, 24 are connected to signal lines 37, 38, 39 from the address control circuit 4, respectively. The N-channel MOS transistors 22, 23, and 24 constitute an address transistor.
[0131]
The memory elements 10, 11, and 12 are constituted by memory elements having a read-only metal-insulating film-metal structure that can be electrically written only once.
Since the structure, manufacturing method, and writing method of the memory element in the present invention have been described above, detailed description thereof is omitted here.
[0132]
Next, a method for setting the resistance value of the resistor array 8 of FIG. 8 that meets the specifications after manufacturing the semiconductor integrated circuit device will be described with reference to FIG.
[0133]
The resistance value of the resistance array 8 can be selected from four types of resistance values by bringing one of the memory elements 10, 11, 12 constituting the memory cells 1, 2, 3 into a conductive state.
That is, this corresponds to writing resistance value setting information in the memory elements 10, 11, and 12.
[0134]
To write data to the memory element, first, an external power supply set to the Vss voltage is connected to the Vm terminal 5. A signal “1” is input to the program mode input terminal 6 to set the address control circuit 4 to the write mode. When the address control circuit 4 is in the write mode, Vss is applied to the gate electrode of the P-channel MOS transistor 40 via the signal line 48 to always keep the P-channel MOS transistor 40 in the “ON” state and the potential at the end 9 of the resistor array 8. Is set to Vdd.
Further, an address signal is input to the write address input terminal 7 to select a write destination memory element.
[0135]
Next, the output voltage of the external power supply is set to the write voltage Vm and applied to the Vm terminal 5 for a predetermined time, and the memory oxide film of the selected memory element is subjected to dielectric breakdown and writing is performed.
At this time, the Vm voltage is also applied to the gate electrode of the P-channel MOS transistor 40.
[0136]
The operation state of the N-channel MOS transistors 22, 23, 24 in the memory cells 1, 2, 3 when the Vm voltage is applied to the Vm terminal 5 will be described below by taking as an example the case of writing to the memory element 10. To do.
[0137]
Vdd is applied from the address control circuit 4 to the gate electrode of the N channel MOS transistor 22 of the memory cell 1 via the signal line 37, and the N channel MOS transistor 22 is in the "ON" state.
On the other hand, the Vm voltage is applied to the gate electrodes of the N channel MOS transistors 23 and 24 of the memory cells 2 and 3 through the signal lines 38 and 39 from the address control circuit 4, and the N channel MOS transistors 23 and 24 are connected to the “ “Off” state.
[0138]
At this time, the potential of the electrode 14 of the memory element 10 becomes Vm because the N-channel MOS transistor 22 is in the “on” state.
Therefore, since the potential of the electrode 13 of the memory element 10 is Vdd, information is written by applying a voltage higher than the dielectric breakdown voltage to the memory oxide film.
[0139]
On the other hand, the potentials of the electrodes 16 and 18 of the memory elements 11 and 12 are such that the potential Vm at the connection point 33 and the potential Vdd at the end point 9 of the resistor array 8 are the same. The potential is divided by resistance.
[0140]
When the resistance values of the resistors 29, 30, 31, and 32 constituting the resistor array 8 are R1, R2, R3, and R4, the potential of the electrode 16 of the memory cell 11 is
{(R3 + R4) / (R2 + R3 + R4)}. (Vm−Vdd) + Vdd
Thus, the potential of the electrode 218 of the memory cell 212 is
R4 / (R2 + R3 + R4). (Vm−Vdd) + Vdd
Thus, since a voltage higher than the dielectric breakdown voltage is not applied to the memory oxide films of the memory elements 11 and 12, the memory elements 11 and 12 remain in a non-written state.
[0141]
FIG. 11 shows the time course of the potentials of the electrodes 14, 16 and 18 of the memory cells 10, 11 and 12. 11, the broken line 67 corresponds to the potential change of the electrode 14, the broken line 68 corresponds to the potential change of the electrode 16, and the broken line 69 corresponds to the potential change of the electrode 18. The origin of the time axis is when the signal “1” is input to the program mode input terminal.
An address for selecting the memory cell 1 is set at time t0. At time t1, the external power source is switched from Vss to Vm. At time t2, the memory oxide film of the memory element 10 breaks down and writing is completed. At time t3, the external power source is switched from Vm to Vss. In FIG. 11, R16 and R18 indicate the ratio of resistance division of the connection points 33 and 34 of the resistor array 8. Vbr indicates the breakdown voltage.
[0142]
From time t0 to time t1, the electrode 14 of the selected memory element 10 is at the Vss potential, and no writing is performed on the memory element 10, so that the electrodes 16 and 18 of the unselected memory element 11 and the unselected memory element 12 The potential difference between the potential Vss at the connection point 33 of the array 8 and the potential Vdd at the end point 9 becomes a potential obtained by dividing the resistance at the connection point 34 and the connection point 35.
[0143]
Similarly, from time t 1 to time t 2, the electrode 14 of the selected memory element 10 is at Vm potential, and no writing is performed on the memory element 10, so that the electrodes 16 and 18 of the unselected memory elements 11 and 12 are connected to the resistor array 8. The potential difference between the potential Vm at the connection point 33 and the potential Vdd at the end point 9 becomes the potential obtained by dividing the resistance at the connection points 34 and 35.
After time t2, since the memory oxide film of the memory element 10 is broken down, the electrode 13 and the electrode 14 are brought into conduction, so that Vdd is approximately indicated. Similarly, since the potential at the connection point 33 is also Vdd, the potential difference from the end point 9 of the resistor array 8 is eliminated, indicating Vdd.
[0144]
Next, the operation of the semiconductor resistance device of the present invention after setting the resistance value will be described. The connection between the Vm terminal and the external power supply is disconnected, and the potential of the Vm terminal is set to Vss through the pull-down resistor 36.
A signal “0” is input to the program mode input terminal to set the address control circuit 4 to the normal mode, and Vdd is applied to the gate electrode from the address control circuit 4 through the signal line 48 to the P-channel MOS transistor 40. The channel MOS transistor 19 is turned off.
Further, Vss is applied from the address control circuit 4 to the gate electrodes of the N-channel MOS transistors 22, 23, and 24 via the signal lines 37, 38, and 39, thereby turning them off.
[0145]
Since writing is performed on the memory element 10, the memory oxide film of the memory element 10 is broken down, and the electrode 13 and the electrode 14 to which Vdd is applied are in a conductive state.
Therefore, a path through which current flows is formed through the memory element 10 to the connection point 33 between the resistor 29 and the resistor 30 of the resistor array 8.
[0146]
On the other hand, since the memory oxide films of the memory elements 11 and 12 are not dielectrically broken, the electrode 15 and the electrode 16 and the electrode 17 and the electrode 18 are in a non-passing state.
[0147]
The resistance value R0 of the resistance array 8 at this time is obtained by calculating the resistance value after writing of the memory element 10 as R5.
R0 = R2 + R3 + R4 + R5 · R1 / (R1 + R5)
It becomes.
[0148]
As is apparent from the above equation for obtaining the adjusted resistance value, the resistance value R5 of the memory element 10 is sufficiently higher than the resistance values R1, R2, R3, and R4 of the resistors 29, 30, 31, and 32. When it is small, R0 which is the resistance value of the resistor array 8 can be approximated to (R2 + R3 + R4).
[0149]
Although the case where information is written to the memory element 10 has been described here, the case where data is written to the memory elements 11 and 12 can be performed in the same manner, and thus detailed description thereof is omitted.
[0150]
In the above-described embodiment of the present invention, the number of memory cells is three, but the number of cells may be increased.
By increasing the number of cells, it is possible to further finely adjust the correction amount of the resistance value.
[0151]
【The invention's effect】
As is apparent from the above description, according to the semiconductor resistance device of the present invention, the resistance value is corrected after the resistance that fluctuates due to manufacturing variations is formed, and is most suitable for the specifications of the semiconductor integrated circuit device. The resistance value can be set.
[0152]
Furthermore, in the semiconductor resistance device of the present invention, one memory element that obtains a resistance value that meets the specifications is dielectrically broken and turned on to form a path through which the current of the resistor array flows directly. The resistance value can be set to an optimum value without consumption of current necessary for the operation of these circuits.
[0153]
The memory element constituting the semiconductor resistance device of the present invention adopts a polycrystalline silicon two-layer structure using polycrystalline silicon in which the first electrode is used as the gate electrode of the MOS structure. Therefore, the manufacturing process is simple and does not affect the peripheral MOS transistor characteristics.
[0154]
Further, the write current required for reducing the variation in resistance value of the memory element after writing is as low as 2 mA, and the write voltage required for causing dielectric breakdown in the time of 1 msec in the memory oxide film 5 nm is as low as 10 V. There is no need to increase the breakdown voltage of the peripheral semiconductor elements.
Furthermore, there is no generation of silicon scraps or deterioration of the passivation film, and characteristics of the semiconductor integrated circuit device do not deteriorate.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a semiconductor resistance device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a memory element of a metal-insulating film-metal structure constituting the semiconductor resistance device in the embodiment of the present invention.
FIG. 3 is a graph showing a distribution of a through current value and a resistance value after writing of a memory element having a metal-insulating film-metal structure constituting the semiconductor resistance device according to the embodiment of the present invention.
FIG. 4 is a graph showing voltage dependency of resistance value after writing of a memory element having a metal-insulating film-metal structure constituting the semiconductor resistance device according to the embodiment of the present invention;
FIG. 5 is a plan view showing a planar pattern shape when the resistance coat of the semiconductor resistance device according to the first embodiment of the present invention is made of polycrystalline silicon.
FIG. 6 is a circuit diagram showing a semiconductor resistance device in the prior art.
FIG. 7 is a circuit diagram showing a semiconductor resistance device according to a second embodiment of the present invention.
FIG. 8 is a circuit diagram showing a semiconductor resistance device according to a third embodiment of the present invention.
FIG. 9 is a graph showing temporal changes in the potential of the first electrode of the memory element in the write mode according to the first embodiment of the present invention.
FIG. 10 is a graph showing temporal changes in the potential of the first electrode of the memory element in the write mode according to the second embodiment of the present invention.
FIG. 11 is a graph showing a change with time of the potential of the first electrode of the memory element in the write mode in the third embodiment of the present invention;
[Explanation of symbols]
1 Memory cell
4 Address control circuit
5 Vm terminal
6 Program mode input terminal
7 Address signal input terminal
8 Resistance array
10 Memory elements
19 P-channel MOS transistor
22 N-channel MOS transistor
20 resistor array

Claims (6)

A resistor array configured by connecting a plurality of resistors in series , one end of which is connected to a predetermined potential ;
A plurality of memory elements, one end of which is connected to a connection point between a plurality of resistors of the resistor array and the other end of which is connected to the predetermined potential, and for selectively writing information to each of the plurality of memory elements and a memory cell to have a plurality of address transistor,
A semiconductor resistance device, wherein information is written in the memory element to make the memory element a resistance, and a resistance value of the resistor array connected in parallel is selected. The resistor array has alternately a plurality of low sheet resistance regions and a plurality of high sheet resistance regions respectively constituting the plurality of resistors on a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. The semiconductor resistance device according to claim 1, wherein: The memory device includes a polycrystalline silicon wiring provided on the field oxide film on a semiconductor substrate, the polycrystalline silicon wiring to provide a memory oxide film, a polysilicon electrode provided on the memory oxide film, electrical 2. The semiconductor resistance device according to claim 1 , wherein the memory element is a writable memory element only once. A resistor array configured by connecting a plurality of resistors in series , one end of which is connected to the high potential of the driving voltage of the semiconductor device ;
Information is selectively written to each of the plurality of memory elements , one end of which is connected to a connection point between the resistors of the resistor array and the other end of which is connected to the high potential of the driving voltage. A memory cell having a plurality of address transistors ,
The memory element is provided on a field oxide film on a semiconductor substrate, and includes a first electrode connected to connection points of a plurality of resistors of the resistor array, a memory oxide film provided on a surface of the first electrode, , the memory oxide film only in contact, and a second electrode connected to the high potential driving voltage, a control method of a semiconductor resistor device that only electrically once writable memory device,
By applying a write voltage to the first electrode of the memory element to which information is written, the memory oxide film is caused to break down and become a resistor, and a constant voltage is applied to the first electrode of the non-selected memory element. A method of controlling a semiconductor resistance device, wherein the resistance value of a resistance array connected in parallel is selected by applying and blocking writing. The constant voltage control method of a semiconductor resistor device according to claim 4, characterized in that a high potential or a high potential and the smaller voltage than the breakdown voltage between the write voltage of the drive voltage of the drive voltage. A resistor array configured by connecting a plurality of resistors in series , one end of which is connected to the high potential of the driving voltage of the semiconductor device ;
A P-channel MOS transistor having a drain connected to the other end of the resistor array and a source connected to the high potential of the drive voltage;
Information is selectively written to each of the plurality of memory elements , one end of which is connected to a connection point between the resistors of the resistor array and the other end of which is connected to the high potential of the driving voltage. A memory cell having a plurality of address transistors ,
The memory element is provided on a field oxide film on a semiconductor substrate, and includes a first electrode connected to connection points of a plurality of resistors of the resistor array, a memory oxide film provided on a surface of the first electrode, , the memory oxide film only in contact, and a second electrode connected to the high potential driving voltage, a control method of a semiconductor resistor device that only electrically once writable memory device,
The memory oxide film as a resistor allowed to reach breakdown by the first electrode of the memory element for writing information to apply a write voltage, the both ends of the resistor array by a high potential of the driving voltage, the first electrode of the memory element of the non-selected application of a high potential and a voltage less than the resistance divided breakdown voltage by resistors constituting the resistor array to the potential difference between the write voltage of the driving voltage, writing prevention And selecting a resistance value of the resistor array connected in parallel.

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