JPH09283717A - Semiconductor resistance device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor resistance device where no silicon particles are produced, no deterioration in a passivation film is caused, no high breakdown voltage is required for elements of a semiconductor integrated circuit with a simple manufacture process, without the need for a read circuit and for any current consumption to read written information. SOLUTION: The device is provide with a resistor array 9 consisting of plural resistors connected in series, memory cells (1-4) each connected in parallel with each resistor, each memory cell is made up of a memory element (10) of a metal-insulation film-metal structure and a MOS transistor(TR). First and second electrodes are electrically connected to each other by applying an overvoltage externally to a selected memory element to destroy permanently the element, and a current is supplied only through the conductive memory element 10. Since selection information of the element corresponds directly to a path through which a current flows to the resistor array 9, the resistance is set at an optimum value without the need for a read circuit and a data latch circuit and without consumption of a current required for the operation of the circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor resistance device, and in particular, a yield is obtained by correcting manufacturing variations such as resistance and changing operating conditions by using a memory element which can be written only once in a semiconductor integrated circuit. Regarding improvement and stabilization of performance.

[0002]

2. Description of the Related Art The prior art in a semiconductor resistance device equipped with a circuit for adjusting the resistance value of a resistance array based on information stored in a laser fuse blown programmable read only memory (PROM) is shown in FIG. Shown in the figure.

As shown in FIG. 6, the semiconductor resistance device includes eight resistors 81, 82, 83, 84, 85, which are connected in series.
86, 87, 88 and eight MOS transistors 91, 92, 93, 94, 9 connected in parallel to these eight resistors.
5, 96, 97, 98 and a decoder 80.

The memory block 70 includes three laser fuse blown type PROs, one ends of which are connected to the high potential of the power source.
M elements 71, 72, 73 and comparison resistors 74, 75, 76 having one end connected to the laser fuse blown type PROM element and the other end connected to the low potential of the power source, and compared with the laser fuse blown type PROM element It is composed of inverters 77, 78, 79 whose output voltage is determined by the potential at the connection point of the resistors.

In the semiconductor resistance device, the outputs from the inverters 77, 78 and 79 of the memory block 70 are decoder 80.
To the MOS transistors 91, 92, 93, 9
By turning on any of 4, 95, 96, 97, 98, eight kinds of resistance values can be selected.

For example, if the laser fuse blowing type PROM elements 71, 77, 73 of the memory block 70 are not blown, the output voltages of the inverters 77, 78, 79 are all at a low potential of the power supply voltage, and the MOS transistor 91 is turned on. The decoder 80 is controlled to be in the "on" state. As a result, the semiconductor resistance device has the resistance value of the resistor 81.

Further, when the laser fuse blowout type PROM elements 72 and 73 are blown, the inverter 7
The output of 7 becomes the low potential of the power supply voltage, and the inverter 78,
The output of 79 becomes the high potential of the power supply voltage, and the decoder 80
To turn on the MOS transistor 94 via
The resistance value is a value obtained by adding the resistance 81, the resistance 82, the resistance 83, and the resistance 84.

As the memory element which can be written only once, in addition to the laser fuse fusing type PROM element described above, a PR such as an electric fuse fusing type or a junction breaking type is also used.
An OM element can be used.

[0009]

However, in order to read the information stored in the memory block 70 and judge the state of each memory element, as shown in FIG. 6, the comparison resistors 74, 75 and 76 and the inverter 77 are used. , 78, 79, which increases the area of the semiconductor integrated circuit.

Furthermore, the power supply and the laser fuse PRO
Since the M elements 71, 72 and 73 and the comparison resistors 74, 75 and 76 form a closed circuit, a current always flows. Therefore, in order to suppress the current consumption of the semiconductor integrated circuit, it is necessary to add a data latch circuit, which is not shown in FIG.

Furthermore, a laser fuse blown type PRO
The M element performs writing of information by irradiating laser light. Therefore, a dedicated device for generating laser light is required, and further, it is necessary to open a passivation film on the fuse PROM element to form an incident window for laser light. For this reason, there are disadvantages that the area of the semiconductor integrated circuit becomes large, the cost becomes high, and the mounting form is limited in order to write information after mounting.

Further, in the fuse-cut PROM element of the electric fuse, information is written by physically breaking polysilicon or the like which constitutes the PROM element. Therefore, there are problems such as generation of silicon scraps and deterioration of the passivation film.

In the junction breakdown type PROM element, information is written by passing a current to break the junction.
For this reason, since a large amount of current is required for writing information, the voltage applied at the time of writing is large, and in order to prevent the leakage of the writing current, the elements that form the semiconductor integrated circuit must have a breakdown voltage equal to or higher than the writing voltage. And
Therefore, there is a drawback in that the manufacturing process for forming is complicated.

In the electric fuse blowout type PROM element and the junction breakdown type PROM element, a high voltage is applied to the memory element, and most of the voltage is applied to the memory element in the path in which a large current flows in the memory element by thermal destruction. By doing so, information is written. Therefore, the size of the resistance value that can be inserted between the memory element and the write voltage terminal is limited.

Therefore, it is difficult to select and write an electric fuse blowing type PROM element or a junction breakdown type PROM element by using a general MOS transistor as an address transistor.

Therefore, an object of the present invention is to prevent the generation of silicon scraps and the deterioration of the passivation film, to increase the withstand voltage of the elements constituting the semiconductor integrated circuit, to simplify the manufacturing process, and to provide the read circuit. Another object of the present invention is to provide a semiconductor resistance device that does not consume current for reading written information.

[0017]

In order to achieve the above object, the semiconductor resistance device of the present invention adopts the following structure.

The semiconductor resistance device of the present invention includes a resistance array in which a plurality of resistances are connected in series, a memory element connected in parallel with the resistances of the resistance array, and a plurality of address transistors for selectively writing information in the memory element. And a resistance value of the resistor array is selected by writing information in the memory element.

In the semiconductor resistance device of the present invention, a resistor array in which a plurality of resistors are connected in series, an electrically writable memory element connected in parallel with the resistors of the resistor array, and information is selected in the memory element. And a plurality of address transistors for writing data selectively, and the resistance value of the resistance array is selected by writing information in the memory element.

The semiconductor resistance device of the present invention includes a resistance array in which a plurality of resistances are connected in series, and a memory element having a metal-insulating film-metal structure that is electrically writable only once and is connected in parallel with the resistances of the resistance array. A plurality of address transistors for selectively writing information in the memory element are provided, and the resistance value of the resistor array is selected by writing the information in the memory element.

The semiconductor resistance device of the present invention comprises a resistance array in which a plurality of resistances are connected in series, a memory element connected in parallel with the resistances of the resistance array, and a plurality of address transistors for selectively writing information in the memory element. The resistance array has a plurality of low sheet resistance regions and a plurality of high sheet resistance regions in the polycrystalline silicon wiring provided on the field oxide film on the semiconductor substrate, and by writing information in the memory element, the resistance array of It is characterized by selecting a resistance value.

In the semiconductor resistance device of the present invention, a resistor array in which a plurality of resistors are connected in series, an electrically writable memory element connected in parallel with the resistors of the resistor array, and information is selected in the memory element. And a plurality of address transistors for writing data, the resistance array having a plurality of low sheet resistance regions and a plurality of high sheet resistance regions in a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. The resistance value of the resistor array is selected by writing information in the.

The semiconductor resistance device of the present invention includes a resistance array in which a plurality of resistances are connected in series, and a memory element having a metal-insulating film-metal structure that is electrically writable only once and is connected in parallel with the resistances of the resistance array. , A plurality of address transistors for selectively writing information in a memory element, and the resistance array has a plurality of low sheet resistance regions and high sheet resistance regions in polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. And a resistance value of the resistance array is selected by writing information in the memory element.

In the semiconductor resistance device of the present invention, a resistance array in which a plurality of resistances are connected in series, an electrically writable memory element connected in parallel with the resistances of the resistance array, and information is selected in the memory element. A plurality of address transistors for selectively writing, the memory element has a first electrode provided on a field oxide film on a semiconductor substrate, a memory oxide film provided on a surface of the first electrode, and an upper surface of the first electrode. It has a second electrode in contact with only the memory oxide film to be provided, and the resistance value of the resistor array is selected by writing information in the memory element.

In the semiconductor resistance device of the present invention, a resistance array in which a plurality of resistances are connected in series, an electrically writable memory element connected in parallel with the resistances of the resistance array and information is selected for the memory element. And a plurality of address transistors for writing data, the resistance array having a plurality of low sheet resistance regions and a plurality of high sheet resistance regions in a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. Comprises a first electrode provided on the field oxide film on the semiconductor substrate, a memory oxide film provided on the surface of the first electrode, and a second electrode contacting only the memory oxide film provided on the upper surface of the first electrode. The resistance value of the resistor array is selected by writing information in the memory element.

In the semiconductor resistance device of the present invention, a resistance array in which a plurality of resistances are connected in series, an electrically writable memory element connected in parallel with the resistances of the resistance array, and information is selected in the memory element. And a plurality of address transistors for writing data, and the resistance array is formed by a plurality of low sheet resistance regions and a plurality of high sheet resistance regions in a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. Has a polycrystalline silicon wiring provided on the field oxide film on the semiconductor substrate, a memory oxide film provided on the polycrystalline silicon wiring, and a polycrystalline silicon electrode provided on the memory oxide film provided on the polycrystalline silicon wiring. The resistance value of the resistor array is selected by writing information in the memory element.

In the semiconductor resistance device of the present invention, a resistance array in which a plurality of resistances are connected in series, an electrically writable memory element connected in parallel with the resistances of the resistance array and information is selected in the memory element. And a plurality of address transistors for writing data, and the resistance array is composed of a plurality of low sheet resistance regions and a plurality of high sheet resistance regions on a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. Is polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate, a memory oxide film provided on the polycrystalline silicon wiring, and polycrystalline silicon provided on a memory oxide film provided on a low sheet resistance region of the polycrystalline silicon wiring. And a resistance value of the resistance array is selected by writing information in the memory element.

In the semiconductor resistance device of the present invention, a user externally attaches to a memory oxide film, which is connected in parallel with the resistance of the resistance array and insulates the first electrode and the second electrode of an arbitrary memory element. By forcibly applying an overvoltage to cause permanent breakdown, the first electrode and the second electrode are brought into conduction. Then, the resistance value of the resistance array can be arbitrarily selected by setting the state in which the current flows through the memory element in the conductive state.

Therefore, after the semiconductor integrated circuit is manufactured, the selection information of the resistor array is stored in the memory element that obtains the resistance value that meets the specifications. Since this selection information directly forms a path through which the current of the resistor array flows, a read circuit and a data latch circuit, which are conventionally required, are not required, and the semiconductor resistance device of the present invention consumes the current required for the operation of these circuits. Of course, the resistance value can be set to the optimum value.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the semiconductor resistance device of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor resistance device according to an embodiment of the present invention. An embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 1, the semiconductor resistance device of the present invention has a resistor array 9 in which five resistors 33, 34, 35, 36, 37 are connected in series, and a resistor 3 constituting the resistor array 9.
Three memory elements 1, 2, 3, 4 connected in parallel to 3, 34, 35, 36 and five address transistors 23, 24, 2 for selectively writing information into the memory elements.
5, 26, 27, an address control circuit 5, a Vm terminal 6 for applying a high negative write voltage for externally supplying a program voltage, an address signal input terminal 8, and a program mode input terminal 7. To do. The potential of the Vm terminal 6 becomes a low potential (hereinafter referred to as Vss) of the power source of the semiconductor integrated circuit through the pull-down resistor 38 when the external power source is not connected.

N-channel MOS transistors are used as the address transistors 23, 25 and 27, P-channel MOS transistors are used as the address transistors 24 and 26, and the memory elements 1, 2, 3 and 4 are respectively P-type.
A channel MOS transistor and an N channel MOS transistor are connected in series. The gate electrodes of the address transistors 23, 24, 25, 26, 27 are signal lines 28, 29, 30, 3 from the address control circuit 5.
1 and 32, respectively.

A resistor 33 and a resistor 3, one end of which is connected to a high potential (hereinafter referred to as Vdd) of the power source of the semiconductor integrated circuit.
Address transistor 23 connected to connection point 18 with 4
Must necessarily use an N-channel MOS transistor in order to selectively write information in the memory device 1. Further, in order to prevent erroneous writing to the non-selected memory element, the semiconductor resistance device of the present invention comprises an even number of memory elements, and the address transistors connected to both ends of the memory element array connected in series are N-channel MOS transistors. To use.

Each of the memory elements 1, 2, 3, and 4 is composed of a memory element having a read-only metal-insulating film-metal structure that can be electrically written only once. FIG. 2 shows a cross-sectional structure of the memory element having the metal-insulating film-metal structure. FIG. 2 is a sectional view showing a memory device according to an embodiment of the present invention.

As shown in FIG. 2, a field oxide film 42 is provided on the semiconductor substrate 41, and a first electrode 43 made of polycrystalline silicon is provided on the field oxide film 42. Further, a memory oxide film 44, which is a thin silicon oxide film formed on the surface of the first electrode 43, and a second electrode 45 made of polycrystalline silicon provided on the memory oxide film 44 are provided. Furthermore, the first electrode 43 and the second electrode 43 are formed through a contact hole provided in the interlayer insulating film 46.
And aluminum wiring 47 for setting the potential of the electrode 45.

As a method of manufacturing a memory element having a metal-insulating film-metal structure according to the present invention, polycrystalline silicon forming a gate electrode in a general complementary field effect transistor (CMOS transistor) manufacturing process is formed on the entire surface. However, the processing steps up to the impurity implantation step are the same. That is, the gate electrode of the MOS transistor and the first electrode 4
3 may be made of the same polycrystalline silicon. Here, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 41 by a chemical vapor deposition apparatus, and no pattern is formed.

Then, a silicon oxide film having a small film thickness is formed on the first electrode 43 by a thermal oxidation process to form a memory oxide film 44. After that, polycrystalline silicon is further formed by a chemical vapor deposition method, impurities are implanted to form a predetermined conductive layer, and a photoetching method is used to form a polycrystalline material of the first electrode 43 as shown in FIG. Second on top of silicon film
Patterning is performed so that the electrode 45 of FIG.

Next, a first photoetching method is used.
The electrode 43 and the gate electrode of the MOS transistor are patterned. Subsequently, a general CMOS transistor manufacturing process of forming an interlayer insulating film 46 after forming a gate electrode of polycrystalline silicon, forming a contact hole, and forming an aluminum wiring 47 is performed.

In this way, the patterning of the gate electrode of the MOS transistor and the first electrode 43 is carried out by the second electrode 4
This is done after patterning No. 5. Therefore M
The pattern size of the gate electrode of the OS transistor is not thin, and the etching residue of polycrystalline silicon, which is the material for forming the second electrode 45, is not generated.

In addition, forming the memory element before forming the source region and the drain region does not increase the diffusion distance between the source region and the drain region due to the heat treatment when forming the memory oxide film 44. That is, there is no influence on the MOS transistor characteristics due to the fabrication of the memory element.

When writing information to the memory element, the potentials of the first electrode 43 and the second electrode 45 are set to the memory oxide film 44.
Is set so that an electric field of 8 MV / cm or more is applied to the memory oxide film 44 so that the memory oxide film 44 is permanently destroyed and the first electrode 43 and the second electrode 45 are brought into conduction.

On the other hand, in a potential state in which the memory oxide film 44 provided between the first electrode 43 and the second electrode 45 does not cause dielectric breakdown, the first electrode 43 and the second electrode 45 are in the insulated state. It remains.

In this way, the first electrode 43 and the second electrode 4 are
By controlling the potential with respect to 5 it is possible to change to two stable states, a conducting state and an insulating state, so that it operates as a memory element.

Next, a method of setting the resistance value of the resistor array 9 of FIG. 1 which meets the specifications after manufacturing the semiconductor integrated circuit device will be described with reference to FIG.

The resistance value of the resistor array 9 is the memory element 1,
16 types of resistance values can be selected by setting 2, 3, and 4 to the conductive state. That is, this corresponds to writing the resistance value setting information in the memory elements 1, 2, 3, and 4.

To write data to the memory device, first, an external power supply whose output voltage is set to Vss is used as the Vm terminal 6
Connect to. Signal "1" at program mode input terminal 7
Is input to set the address control circuit 5 to the write mode. An address signal is input to the address input terminal 7 to select a memory element as a writing destination.

Next, a high negative write voltage (hereinafter referred to as Vm voltage) is output from the output voltage of the external power source for a predetermined time V.
The voltage is applied to the m terminal 6 and the memory oxide film of the selected memory element is brought to a dielectric breakdown and writing is performed.

Next, when the Vm voltage is applied to the Vm terminal 6, the address transistors 23, 24, 25,
The operation states of 26 and 27 will be described by taking as an example the case of writing to the memory elements 1, 2, 3, and 4, respectively.

When writing to the memory cell 1,
The Vdd and Vm voltages are applied to the gate electrodes of the address transistors 23 and 24 from the address control circuit 5 via the signal lines 28 and 29, and the address transistors 23 and 24 are in the "on" state. On the other hand, the gate electrodes of the address transistors 25, 26 and 27 are connected to the signal lines 30 and 3 from the address control circuit 5.
Vm voltage, Vdd, V
m voltage is applied to the address transistors 25, 26,
27 is in the "off" state.

At this time, the potential of the electrode 10 of the memory element 1 becomes Vm voltage, and the potential of the electrode 11 becomes Vdd. Therefore, a voltage higher than the dielectric breakdown voltage is applied to the memory oxide film to write information. On the other hand, the memory element 2,
The electrodes 12, 13, 14, 15, 16, which constitute 3, 4,
Since the address transistors 25, 26, and 27 are non-conductive, a voltage determined by the potential Vdd at the connection point 19 and the potential at the connection point 9 between the internal circuit and the resistors 35, 36, 37 is applied to 17. That is, since no voltage higher than the dielectric breakdown voltage is applied to the memory oxide film, it remains in the non-written state.

Next, when writing to the memory cell 2, the address control circuit 5 supplies signal lines 29, 30, 3 to the gate electrodes of the address transistors 24, 25, 27.
The Vm voltage, Vdd and Vdd are respectively applied via 2 and the address transistors 24, 25 and 27 are in the “on” state. On the other hand, the address transistor 2
The gate electrodes of 3 and 26 are supplied with Vm voltage and Vdd via signal lines 28 and 31 from the address control circuit 5, respectively.
Is applied, and the address transistors 23 and 26 are in the “off” state.

At this time, the potential of the electrode 13 of the memory element 2 becomes Vm voltage, and the potential of the electrode 12 becomes Vdd. Therefore, a voltage higher than the dielectric breakdown voltage is applied to the memory oxide film to write information. On the other hand, the potentials of the electrodes 10 and 11 of the memory element 1 become Vdd because the address transistor 23 is in the non-conductive state. The potentials of the electrodes 14, 15, 16 and 17 of the memory elements 3 and 4 become Vm voltage because the address transistor 27 is conductive and the address transistor 26 is non-conductive. That is, since no voltage higher than the dielectric breakdown voltage is applied to the memory oxide film, it remains in the non-written state.

Next, when writing to the memory cell 3, the address control circuit 5 supplies signal lines 28, 30, to the gate electrodes of the address transistors 23, 25, 26.
Vdd, Vdd, and Vm voltages are applied via 31 respectively, and the address transistors 23, 25, and 26 are in the “on” state. On the other hand, the gate electrodes of the address transistors 24 and 27 are connected to Vdd and Vd via signal lines 29 and 32 from the address control circuit 5, respectively.
d is applied, and the address transistors 24 and 27 are in the "off" state.

At this time, the potential of the electrode 14 of the memory element 3 becomes Vm voltage, and the potential of the electrode 15 becomes Vdd. Therefore, a voltage higher than the dielectric breakdown voltage is applied to the memory oxide film to write information. On the other hand, the memory device 1,
The potentials of the second electrodes 10, 11, 12, and 13 become the Vm voltage because the address transistor 23 is in the conductive state and the address transistor 24 is in the non-conductive state. The potential of the electrode 16 of the memory element 4 is Vdd, and the potential of the electrode 17 is determined by the potential Vdd of the connection point 21, the potential of the connection point 39 with the internal circuit, and the resistance 37 because the address transistor 27 is in the non-conductive state. A voltage is applied. That is,
Since no voltage higher than the dielectric breakdown voltage is applied to the memory oxide film, it remains in the non-written state.

Next, when writing to the memory cell 4, Vm voltage and Vd are applied to the gate electrodes of the address transistor 26 and the address transistor 27 from the address control circuit 5 via the signal line 31 and the signal line 32, respectively.
d is applied, and the address transistor 26 and the address transistor 27 are in the “on” state. On the other hand, the gate electrodes of the address transistors 23, 24, 25 have signal lines 28, 29, 31 from the address control circuit 5, respectively.
The Vm voltage, the Vdd voltage, and the Vm voltage are applied to the address transistors 23, 24, and 25, respectively, so that the address transistors 23, 24, and 25 are in the "off" state.

At this time, the potential of the electrode 17 of the memory element 4 becomes Vm voltage, and the potential of the electrode 16 becomes Vdd. Therefore, a voltage higher than the dielectric breakdown voltage is applied to the memory oxide film to write information. On the other hand, the memory device 1,
The potentials of the electrodes 10, 11, 12, 13, 14, 15 of the second and third electrodes become Vdd because the address transistors 23, 24, 25 are in the non-conductive state. That is, since no voltage higher than the dielectric breakdown voltage is applied to the memory oxide film, it remains in the non-written state.

The writing of a plurality of memory elements is performed by repeating the operation of writing one memory element at an arbitrary position described above, and thus detailed description thereof will be omitted.

Next, the operation of the semiconductor resistance device of the present invention after setting the resistance value will be described. The Vm terminal is disconnected from the external power supply, and the potential of the Vm terminal is set to V through the pull-down resistor 38.
ss. A signal "0" is input to the program mode input terminal to set the address control circuit 5 to the normal mode, and the address transistors 23, 25, and 27 using N-channel MOS transistors are connected to the signal line 28 from the address control circuit 5. , 30, 32 to the gate electrode Vs
s is applied to turn off the address transistors 23, 25, 27. Vdd is applied from the address control circuit 5 to the gate electrodes of the address transistors 24 and 31 using P-channel MOS transistors via the signal line 29 and the signal line 31 to bring them into the "off" state. That is,
All address transistors are "off".

When the memory element 1 is written, the memory oxide film of the memory element 1 has a dielectric breakdown,
The electrode 10 and the electrode 11 are in a conductive state. Therefore, a path in which a current flows is formed through the memory element 1 connected in parallel to the resistor 34 of the resistor array 9. On the other hand, since the memory oxide films of the memory elements 2, 3, 4 are not dielectrically broken down, the electrodes 12 and 13, the electrodes 14 and 15, and the electrodes 16 and 17 are in the non-conductive state. not exist.

The resistance value R0 of the resistor array 9 at this time is
If the resistance values of the resistors 33, 34, 35, 36, 37 are R1, R2, R3, R4, R5, respectively, and the resistance value after writing of the memory element 1 is calculated as R6, R0 = R1 + R3 + R4 + R6.R2 / (R2 + R6) Becomes

As is apparent from the above-mentioned formula for obtaining the adjusted resistance value, the resistance value R6 of the memory element 1 is equal to the resistance value 3
Resistance values R1, R of 3, 34, 35, 36, 37, respectively
If it is sufficiently smaller than 2, R3, R4, and R5, the resistance value R0 of the resistance array 9 becomes (R1 + R3 + R4 + R
It can be approximated to 5).

Although the case where information is written to the memory element 1 has been described here, the same can be done when writing to the memory elements 2, 3, 4 and a plurality of memory elements. Detailed description is omitted.

Therefore, in order to widen the setting range of the resistance value of the semiconductor resistance device and make the setting of the resistance value more accurate, the resistance value of the memory element after writing is made smaller and its variation is made smaller. is there.

Next, a memory element having a memory oxide film 44 having a film thickness of 5 nm shown in FIG.
Under the write condition of V and Vm application time of 1 msec, the gate width of the address transistor of the memory cell is changed,
The distribution of the resistance value of the memory element after writing when the amount of current passing through the memory element is changed when Vm is applied is shown in the graph of FIG.

In the graph of FIG. 3, the resistance value of the memory element is measured by applying a voltage of 1 V to the memory element after writing, measuring the flowing current value, and converting it to the resistance value.

As is clear from the graph of FIG. 3, when the current value passing through the memory element is 2 mA, the resistance value is distributed in the range of 600Ω to 1KΩ. And the average resistance is 7
It is 50Ω. On the other hand, when the current value is 200 μA, the resistance value is distributed in the range of 1.5 KΩ to 11 KΩ, and the average resistance value is 3.73 KΩ, which is higher than the resistance of 2 mA. The variation is also large.

Next, during normal operation, the voltage applied to the memory element changes depending on the resistance value of the resistance array 9. Therefore, in order to set the resistance value accurately, it is necessary that the resistance value of the memory element after writing has a small voltage dependency. Therefore, the voltage dependence of the resistance value of the memory element after writing is shown in the graph of FIG.

In FIG. 4, the curves 50, 51 and 52 are
The resistance value after writing the memory element at 1V is 8
The voltage dependence is shown for 00Ω, 10KΩ, and 50KΩ. As is clear from this graph, the smaller the resistance value after writing at 1 V, the smaller the change in the resistance value due to the voltage. In particular, in the curve 50, no change in resistance value was observed. On the other hand, in the curve 52, the applied voltage is 0.5 V
When it becomes smaller, the resistance value remarkably increases depending on the voltage.

From the graphs of FIG. 3 and FIG. 4, the write condition of the memory element is that the current value passing through the memory element when Vm is applied is 2 mA or more. By performing writing in the memory element under this condition, the resistance value of the memory element after writing is distributed to 1 KΩ or less and there is almost no variation. In addition, the resistance value of the memory element after writing has no voltage dependence. This indicates that the resistance value of the resistance array 9 shown in FIG. 1 can be adjusted accurately and stably.

Next, in the case where the resistance array of the semiconductor device according to the embodiment of the present invention is formed of polycrystalline silicon, the resistance 33, the resistance 34, the memory element 1, and the address transistors 23 and 24 shown in FIG. A part of the plane pattern shape is shown in the plan view of FIG.

In FIG. 5, a polycrystalline silicon wiring 63 operates as the resistors 33 and 34 in FIG.
Ω / cm 2 to 1 MΩ / cm 2 high sheet resistance region 5
5, 56, a low sheet resistance region 57 that operates as an electrode connected to Vdd through an aluminum wiring 60 through a contact hole, and a first electrode that constitutes a memory element having a metal-insulating film-metal structure shown in FIG. And a low sheet resistance region 54 operating as 43. This low sheet resistance region 54
Corresponds to the electrode 10 shown in FIG.

On the low sheet resistance region 54, the polycrystalline silicon electrode 5 acting as the second electrode 45 in FIG.
3 is provided. Further, although not shown in FIG. 5, a memory oxide film formed on the surface of the polycrystalline silicon wiring 63 is provided.
The low sheet resistance region 54, the memory oxide film, and the polycrystalline silicon electrode 53 constitute a memory element having a metal-insulating film-metal structure. This polycrystalline silicon electrode 53 corresponds to the electrode 11 in FIG.

The polycrystalline silicon electrode 53 is a P channel M
Aluminum wiring 5 through the contact hole to the drain electrode of the address transistor 61 using the OS transistor
8 are connected.

The low sheet resistance region 54, which is a high concentration impurity region, is connected to the drain electrode of the address transistor 62 using an N channel MOS transistor by an aluminum wiring 59 via a contact hole.

As described above, in the embodiment of the present invention, the high sheet resistance regions 55 and 56 of one polycrystalline silicon wiring 63 are formed.
Is used as the resistance element, and the low sheet resistance region 54 is used as the first electrode of the memory element. As a result, the wiring between the resistance element and the memory element can be omitted, so that the area of the semiconductor resistance device can be reduced.

Although the number of memory cells is four in the above-described embodiment of the present invention, the number of cells may be increased in units of an even number. By increasing the number of cells, it is possible to further finely adjust the correction amount of the resistance value.

[0077]

As is apparent from the above description, according to the semiconductor resistance device of the present invention, after the resistance that fluctuates due to manufacturing variations is formed in the semiconductor integrated circuit device, the resistance value is corrected and the semiconductor integrated circuit device is corrected. Can be set to a resistance value that is most suitable for the specifications.

Further, in the semiconductor resistance device of the present invention, the memory element that obtains the resistance value conforming to the specifications is subjected to dielectric breakdown,
Since a current path is formed that is in a conductive state and is directly connected in parallel to the resistors that form the resistor array, it does not require a read circuit or data latch circuit, and does not consume the current required for these circuits to operate. The value can be set to the optimum value.

The memory element constituting the semiconductor resistance device of the present invention adopts a polycrystalline silicon two-layer structure using polycrystalline silicon in which the first electrode is used as the gate electrode of the MOS structure. For this reason, the manufacturing process is simple and the surrounding MO
It does not affect the S-transistor characteristics.

Further, the write current required to reduce the variation in the resistance value of the memory element after writing is 2 m.
As small as A, 1 msec at 5 nm memory oxide film
The writing voltage required for dielectric breakdown in 10 hours is also 10
It is as small as V, and it is not necessary to increase the withstand voltage of the peripheral semiconductor elements.

Further, in the semiconductor resistance device of the present invention, there is no occurrence of silicon scraps or deterioration of the passivation film,
The characteristic deterioration of the semiconductor integrated circuit device does not occur.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor resistance device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a memory element having a metal-insulating film-metal structure that constitutes a semiconductor resistance device according to an embodiment of the present invention.

FIG. 3 is a graph showing a distribution of a through current value and a resistance value after writing of a memory element having a metal-insulating film-metal structure which constitutes a semiconductor resistance device according to an embodiment of the present invention.

FIG. 4 is a graph showing voltage dependence of a resistance value after writing of a memory element having a metal-insulating film-metal structure which constitutes a semiconductor resistance device according to an exemplary embodiment of the present invention.

FIG. 5 is a plan view showing a plane pattern shape when the resistance garment of the semiconductor resistance device in the embodiment of the present invention is made of polycrystalline silicon.

FIG. 6 is a circuit diagram showing a semiconductor resistance device in the related art.

[Explanation of symbols]

 1 Memory Cell 4 Address Control Circuit 5 Vm Terminal 6 Program Mode Input Terminal 7 Address Signal Input Terminal 8 Resistor Array 10 Memory Element 19 Address Transistor 22 Address Transistor

Claims (10)

[Claims] 1. A memory device comprising: a resistor array having a plurality of resistors connected in series; a memory element connected in parallel with the resistors of the resistor array; and a plurality of address transistors for selectively writing information to the memory device. A semiconductor resistance device characterized in that the resistance value of a resistance array is selected by writing information to the semiconductor resistance device. 2. A resistor array in which a plurality of resistors are connected in series, an electrically writable memory element connected in parallel with the resistors of the resistor array, and a plurality of memory elements for selectively writing information in the memory element. A semiconductor resistance device comprising an address transistor and selecting a resistance value of a resistance array by writing information in a memory element. 3. A resistance array in which a plurality of resistors are connected in series, a memory element of a metal-insulating film-metal structure that is electrically writable only once and is connected in parallel with the resistance of the resistance array, and information is stored in the memory element. A semiconductor resistance device comprising: a plurality of address transistors for selectively writing, wherein the resistance value of a resistance array is selected by writing information in a memory element. 4. A resistance array comprising: a resistance array in which a plurality of resistances are connected in series; a memory element connected in parallel with the resistances of the resistance array; and a plurality of address transistors for selectively writing information in the memory element. Has a plurality of low sheet resistance regions and a plurality of high sheet resistance regions in the polycrystalline silicon wiring provided on the field oxide film on the semiconductor substrate, and selects the resistance value of the resistor array by writing information in the memory element. And a semiconductor resistance device. 5. A resistor array in which a plurality of resistors are connected in series, an electrically writable memory element that is connected in parallel with the resistors in the resistor array, and a plurality of memory devices for selectively writing information in the memory device. An address transistor is provided, and the resistance array has a plurality of low sheet resistance regions and high sheet resistance regions in a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. A semiconductor resistance device characterized by selecting a resistance value of an array. 6. A resistor array having a plurality of resistors connected in series, a memory element having a metal-insulating film-metal structure which is electrically writable only once and is connected in parallel with the resistors of the resistor array, and information is stored in the memory element. The resistance array has a plurality of address transistors for selectively writing, and the resistance array has a plurality of low sheet resistance regions and high sheet resistance regions in a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. A semiconductor resistance device characterized in that the resistance value of a resistance array is selected by writing information in an element. 7. A resistor array in which a plurality of resistors are connected in series, an electrically writable memory element that is connected in parallel with the resistors in the resistor array, and a plurality of memory elements for selectively writing information in the memory element. An address transistor is provided, and the memory element is in contact only with the first electrode provided on the field oxide film on the semiconductor substrate, the memory oxide film provided on the surface of the first electrode, and the memory oxide film provided on the upper surface of the first electrode. A semiconductor resistance device having a second electrode, wherein the resistance value of the resistance array is selected by writing information in a memory element. 8. A resistor array in which a plurality of resistors are connected in series, an electrically writable memory element connected in parallel with the resistors of the resistor array, and a plurality of memory elements for selectively writing information in the memory element. An address transistor is provided, and the resistance array is composed of a plurality of low sheet resistance regions and a plurality of high sheet resistance regions on a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. Information is written to a memory element having a first electrode provided on the film, a memory oxide film provided on the surface of the first electrode, and a second electrode contacting only the memory oxide film provided on the upper surface of the first electrode. A semiconductor resistance device characterized in that the resistance value of the resistance array is thereby selected. 9. A resistor array in which a plurality of resistors are connected in series, an electrically writable memory element connected in parallel with the resistors of the resistor array, and a plurality of memory devices for selectively writing information in the memory device. An address transistor is provided, and the resistance array is composed of a plurality of low sheet resistance regions and a plurality of high sheet resistance regions on a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. Information is written in a memory element, which includes a polycrystalline silicon wiring provided over the film, a memory oxide film provided over the polycrystalline silicon wiring, and a polycrystalline silicon electrode provided over the memory oxide film provided over the polycrystalline silicon wiring. A semiconductor resistance device characterized in that the resistance value of the resistance array is thereby selected. 10. A resistor array in which a plurality of resistors are connected in series, an electrically writable memory element that is connected in parallel with the resistors of the resistor array, and a plurality of memory elements for selectively writing information in the memory element. An address transistor is provided, and the resistance array is composed of a plurality of low sheet resistance regions and a plurality of high sheet resistance regions in a polycrystalline silicon wiring provided on a field oxide film on a semiconductor substrate. A polycrystalline silicon wiring provided on the film; a memory oxide film provided on the polycrystalline silicon wiring; and a polycrystalline silicon electrode provided on the memory oxide film provided on a low sheet resistance region of the polycrystalline silicon wiring. A semiconductor resistance device characterized in that the resistance value of a resistance array is selected by writing information in an element.