JPH09281256A - Crystal oscillation type electronic watch - Google Patents

Abstract

PROBLEM TO BE SOLVED: A crystal oscillation type electronic watch eliminates the influence of the origination frequency by the voltage fluctuation of a battery by using a constant voltage circuit but the fluctuation in the element characteristics by a variation in production fluctuates the output voltage and current consumption of the constant voltage circuit and degrades the watch performance and battery life. SOLUTION: This electronic watch has a reference resistor 7 connected in series with plural resistors and a memory cell 11 connected in series to the resistors. This memory cell 11 is composed of a memory element of a metal-insulating film-metal structure and a MOS transistor. An overvoltage is impressed from outside on the selected memory element to cause permanent destruction, by which a first electrode and a second electrode are made conducting and the state of passing a current only through the memory element made conducting is attained. This selected information directly forms a route where the current of the resistor array 10 flows and, therefore, the resistance value of a reference resistor may be set at the value most meeting the specifications of the watch without requiring a reading out circuit and data latched circuit and without consuming the current necessary for the operation of these circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a crystal oscillation type electronic timepiece, and more particularly, to a complementary field effect transistor (CMOS) having means for dividing a frequency of the crystal resonator to a time display device with the crystal resonator as a time reference. Transistor)
The present invention relates to a crystal oscillation type electronic timepiece using the above logic circuit. More specifically, the discharge characteristic of the battery voltage is 1.55V.
The present invention relates to a configuration of a crystal oscillation type electronic timepiece equipped with a constant voltage circuit capable of removing this voltage fluctuation when a battery of a type that fluctuates up to 1.2 V is used.

[0002]

2. Description of the Related Art A CM having means for dividing a frequency of the crystal unit to a time display device with the crystal unit as a time reference.
A constant voltage that can eliminate this voltage fluctuation when a battery of a type in which the discharge characteristic of the battery voltage fluctuates from 1.55 V to 1.2 V is used in a quartz oscillation electronic timepiece that uses a logic circuit of an OS transistor. A conventional technique of a crystal oscillation type electronic timepiece including a circuit will be described with reference to the circuit block diagram of FIG. 7 and the circuit diagram of FIG.

As shown in FIG. 7, a conventional crystal oscillation type electronic timepiece has an oscillator 71, a frequency divider 72, a display driver 73, a time display device 74, a constant voltage circuit 76, and a battery. It is composed of 75.

The battery 75 is set to 1V by the constant voltage circuit 76.
The constant voltage is converted into the following constant voltage, and the constant voltage is converted into
Is added to the frequency divider 72 to eliminate the influence of voltage fluctuation on the oscillation frequency. On the other hand, the voltage of the battery 75 is applied to the display drive unit 73 as it is.

The circuit operation of the constant voltage circuit 76 shown in FIG.
A brief description will be given with reference to the circuit diagram of FIG. The reference voltage obtained by the current mirror type reference voltage device composed of the MOS transistors 82, 83, 84, 85, 86 and the reference resistor 81 is applied to the MOS transistors 87, 88, 8
The line 80 as the input of the differential amplifier consisting of 9, 90, 91
In addition, the same reference voltage is taken out as the gate voltage of the output MOS transistor 92, and a constant output voltage is provided between the drain of the output MOS transistor 92 and the high potential of the power supply voltage.

[0006]

The gain of the current mirror type reference voltage device depends on the amplification degree of each MOS transistor. If the gain is increased, the stability is improved, but the current consumption is increased. , Battery life will be shortened. Therefore, in order to realize a constant voltage circuit with a current consumption of several tens of nA, the gain is increased and the reference resistor 81
Also need to be larger.

As described above, in the crystal oscillation type electronic timepiece,
In order to set the constant voltage value to the best value, it is necessary to strictly set the gain and the reference resistor 81.

However, variations in element characteristics due to manufacturing variations of the MOS transistor and the reference resistor 81 cause an error in the setting of the gain and the reference resistor, which must be strictly performed. That is, the output voltage and current consumption of the constant voltage circuit 76 fluctuate due to manufacturing variations, which deteriorates watch performance and battery life.

Therefore, an object of the present invention is to solve the above problems and provide a quartz oscillation type electronic timepiece having a long life due to low current consumption and good frequency stability when a battery with large voltage fluctuation is used. is there.

[0010]

In order to achieve the above object, the quartz oscillator type electronic timepiece of the invention adopts the following means.

The crystal oscillation type electronic timepiece of the present invention includes an oscillating unit using a crystal oscillator as a time reference source, and a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device.
A display drive unit for driving the time display device, a constant voltage circuit for supplying a constant voltage to the oscillation unit and the frequency division unit, and a battery, the constant voltage circuit being a reference resistor and a current mirror type reference It is characterized by having a voltmeter and a differential amplifier.

The crystal oscillating electronic timepiece of the present invention comprises an oscillating unit using a crystal oscillator as a time reference source, and a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device.
A display drive unit for driving the time display device, a constant voltage circuit for supplying a constant voltage to the oscillation unit and the frequency division unit, and a battery, the constant voltage circuit being a reference resistor and a current mirror type reference The reference resistor includes a voltage generator and a differential amplifier, and the reference resistor includes a resistor array in which a plurality of resistors are connected in series, and a memory cell array including memory cells connected in parallel to a plurality of resistors in the resistor array and a connection point of the resistors. And an address control circuit.

The crystal oscillating electronic timepiece of the present invention includes an oscillating unit using a crystal oscillator as a time reference source, and a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device.
A display drive unit for driving the time display device, a constant voltage circuit for supplying a constant voltage to the oscillation unit and the frequency division unit, and a battery, the constant voltage circuit being a reference resistor and a current mirror type reference The reference resistor includes a voltage generator and a differential amplifier, and the reference resistor includes a resistor array in which a plurality of resistors are connected in series, and a memory cell array including memory cells connected in parallel to a plurality of resistors in the resistor array and a connection point of the resistors. An address control circuit is provided, and the memory cell has a memory element and a plurality of address transistors for selectively writing information to the memory element and for reading information from the memory element. It is characterized in that the resistance value of the array is selected.

The crystal oscillating electronic timepiece of the present invention includes an oscillating section using a crystal oscillator as a time reference source, and a frequency dividing section for dividing the frequency of the crystal oscillator to a frequency for driving the time display device.
A display drive unit for driving the time display device, a constant voltage circuit for supplying a constant voltage to the oscillation unit and the frequency division unit, and a battery, the constant voltage circuit being a reference resistor and a current mirror type reference The reference resistor includes a voltage generator and a differential amplifier, and the reference resistor includes a resistor array in which a plurality of resistors are connected in series, and a memory cell array including memory cells connected in parallel to a plurality of resistors in the resistor array and a connection point of the resistors. An address control circuit is provided, and the memory cell has a memory element that is electrically writable only once and a plurality of address transistors for selectively writing information to the memory element and reading information from the memory element. The resistance value of the resistor array is selected by writing information in the element.

The crystal oscillation type electronic timepiece of the present invention includes an oscillating unit using a crystal oscillator as a time reference source, and a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device.
A display drive unit for driving the time display device, a constant voltage circuit for supplying a constant voltage to the oscillation unit and the frequency division unit, and a battery, the constant voltage circuit being a reference resistor and a current mirror type reference The reference resistor includes a voltage generator and a differential amplifier, and the reference resistor includes a resistor array in which a plurality of resistors are connected in series, and a memory cell array including memory cells connected in parallel to a plurality of resistors in the resistor array and a connection point of the resistors. The memory cell is provided with an address control circuit, and the memory cell has a metal-insulating film-metal structure electrically writable only once and a plurality of memory cells for selectively writing information to the memory element and reading information from the memory element. An address transistor is provided, and the resistance value of the resistor array is selected by writing information in the memory element.

The crystal oscillating electronic timepiece of the present invention includes an oscillating unit using a crystal oscillator as a time reference source, and a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device.
A display drive unit for driving the time display device, a constant voltage circuit for supplying a constant voltage to the oscillation unit and the frequency division unit, and a battery, the constant voltage circuit being a reference resistor and a current mirror type reference The reference resistor includes a voltage generator and a differential amplifier, and the reference resistor includes a resistor array in which a plurality of resistors are connected in series, and a memory cell array including memory cells connected in parallel to a plurality of resistors in the resistor array and a connection point of the resistors. An address control circuit is provided, and the memory cell is provided only on the first electrode provided on the field oxide film on the semiconductor substrate, the memory oxide film provided on the surface of the first electrode, and the memory oxide film provided on the upper surface of the first electrode. An electrically writable memory element having a contacting second electrode and a plurality of address transistors for selectively writing information to the memory element and for reading information from the memory element are provided. , Characterized by selecting the resistance value of the resistor array by writing information into the memory device.

In the crystal oscillation type electronic timepiece of the present invention, the output voltage of the constant voltage circuit is supplied by amplifying the reference voltage generated by the current mirror type reference voltage device by the differential amplifier. At that time, the reference voltage of the current mirror type reference voltage machine can be arbitrarily changed by selecting the resistance value of the reference resistor.

The resistance value of the reference resistor is such that an overvoltage is forcibly applied to the memory oxide film, which is connected in parallel with the resistor array and insulates the first electrode and the second electrode of an arbitrary memory element, from the outside. By applying and causing permanent destruction, the first electrode and the second electrode are brought into conduction. The resistance value of the reference resistor can be arbitrarily selected by setting the state in which the current flows through the resistance array only through the memory element in the conductive state.

Therefore, after the semiconductor integrated circuit device is manufactured, the selection information is stored in one memory element that obtains the resistance value of the reference resistor that is the output voltage of the constant voltage circuit that most matches the timepiece specifications. Since this selection information directly forms a path through which a current flows in the resistor array, it does not require a read circuit or a data latch circuit, which have been conventionally required, and does not consume the current necessary for the operation of these circuits, and the constant voltage circuit The output voltage can be set to the optimum value.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the crystal oscillation type electronic timepiece of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing a configuration of a crystal oscillation type electronic timepiece according to an embodiment of the present invention.

As shown in FIG. 1, a crystal oscillation type electronic timepiece has an oscillating unit 1 having a crystal oscillator as a time reference source, and a frequency divider for dividing the frequency of the crystal oscillator to a frequency driven by a time display device. A unit 2, a display drive unit 3, a time display device 4,
It comprises a constant voltage circuit 6 for supplying a constant voltage to the oscillator 1 and the frequency divider 2, and a battery 5.

Further, the constant voltage circuit 6 includes a reference resistor 7 and
A current mirror type reference voltage device 8 and a differential amplifier 9 are provided. The reference resistor 7 is a memory cell array 11 for storing information for controlling the output voltage of the constant voltage circuit 6.
A resistance array 10 that changes the resistance value based on the information stored in the memory cell array; an address control circuit 12 that selects a memory cell to write the information; and a program voltage that is externally supplied. A Vm terminal 13 to which Vm) is applied, an address signal input terminal 15, and a program mode input terminal 14.

Next, the circuit configuration of the reference resistor 7 according to the embodiment shown in FIG. 1 will be described with reference to the circuit diagram of FIG.
Hereinafter, an embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 2, the reference resistor 7 includes a resistor array 10 in which four resistors 49, 50, 51 and 52 are connected in series, and three connecting points 53 and 5 in the resistor array 10.
Three memory cells 21, 22, which are connected in parallel to 4, 55,
The memory cell array 11 is composed of 23, the address control circuit 12, the Vm terminal 12, the address signal input terminal 15, and the program mode input terminal 14. The potential of the Vm terminal 13 becomes the low potential (hereinafter referred to as Vss) of the battery 5 in FIG. 1 via the pull-down resistor 56 when the external power supply is not connected.

The memory cells 21, 22, 23 are P-channel MOS transistors 39, 40, 41, respectively.
, Memory elements 30, 31, 32, and N-channel MOS
Transistors 42, 43, and 44 are connected in series to configure. Further, the connection portion between the memory element and the drain electrode of the N-channel MOS transistor is connected to the connection points 53, 54 and 55 of the resistance array 10, respectively. P channel M
The gate electrodes of the OS transistors 39, 40 and 41 are connected to the signal lines 45, 46 and 47 from the address control circuit 12, respectively.

On the other hand, the N-channel MOS transistor 3
The gate electrodes of 2, 33, and 34 are connected to the signal line 48 from the address control circuit 12 and three of them are configured so that they can receive the same control. The P-channel MOS transistors 39, 40 and 41 and the N-channel MOS transistors 42, 43 and 44 form an address transistor.

The memory elements 30, 31, 32 are composed of read-only metal-insulator-metal structure memory elements which can be electrically written only once. A cross-sectional structure of the memory element having the metal-insulating film-metal structure is shown in FIG. FIG. 3 is a cross-sectional view showing the structure of the memory device according to the embodiment of the present invention.

As shown in FIG. 3, a field oxide film 62 is provided on a semiconductor substrate 61, and a first electrode 63 made of polycrystalline silicon is provided on the field oxide film 62. Further, a memory oxide film 64, which is a thin silicon oxide film formed on the surface of the first electrode 63, and a second electrode 65 made of polycrystalline silicon provided on the memory oxide film 64 are provided. Furthermore, the first electrode 63 and the second electrode 63 are formed through a contact hole provided in the interlayer insulating film 66.
Aluminum wiring 67 for setting the potential of the electrode 65 is provided.

As a method of manufacturing a memory element having a metal-insulating film-metal structure in the present invention, polycrystalline silicon forming a gate electrode in a general complementary field effect transistor (CMOS transistor) manufacturing process is formed on the entire surface. However, the processing steps up to the impurity implantation step are the same. That is, the gate electrode of the MOS transistor and the first electrode 6
3 may be made of the same polycrystalline silicon. Here, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 61 by a chemical vapor deposition apparatus, and no pattern is formed.

Next, a silicon oxide film having a small thickness is formed on the polycrystalline silicon provided on the entire surface of the silicon substrate by thermal oxidation to form a memory oxide film 64. After that, polycrystalline silicon is further formed by a chemical vapor deposition method, impurities are implanted to form a predetermined conductive layer, and a photoetching method is used to form a polycrystalline material which is a material of the first electrode 63 as shown in FIG. Patterning is performed so that the second electrode 65 remains on the silicon film.

Next, a first photoetching method is used.
The electrode 63 and the gate electrode of the MOS transistor are patterned. Subsequently, a general CMOS transistor manufacturing process of forming a correlation insulating film 66 after forming a gate electrode of polycrystalline silicon, forming a contact hole, and forming an aluminum wiring 67 is performed.

In this way, the patterning of the gate electrode of the MOS transistor and the first electrode 63 is carried out by the second electrode 6
This is performed after patterning No. 5. Therefore, MOS
There is no thinning of the pattern size of the gate electrode of the transistor, and the etching residue of the polycrystalline silicon, which is the material for forming the second electrode 65, does not occur.

Moreover, the manufacturing of the memory element before the formation of the source region and the drain region does not increase the diffusion distance between the source region and the drain region due to the heat treatment for forming the memory oxide film 64. That is, there is no influence on the MOS transistor characteristics due to the fabrication of the memory element.

To write information to the memory element, the potentials of the first electrode 63 and the second electrode 65 are applied to the memory oxide film 64 by 8 times.
By setting so that an electric field of MV / cm or more is applied, permanent destruction is caused in the memory oxide film 64, and the first electrode 63 and the second electrode 65 are brought into conduction.

On the other hand, in a potential state in which the memory oxide film 64 provided between the first electrode 63 and the second electrode 65 does not cause dielectric breakdown, the first electrode 63 and the second electrode 65 are in an insulated state. There is.

In this way, the first electrode 63 and the second electrode 6
By controlling the potential with respect to 5 it is possible to change to two stable states, a conducting state and an insulating state, so that it operates as a memory element.

Next, a method of setting the resistance value of the resistor array 10 shown in FIG. 2 which meets the specifications after manufacturing the semiconductor integrated circuit device will be described with reference to FIG.

The resistance value of the resistor array 10 is the same as that of the memory cell 2.
It is possible to select four types of resistance values by setting one of the memory elements 1, 22, and 23, 31, 32, and 32 into a conductive state. That is, the memory elements 30, 31, 3
This is equivalent to writing the setting information of the resistance value in 2.

To write data to the memory device, first, an external power source whose output voltage is set to Vss is connected to the Vm terminal 1.
Connect to 3. A signal "1" is input to the program mode input terminal 14 to put the address control circuit 12 in the write mode. An address signal is input to the address input terminal 15 to select a write destination memory element.

Next, the output voltage of the external power supply is applied to the Vm terminal 13 with a high negative write voltage (Vm voltage) for a predetermined time to cause dielectric breakdown in the memory oxide film of the selected memory element to perform writing.

P-channel MO in memory cells 21, 22, and 23 when Vm is applied to Vm terminal 13.
The operation states of the S transistors 39, 40, 41 and the N channel MOS transistors 42, 43, 44 will be described below by taking the case of writing to the memory element 30 as an example.

Vm is applied to the gate electrode of the P-channel MOS transistor 39 of the memory cell 21 from the address control circuit 12 via the signal line 45, and the P-channel MOS transistor 39 is applied.
The transistor 39 is in the "on" state. on the other hand,
Vdd is applied to the gate electrodes of the P-channel MOS transistors 40 and 41 of the memory cells 22 and 23 from the address control circuit 12 through the signal lines 46 and 47, and the P-channel MOS transistors 40 and 41 are turned off. To do.

N-channel MOS transistors 42, 4
Vdd is applied from the address control circuit 12 through the signal line 48 so that 3, 44 are always in the “on” state in the write mode.

At this time, the potential of the electrode 33 of the memory element 30 becomes Vdd, and the potential of the electrode 34 becomes Vm. Therefore, a voltage higher than the dielectric breakdown voltage is applied to the memory oxide film to write information. On the other hand, the memory device 3
The potentials of the electrodes 36 and 37 of the electrodes 1 and 32 are Vm, but since the P-channel MOS transistors 40 and 41 are in the non-conductive state, Vdd is not applied to the electrodes 35 and 36. That is, since no voltage higher than the dielectric breakdown voltage is applied to the memory oxide film, it remains in the non-written state.

Next, the operation of the reference resistor of the present invention after setting the resistance value will be described. The Vm terminal is disconnected from the external power supply, and the potential of the Vm terminal is set to Vs via the pull-down resistor 56.
s. A signal "0" is input to the program mode input terminal to set the address control circuit 12 to the normal mode, and the P-channel MOS transistors 39, 40 and 41 are gated from the address control circuit 12 via the signal lines 45, 46 and 47. Vss is applied to the electrodes to turn on the P-channel MOS transistors 39, 40, 41. on the other hand,
Vss is applied from the address control circuit 12 to the gate electrodes of the N-channel MOS transistors 42, 43 and 44 via the signal line 48 to bring them into the "off" state.

Since writing was performed in the memory element 30,
The memory oxide film of the memory element 30 has a dielectric breakdown, and the electrodes 33 and 34 are in a conductive state. Therefore, the P-channel MOS transistor 39 and the memory element 3
Thus, a path through which a current flows is formed to the connection point 53 between the resistor 49 and the resistor 50 of the resistor array 10 via 0. On the other hand, since the memory oxide films of the memory elements 31 and 32 have not been dielectrically broken down, the electrodes 35 and 36, and the electrodes 37 and 38 are in the non-conductive state, so that there is no path through which current flows to the resistor array 10. .

The resistance value R0 of the resistance array 10 at this time
Indicates the resistance values of the resistors 49, 50, 51, 52 as R1, R
2, R3 and R4, P-channel MOS transistor 1
When the on resistance of 9 is R5 and the resistance value of the memory element 10 after writing is R6, R0 = R2 + R3 + R
4+ (R5 + R6) · R1 / (R1 + R5 + R6).

As is clear from the above equation for obtaining the adjusted resistance value, the sum (R5 + R6) of the resistance values of the P-channel MOS transistor 39 and the memory element 30 is the resistance 4
Resistance values R1, R2, R3, R4 of 9, 50, 51, 52
If it is sufficiently smaller than R, the resistance value R0 of the resistance array 10 can be approximated to (R2 + R3 + R4).

Although the case where the information is written in the memory element 30 has been described here, the same can be done when the information is written in the memory elements 31 and 32, and the detailed description will be omitted.

Therefore, in order to widen the setting range of the resistance value of the reference resistor 7 in FIG. 1 and to make the setting of the resistance value more accurate, the resistance value of the memory element after writing is made smaller and its variation is further reduced. It is to make it small.

Next, in the memory element in which the thickness of the memory oxide film 64 in FIG.
The resistance of the memory element after writing when changing the gate width dimension of the P-channel MOS transistor of the memory cell and changing the amount of current passing through the memory element when Vm is applied under the write condition of Vm for 1 msec The distribution of values is shown in the graph of FIG.

In the graph of FIG. 4, the resistance value of the memory element is measured by applying a voltage of 1 V to the memory element after writing, measuring the flowing current value, and converting it to the resistance value.

As is clear from the graph of FIG. 4, when the current value passing through the memory element is 2 mA, the resistance value is distributed in the range of 600Ω to 1KΩ. And the average resistance is 7
It is 50Ω. On the other hand, when the current value is 200 μA, the resistance value is distributed in the range of 1.5 KΩ to 11 KΩ, and the average resistance value is 3.73 KΩ, which is a distribution shifted to the high resistance side as compared with 2 mA, and its variation. Is also big.

Next, during normal operation, the voltage applied to the memory element changes depending on the resistance value of the resistance array 10. Therefore, in order to set the resistance value accurately, it is necessary that the resistance value of the memory element after writing has a small voltage dependency. Therefore, the voltage dependence of the resistance value of the memory element after writing is shown in the graph of FIG.

In FIG. 5, the curves 58, 59 and 60 are
The resistance value after writing the memory element at 1V is 8
The voltage dependence is shown for 00Ω, 10KΩ, and 50KΩ. As is clear from this graph, the smaller the resistance value after writing at 1 V, the smaller the change in the resistance value due to the voltage. In particular, in the curve 58, no change in resistance value is observed. On the other hand, in the curve 60, when the applied voltage becomes smaller than 0.5 V, the resistance value remarkably increases depending on the voltage.

As shown in FIGS. 4 and 5, the write condition of the memory element is that the current value passing through the memory element is 2 when Vm is applied.
It is mA or more. By writing to the memory element under this condition, the resistance value of the memory element after writing is 1K.
It can be distributed in the range of Ω or less and has almost no variation. In addition, the resistance value of the memory element after writing has no voltage dependence. This means that the reference resistor 7 of FIG.
It shows that the resistance value can be adjusted accurately and stably.

When the reference resistance is changed, the output of the constant voltage circuit 6 in FIG. 1 becomes a curve 69 when the resistance value is increased and a curve 70 when the resistance value is decreased, as shown in FIG.
Therefore, it is possible to control the output voltage of the constant voltage circuit 6.

In the embodiment of the present invention, the number of memory elements forming the memory block 10 is 3 bits, but the number of bits may be increased. By increasing the number of bits, it becomes possible to finely adjust the correction amount of the reference resistance value.

[0059]

As described above, according to the present invention,
After the semiconductor integrated circuit device is completed with the reference resistance that fluctuates due to manufacturing variations and the like, the reference resistance value can be corrected and the constant voltage value can be set to the best value.

Further, according to the present invention, one memory element that obtains a resistance value matching the specifications is dielectrically broken down to be in a conductive state, and a path through which the current of the resistor array directly flows is formed. Therefore, the read circuit and the data latch circuit are formed. It is possible to set the resistance value to an optimum value without the need for the above, and without consuming the current necessary for the operation of these circuits.

Therefore, according to the present invention, the constant voltage most conforming to the meter specifications enables the long life due to the low current consumption, and the frequency stability can be improved when the battery having the large voltage fluctuation is used. The effect is great.

Further, the memory element employs a polycrystalline silicon two-layer structure using polycrystalline silicon in which the first electrode is used as the gate electrode of the MOS structure. Therefore, the manufacturing process is simple and the characteristics of the surrounding MOS transistors are not affected.

Furthermore, the write current required to reduce the variation in the resistance value of the memory element after writing is 2
As low as mA, 1 mse at memory oxide film 5 nm
The write voltage required for dielectric breakdown in time c is also 1
It is as small as 0 V, and it is not necessary to increase the withstand voltage of the peripheral semiconductor elements. Furthermore, there is no occurrence of silicon scraps or deterioration of the passivation film, and no deterioration of the characteristics of the semiconductor integrated circuit device occurs.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a crystal oscillation type electronic timepiece according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a reference resistor and a memory block that compose the crystal oscillation type electronic timepiece according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a memory element having a metal-insulating film-metal structure which constitutes the crystal oscillation type electronic timepiece according to the embodiment of the present invention.

FIG. 4 is a graph showing a distribution of a through current value and a resistance value after writing of a memory element having a metal-insulating film-metal structure which constitutes the crystal oscillation type electronic timepiece according to the embodiment of the present invention.

FIG. 5 is a graph showing the voltage dependence of the resistance value after writing in the memory element having the metal-insulating film-metal structure that constitutes the crystal oscillation type electronic timepiece according to the embodiment of the present invention.

FIG. 6 is a graph showing the relationship between the power supply voltage and the output of the constant voltage circuit according to the embodiment of the present invention.

FIG. 7 is a circuit block diagram showing a configuration of a crystal oscillation type electronic timepiece according to a conventional technique.

FIG. 8 is a circuit diagram showing a constant voltage circuit of a crystal oscillation type electronic timepiece according to a conventional technique.

[Explanation of symbols]

 1 Oscillator 2 Frequency Divider 6 Constant Voltage Circuit 7 Reference Resistor 8 Current Mirror Type Reference Voltage 10 Resistor Array 11 Memory Cell 12 Address Control Circuit

Claims (6)

[Claims] 1. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Unit, a constant voltage circuit for supplying a constant voltage to the oscillating unit and the frequency dividing unit, and a battery, and the constant voltage circuit has a reference resistor, a current mirror type reference voltage device, and a differential amplifier. A crystal oscillation type electronic timepiece characterized in that. 2. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Section, a constant voltage circuit for supplying a constant voltage to the oscillating section and the frequency dividing section, and a battery. The constant voltage circuit includes a reference resistor, a current mirror type reference voltage unit, and a differential amplifier. The reference resistor has a resistor array in which a plurality of resistors are connected in series, a memory cell array including memory cells connected in parallel to a plurality of resistors in the resistor array, and an address control circuit. Quartz oscillation type electronic timepiece. 3. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Section, a constant voltage circuit for supplying a constant voltage to the oscillating section and the frequency dividing section, and a battery. The constant voltage circuit includes a reference resistor, a current mirror type reference voltage unit, and a differential amplifier. The reference resistor is provided with a resistance array in which a plurality of resistances are connected in series, a memory cell array including a memory cell connected in parallel to a connection point of the resistances in the resistance array, and an address control circuit. Has a memory element and a plurality of address transistors for selectively writing information to the memory element and for reading information from the memory element. By writing information to the memory element, the resistance value of the resistor array is changed. Crystal oscillator electronic timepiece which is characterized in that-option. 4. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Section, a constant voltage circuit for supplying a constant voltage to the oscillating section and the frequency dividing section, and a battery. The constant voltage circuit includes a reference resistor, a current mirror type reference voltage unit, and a differential amplifier. The reference resistor is provided with a resistance array in which a plurality of resistances are connected in series, a memory cell array including a memory cell connected in parallel to a connection point of the resistances in the resistance array, and an address control circuit. Has a memory element which can be electrically written only once and a plurality of address transistors for selectively writing information to the memory element and for reading information from the memory element, and writes information to the memory element. Crystal oscillation type electronic timepiece and selects the resistance value of the resistor array by the. 5. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Section, a constant voltage circuit for supplying a constant voltage to the oscillating section and the frequency dividing section, and a battery. The constant voltage circuit includes a reference resistor, a current mirror type reference voltage unit, and a differential amplifier. The reference resistor is provided with a resistance array in which a plurality of resistances are connected in series, a memory cell array including a memory cell connected in parallel to a connection point of the resistances in the resistance array, and an address control circuit. Is a metal that is electrically writable only once
Insulating film-A memory element having a metal structure and a plurality of address transistors for selectively writing information to the memory element and for reading information from the memory element, and by writing information to the memory element, the resistance value of the resistor array A crystal oscillation type electronic timepiece characterized by selecting. 6. An oscillating unit using a crystal oscillator as a time reference source, a frequency dividing unit for dividing the frequency of the crystal oscillator to a frequency for driving the time display device, and a display drive for driving the time display device. Section, a constant voltage circuit for supplying a constant voltage to the oscillating section and the frequency dividing section, and a battery. The constant voltage circuit includes a reference resistor, a current mirror type reference voltage unit, and a differential amplifier. The reference resistor is provided with a resistance array in which a plurality of resistances are connected in series, a memory cell array including a memory cell connected in parallel to a connection point of the resistances in the resistance array, and an address control circuit. Is a first electrode provided on the field oxide film on the semiconductor substrate, a memory oxide film provided on the surface of the first electrode, and a second electrode contacting only the memory oxide film provided on the upper surface of the first electrode. Write once Has a visible memory element and a plurality of address transistors for selectively writing information to the memory element and reading information from the memory element, and writing the information to the memory element selects the resistance value of the resistor array. A quartz oscillator type electronic timepiece characterized by