JP3669742B2 - Data holding circuit and method for writing and reading data - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a data holding circuit, and more particularly to a data holding circuit using a nonvolatile memory element.
[0002]
[Prior art]
A D latch circuit (static type or dynamic type) using CMOS is known as a data holding circuit. FIG. 5A shows a circuit diagram of a static type D latch circuit using CMOS.
[0003]
This D latch circuit has an input terminal IN, an output terminal OUT, inverters W1, W2, W3 and W4, and analog switches S1, S2, S3 and S4. The analog switches S1 and S4 are closed by “H” of the clock φ1 and opened by “L”. The analog switches S2 and S3 are closed by “H” of the clock φ2 and opened by “L”. Here, the clock φ2 is an inverted signal of the clock φ1.
[0004]
Therefore, as shown in the timing diagram of FIG. 5B, the value of the data input from the input terminal IN at the rising edge of the clock φ2 (time t1) is written into the D latch circuit. The written data is held until the next rising edge of clock φ2 (time t2), and the held value is output from output terminal OUT.
[0005]
In this way, the D latch circuit can hold data at a predetermined timing for a predetermined period.
[0006]
[Problems to be solved by the invention]
However, the D latch circuit using CMOS as described above has the following problems. In a D latch circuit using a CMOS, a voltage must always be applied to the circuit in order to retain data. Therefore, even when data is not written or read, a power source for holding the data is required. For this reason, unnecessary power is consumed when data is held. In addition, when the power is turned off due to an accident or the like, the stored data is lost.
[0007]
In order to solve this problem, it is also conceivable to use an EEPROM which is a nonvolatile memory element as a memory element. However, since an EEPROM requires a long time for writing, it is not suitable for a latch circuit that requires a high-speed response. Furthermore, since EEPROM requires a high voltage (for example, 12 V or more) at the time of writing and erasing, a booster circuit must be provided in the chip, or a high-voltage power supply must be prepared separately from the normal power supply, and the chip can be made compact. Contrary to cost reduction.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide a data holding circuit capable of solving a problem of a data holding circuit such as a conventional D latch circuit using a CMOS and not requiring a power supply for data holding and capable of high-speed response. And
[0009]
[Means for Solving the Problems]
The data holding circuit of the present invention is
A non-volatile memory device having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage;
An input terminal for inputting data to be written to the nonvolatile memory element;
A write enable terminal for inputting a signal as to whether or not to allow writing of data to the nonvolatile memory element;
First switching means for switching whether to apply a voltage corresponding to data input to the input terminal to the ferroelectric layer in accordance with a signal from the write permission terminal;
Detecting means for detecting the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer;
An output terminal for outputting the detection output of the detection means;
It is provided with.
[0010]
The data holding circuit of the present invention is
A standby terminal for inputting a signal as to whether or not the nonvolatile memory element is in a standby state;
A second switching means for interrupting a current flowing through the nonvolatile memory element in accordance with a signal from the standby terminal;
Is provided.
[0011]
The data holding circuit of the present invention is
That both an input terminal and a standby terminal were used,
It is characterized by.
[0012]
The data holding circuit of the present invention is
A current mirror circuit for forcibly setting the voltage applied to the ferroelectric layer in accordance with the signals from the write enable terminal and the input terminal;
It is characterized by.
[0013]
The data holding circuit of the present invention is
The detection means is a constant current source for supplying a constant reference current to the nonvolatile memory element;
It is characterized by.
[0014]
The data holding circuit of the present invention is
Nonvolatile memory elements
A source region and a drain region of a first conductivity type;
A channel region of a second conductivity type formed between the source region and the drain region;
A floating gate which is a conductor layer formed on the channel region and insulated from the channel region;
A ferroelectric layer formed on the floating gate;
A control gate which is a conductor layer formed on the ferroelectric layer;
It is characterized by having.
[0015]
The data writing and reading method according to the present invention includes:
A method of writing and reading data to and from a nonvolatile memory element having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage,
Give a signal whether to allow writing data,
When a signal permitting writing is given, a voltage corresponding to the given data is applied to the ferroelectric layer,
If no signal to allow writing is given, no voltage is applied to the ferroelectric layer,
Detect and output the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer,
It is characterized by that.
[0016]
[Action]
According to the data holding circuit and the data writing and reading method of the present invention , when a signal permitting writing is given, a voltage corresponding to the given data is instantaneously applied to the ferroelectric layer. When polarization is caused and a signal for permitting writing is not given, the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer can be detected and output.
[0017]
Therefore, the time required to cause polarization in the ferroelectric is extremely small compared to the time for writing data in the EEPROM. Moreover, the ferroelectric material once polarized maintains its polarization state until a voltage is next applied, and the polarization state is not lost even when the power is turned off. For this reason, after the power is turned on again, the polarization state can be detected.
[0018]
The data holding circuit of the present invention is further characterized in that a standby terminal and a second switching means for interrupting a current flowing through the nonvolatile memory element in accordance with a signal from the standby terminal are provided. Therefore, when a signal for permitting writing is not given, the standby state can be further selected. In the standby state, the current flowing through the nonvolatile memory element can be cut off by the second switching means.
[0019]
The data holding circuit according to the present invention is further characterized by using both an input terminal and a standby terminal. Therefore, it is not necessary to separately provide a standby terminal.
[0020]
The data holding circuit according to the present invention includes a current mirror circuit for forcibly setting a voltage to be applied to the ferroelectric layer in accordance with signals from a write permission terminal and an input terminal. Therefore, the voltage applied to the ferroelectric layer can be reliably set during the write operation.
[0021]
The data holding circuit of the present invention is characterized in that the detecting means is a constant current source for supplying a constant reference current to the nonvolatile memory element. Therefore, during the read operation, the polarization state of the ferroelectric substance can be detected by the change in the voltage generated at the output terminal of the constant current source corresponding to the polarization state of the ferroelectric substance.
[0022]
【Example】
FIG. 3A shows the structure of a nonvolatile memory device M according to one embodiment of the present invention. An N-type source region 22 and an N-type drain region 24 are formed on the P-type silicon substrate 20. An insulating layer 28 made of silicon oxide (SiO 2), silicon nitride (SiN), or the like is provided on the P-type channel region 26. A lower conductor layer (floating gate) 30 made of platinum or the like is provided on the insulating layer 28. A ferroelectric layer 32 such as PZT is provided thereon, and an upper conductor layer (control gate) 34 made of platinum or the like is further provided thereon.
[0023]
The lower conductor layer 30 and the upper conductor layer 34 are made of an oxide conductor such as RuOx, IrOx, or ITO, or a metal such as Pb, Au, Ag, Al, or Ni in addition to the above platinum. it can. Further, the silicon substrate 20 may be N-type, and the source region and drain region may be P-type.
[0024]
The nonvolatile memory element M of FIG. 3A is represented by a symbol as shown in FIG. 3B. A control gate electrode CG is connected to the upper conductor layer 34, a floating gate electrode FG is connected to the lower conductor layer 30, a source electrode S is connected to the source region 22, and a drain electrode D is connected to the drain region 24. Is connected.
[0025]
When recording information in the nonvolatile memory element M, a voltage is applied between the control gate electrode CG and the floating gate electrode FG. Thereby, the ferroelectric layer 32 is polarized, and the polarization state is maintained even after the voltage is removed. By changing the polarity of the applied voltage, two polarization states with different polarities can be obtained.
[0026]
For example, when a low voltage is applied to the floating gate electrode FG with respect to the control gate electrode CG side, the ferroelectric layer 32 is polarized with the control gate electrode CG side having a negative polarity (polarized to the second state). On the other hand, when a high voltage is applied to the floating gate electrode FG side, the ferroelectric layer 32 is polarized with the control gate electrode CG side being positive (polarized to the first state). In this way, the two states can be recorded in a nonvolatile manner.
[0027]
When the control gate electrode CG side is polarized with the negative electrode (when polarized to the second state), the voltage of the control gate electrode CG necessary for forming the channel is small. In addition, when the control gate electrode CG side is polarized with the positive electrode (when polarized to the first state), the voltage of the control gate electrode CG necessary for forming a channel increases. Therefore, the recorded information can be read by supplying a constant current to the drain electrode D and detecting the voltage generated in the control gate electrode CG.
[0028]
The above relationship will be described with reference to the characteristic curve of FIG. 4A measured by the circuit of FIG. 4B. In FIG. 4A, a curve β shows the characteristics of the control gate voltage VCG and the drain current ID when the control gate electrode CG and the floating gate electrode FG are short-circuited. As the control gate voltage VCG increases, the drain current ID increases. When the control gate voltage VCG is further increased, the drain current stops increasing at the set maximum drain current IOMAX determined by the resistor R.
[0029]
A curve α indicates a characteristic when the ferroelectric layer 32 is polarized (when polarized to the second state) with the control gate electrode CG side as a negative electrode. Although the same tendency as in the case of the curve β is shown, the drain current flows with a small control gate voltage VCG due to the influence of the polarization of the ferroelectric layer 32. Further, the drain current reaches the set maximum drain current IOMAX with a small control voltage VCG.
[0030]
A curve γ shows characteristics when the ferroelectric layer 32 is polarized (when polarized to the first state) with the control gate electrode CG side as the positive electrode. Although the same tendency as in the case of the curve β is shown, the drain current starts to flow at a large control gate voltage VCG due to the influence of the polarization of the ferroelectric layer 32. Also, the drain current reaches the set maximum drain current IOMAX at a large control voltage VCG, and the increase stops.
[0031]
At the time of reading, for example, a current Is that is half the set maximum drain current IOMAX is supplied to the drain electrode D by a constant current source. At this time, the stored information can be known based on whether the control gate voltage VCG generated in the control gate electrode CG is smaller (point X) or larger (point Y) than the reference voltage Vref. Here, the reference voltage Vref is a voltage generated in the control gate electrode CG when a current Is is supplied as a drain current in the curve β.
[0032]
Next, a latch circuit 2 which is a data holding circuit using the nonvolatile memory element M of FIG. 3B is shown in FIG. The drain electrode D and the control gate electrode CG of the nonvolatile memory element M are short-circuited and connected to the constant current source 4. The constant current source 4 is connected to a power supply terminal 6 connected to a constant voltage source VCC (not shown), and is configured to generate a current IS (reference current) that is half of the set maximum drain current IOMAX. The control gate electrode CG is connected to the output terminal Q.
[0033]
The source electrode S of the nonvolatile memory element M is grounded via an N-channel transistor QN3 which is a second switching means. The gate electrode of the transistor QN3 is connected to an input terminal DT that is also a standby terminal SB (low active).
[0034]
The floating gate electrode FG of the nonvolatile memory element M is connected to the input terminal DT via a P-channel transistor QP3 which is a first switching means. The gate electrode of the transistor QP3 is connected to the write permission terminal WE (low active). The floating gate electrode FG is grounded via an N-channel transistor QN2.
[0035]
The P-channel transistors QP1 and QP2 and the N-channel transistor QN1 are connected in series between the power supply terminal 6 connected to the constant voltage source VCC and the ground G. The gate electrode of the transistor QP1 is connected to the write enable terminal WE, and the gate electrode of the transistor QP2 is connected to the input terminal DT.
[0036]
The drain electrode and gate electrode of transistor QN1 are short-circuited. The gate electrode of transistor QN1 is connected to the gate electrode of transistor QN2. In other words, the transistor QN1 and the transistor QN2 constitute a current mirror circuit 8.
[0037]
Next, the write, read and standby operations for the latch circuit 2 will be described based on FIG. 1 with reference to FIG. First, the write operation will be described. When writing, “L (ground potential)” is input to the write enable terminal WE. As a result, the transistors QP1 and QP3 are turned “ON”.
[0038]
Further, data to be written is input to the input terminal DT. When the input value of the input terminal DT is “L”, the input value “L” is applied to the floating gate electrode FG of the nonvolatile memory element M through the transistor QP3 which is “ON”.
[0039]
For this reason, the N-channel nonvolatile memory element M is “OFF”, and the drain current of the nonvolatile memory element M does not flow. Therefore, the potential of the control gate electrode CG connected to the drain electrode D of the nonvolatile memory element M is lifted by the constant current source 4 and becomes “H”. For this reason, a potential difference is generated between the floating gate electrode FG and the control gate electrode CG, and the ferroelectric layer 32 is polarized to the second state (see FIG. 4A).
[0040]
Note that when “L” is input to the input terminal DT, the transistor QN3 is turned “OFF”. Therefore, the drain current can be cut off more reliably, and the potential of the control gate electrode CG of the nonvolatile memory element M can be reliably set to “H”.
[0041]
Further, when “L” is input to the input terminal DT, the transistor QP2 is turned “ON”. Therefore, a drain current is supplied to one transistor QN1 constituting current mirror circuit 8 via transistors QP1 and QP2. Therefore, the other transistor QN2 constituting the current mirror circuit 8 also tries to flow a drain current having the same magnitude as that of the transistor QN1. For this reason, the potential of the floating gate electrode FG can be more reliably dropped to “L”.
[0042]
On the other hand, when the input value of the input terminal DT is “H”, the input value “H” is applied to the floating gate electrode FG of the nonvolatile memory element M through the transistor QP3 which is “ON”. The
[0043]
For this reason, the N-channel nonvolatile memory element M is “ON”. Further, since the input terminal DT is “H”, the transistor QN3 connected to the source electrode of the nonvolatile memory element M is also “ON”. For this reason, the drain current of the nonvolatile memory element M flows. Therefore, the potential of the control gate electrode CG of the nonvolatile memory element M is “L”. For this reason, a potential difference in the opposite direction to that described above is generated between the floating gate electrode FG and the control gate electrode CG, and the ferroelectric layer 32 is polarized in the first state (see FIG. 4A).
[0044]
Note that when “H” is input to the input terminal DT, the transistor QP2 is turned “OFF”. Therefore, the current mirror circuit 8 does not operate. For this reason, the floating gate electrode FG of the nonvolatile memory element M does not fall to “L”.
[0045]
Next, the reading operation will be described. When reading, “H” is input to the write enable terminal WE. As a result, the transistor QP1 is turned “OFF”. Therefore, the transistors QN1 and QN2 constituting the current mirror circuit 8 are “OFF”. Further, the transistor QP3 is also “OFF”. Therefore, the floating gate electrode FG of the nonvolatile memory element M is in a floating state. For this reason, no potential difference is generated between the floating gate electrode FG and the control gate electrode CG, and the polarization state of the ferroelectric layer 32 does not change.
[0046]
Further, “H” is input to the standby terminal SB (input terminal DT). As a result, the transistor QN3 is turned “ON”. Therefore, a constant current Is is supplied from the constant current source 4 to the drain electrode D of the nonvolatile memory element M. Therefore, a control gate voltage VCG corresponding to the polarization state of the ferroelectric layer 32 is generated at the control gate electrode CG of the nonvolatile memory element M.
[0047]
For example, when the ferroelectric is polarized in the second state (see FIG. 4A), the control gate voltage VCG corresponding to the point X shown in FIG. 4A is generated in the control gate electrode CG of the nonvolatile memory element M. . This control gate voltage VCG is smaller than the reference voltage Vref. Therefore, the potential of the control gate electrode CG, that is, the potential of the output terminal Q is “L”. As described above, the second state occurs when data “L” is input to the input terminal and a write operation is performed. That is, by the reading operation, the same value as the data “L” input to the input terminal DT is output to the output terminal Q.
[0048]
On the other hand, when the ferroelectric is polarized in the first state (see FIG. 4A), the control gate voltage VCG corresponding to the Y point shown in FIG. 4A is generated in the control gate electrode CG of the nonvolatile memory element M. . This control gate voltage VCG is larger than the reference voltage Vref. Therefore, the potential of the control gate electrode CG, that is, the potential of the output terminal Q is “H”. Also in this case, the same value as the data “H” input to the input terminal DT is output to the output terminal Q.
[0049]
Next, the standby operation will be described. When the standby operation is performed, “H” is input to the write enable terminal WE. As a result, the transistors QP1 and QP3 are turned “OFF”. For this reason, as in the read operation, the floating gate electrode FG of the nonvolatile memory element M is in a floating state, and no potential difference is generated between the floating gate electrode FG and the control gate electrode CG. The polarization state of 32 does not change.
[0050]
Further, “L” is input to the standby terminal SB (input terminal DT). As a result, the transistor QN3 is turned “OFF”. Therefore, no drain current flows through the nonvolatile memory element M regardless of the polarization state of the ferroelectric layer 32. Therefore, the power consumption during the standby operation can be extremely reduced.
[0051]
In the above-described embodiment, the current IS which is half the set maximum drain current IOMAX is used as the reference current supplied from the constant current source 4. However, if a control gate voltage VCG different depending on the polarization state can be obtained. For example, a current having any value less than or equal to the set maximum drain current IOMAX may be used as the reference current.
[0052]
Further, although the current mirror circuit 8 forcibly setting the voltage applied to the ferroelectric layer 32 is used, a latch circuit can be configured without using the current mirror circuit 8.
[0053]
In addition, although the input terminal DT and the standby terminal SB are used in common, the input terminal DT and the standby terminal SB may be provided separately. Further, the latch circuit can be configured without providing the standby terminal SB.
[0054]
Further, the constant current source 4 is used as the detecting means and the control gate voltage VCG is detected when the drain current ID is constant. However, the constant voltage source is used as the detecting means and the control gate voltage VCG is constant. The drain current ID may be detected.
[0055]
As a nonvolatile memory element, a nonvolatile memory element M including a source region 22, a drain region 24, a channel region 26, an insulating layer 28, a floating gate 30, a ferroelectric layer 32, and a control gate 34 shown in FIG. 3A. However, the present invention is not limited to this. As the nonvolatile memory element, for example, a three-layered element in which both sides of the ferroelectric layer are sandwiched between conductor layers can be used.
[0056]
In the above embodiment, the two polarization states corresponding to the forward and reverse (polarity) of the direction of the voltage applied between the floating gate electrode FG and the control gate electrode CG are set. It can also be configured to set two polarization states corresponding to the magnitude of the voltage applied between the electrode FG and the control gate electrode CG.
[0057]
Further, two polarization states corresponding to the polarity and magnitude of the voltage applied between the floating gate electrode FG and the control gate electrode CG can be set.
[0058]
Furthermore, not only two polarization states but also three or more polarization states can be set. In a case where three or more polarization states are set, data (multi-value data) having three or more states can be stored in one nonvolatile memory element.
[0059]
The circuit shown in FIG. 1 exemplifies one embodiment of the present invention, and the present invention is not limited to the circuit shown in FIG. In the above-described embodiments, the case where the present invention is applied to the latch circuit has been described as an example. However, the present invention is not limited to the latch circuit, and a high-speed response such as a flip-flop and a register is required. Applicable to data holding circuit in general.
[0060]
【The invention's effect】
According to the data holding circuit and the data writing and reading method of the present invention , when a signal permitting writing is given, a voltage corresponding to the given data is instantaneously applied to the ferroelectric layer. When polarization is caused and a signal for permitting writing is not given, the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer can be detected and output.
[0061]
Therefore, the time required to cause polarization in the ferroelectric is extremely small compared to the time for writing data in the EEPROM or the like. Moreover, the ferroelectric material once polarized maintains its polarization state until a voltage is next applied, and the polarization state is not lost even when the power is turned off. For this reason, after the power is turned on again, the polarization state can be detected. That is, it is possible to obtain a data holding circuit that does not require a power supply for holding data and can respond at high speed.
[0062]
The data holding circuit of the present invention is further characterized in that a standby terminal and a second switching means for interrupting a current flowing through the nonvolatile memory element in accordance with a signal from the standby terminal are provided.
[0063]
Therefore, when a signal for permitting writing is not given, the standby state can be further selected. In the standby state, the current flowing through the nonvolatile memory element can be cut off by the second switching means. That is, in the standby state, a data holding circuit with extremely small power consumption can be obtained.
[0064]
The data holding circuit according to the present invention is further characterized by using both an input terminal and a standby terminal. Therefore, it is not necessary to separately provide a standby terminal. That is, it is possible to obtain a compact data holding circuit that consumes very little power in the standby state.
[0065]
The data holding circuit according to the present invention includes a current mirror circuit for forcibly setting a voltage to be applied to the ferroelectric layer in accordance with signals from a write permission terminal and an input terminal.
[0066]
Therefore, the voltage applied to the ferroelectric layer can be reliably set during the write operation. That is, a more reliable data holding circuit can be obtained.
[0067]
The data holding circuit of the present invention is characterized in that the detecting means is a constant current source for supplying a constant reference current to the nonvolatile memory element.
[0068]
Therefore, during the read operation, the polarization state of the ferroelectric substance can be detected by the change in the voltage generated at the output terminal of the constant current source corresponding to the polarization state of the ferroelectric substance. That is, the polarization state of the ferroelectric can be detected more easily.
[Brief description of the drawings]
FIG. 1 shows a latch circuit according to an embodiment of the present invention.
FIG. 2 is a diagram showing a write operation, a read operation, and an input / output state in a standby state in a latch circuit according to an embodiment of the present invention;
FIG. 3 is a drawing showing a configuration of a nonvolatile memory element constituting a latch circuit according to one embodiment of the present invention, and a drawing showing the nonvolatile memory element by symbols.
FIG. 4 is a drawing showing electrical properties of a ferroelectric layer of a nonvolatile memory element constituting a latch circuit according to an embodiment of the present invention and a circuit for measuring electrical properties.
FIG. 5 is a drawing showing a static type D latch circuit using a conventional CMOS, and a timing diagram showing the operation of the D latch circuit.
[Explanation of symbols]
32... Ferroelectric layer CG ... Control gate electrode D ... Drain electrode DT ... Input terminal FG ... Floating gate electrode IS ··· Reference current QN3 ··· Transistor QP3 ··· Transistor SB ··· Standby terminal VCG ··· Control gate voltage WE ··· Write Permission terminal

Claims (11)

A non-volatile memory device having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage;
An input terminal for inputting data to be written to the nonvolatile memory element;
A write enable terminal for inputting a signal as to whether or not to allow writing of data to the nonvolatile memory element;
First switching means for switching whether to apply a voltage corresponding to data input to the input terminal to the ferroelectric layer in accordance with a signal from the write permission terminal;
Detecting means for detecting the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer;
An output terminal for outputting the detection output of the detection means;
In a data holding circuit comprising
Short-circuit the drain region of the nonvolatile memory element and the control gate and connect to the detection means,
The input terminal is connected to the floating gate of the nonvolatile memory element.
A data holding circuit. A non-volatile memory device having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage;
An input terminal for inputting data to be written to the nonvolatile memory element;
A write enable terminal for inputting a signal as to whether or not to allow writing of data to the nonvolatile memory element;
First switching means for switching whether to apply a voltage corresponding to data input to the input terminal to the ferroelectric layer in accordance with a signal from the write permission terminal;
Detecting means for detecting the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer;
An output terminal for outputting the detection output of the detection means;
In a data holding circuit comprising
A standby terminal for inputting a signal indicating whether the nonvolatile memory element is in a standby state or a read state when a signal for permitting writing is not provided from the write permission terminal;
A second switching means for interrupting a current flowing through the nonvolatile memory element in accordance with a signal from the standby terminal;
A data holding circuit comprising: The data holding circuit according to claim 2,
That both an input terminal and a standby terminal were used,
It is characterized by. In the data holding circuit according to any one of claims 1 to 3,
A current mirror circuit for forcibly setting the voltage applied to the ferroelectric layer in accordance with signals from the write permission terminal and the input terminal or the write permission terminal and the standby terminal ;
It is characterized by. In the data holding circuit according to any one of claims 1 to 4,
The detection means is a constant current source for supplying a constant reference current to the nonvolatile memory element;
It is characterized by.   A source region and a drain region of a first conductivity type;
  A channel region of a second conductivity type formed between the source region and the drain region;
  A floating gate which is a conductor layer formed on the channel region and insulated from the channel region;
  A ferroelectric layer formed on the floating gate, rewritably holding at least two polarization states corresponding to the magnitude and polarity of the applied voltage;
  A control gate which is a conductor layer formed on the ferroelectric layer;
  A method for writing data to a nonvolatile memory element in which a drain region and a control gate are short-circuited and connected to a current source,
  By flowing a drain current through the nonvolatile memory element, a voltage is not directly applied from the current source to the control gate gate, and a desired potential difference is set between the floating gate and the control gate of the nonvolatile memory element. By applying the resulting voltage, the ferroelectric layer is polarized to the first state;
  By preventing drain current from flowing through the nonvolatile memory element, a voltage is directly applied from the current source to the control gate, and a desired potential difference is established between the floating gate and the floating gate of the nonvolatile memory element. Polarizing the ferroelectric layer to a second state by applying a voltage that produces
  It is characterized by that.   A non-volatile memory device having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage;
  An input terminal for inputting data to be written to the nonvolatile memory element;
  A write enable terminal for inputting a signal as to whether or not to allow writing of data to the nonvolatile memory element;
  First switching means for switching whether to apply a voltage corresponding to data input to the input terminal to the ferroelectric layer in accordance with a signal from the write permission terminal;
  Detecting means for detecting the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer;
  An output terminal for outputting the detection output of the detection means;
  A method for writing and reading data to and from a data holding circuit comprising:
  When a signal to allow writing is not given from the write permission terminal, a signal indicating whether the nonvolatile memory element is in a standby state or a reading state is input from the standby terminal,
  The second switching means cuts off the current flowing through the nonvolatile memory element in accordance with a signal from the standby terminal.   A non-volatile memory device having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage;
  An input terminal for inputting data to be written to the nonvolatile memory element;
  A write enable terminal for inputting a signal as to whether or not to allow writing of data to the nonvolatile memory element;
  First switching means for switching whether to apply a voltage corresponding to data input to the input terminal to the ferroelectric layer in accordance with a signal from the write permission terminal;
  A standby terminal for inputting a signal as to whether or not the nonvolatile memory element is in a standby state;
  A second switching means for interrupting a current flowing through the nonvolatile memory element in accordance with a signal from the standby terminal;
  Detecting means for detecting the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer;
  An output terminal for outputting the detection output of the detection means;
  In a data holding circuit characterized by comprising:
  That both an input terminal and a standby terminal were used,
  A data holding circuit.   A non-volatile memory device having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage;
  An input terminal for inputting data to be written to the nonvolatile memory element;
  Write permission to input a signal indicating whether to allow writing data to the non-volatile memory element Terminal,
  First switching means for switching whether to apply a voltage corresponding to data input to the input terminal to the ferroelectric layer in accordance with a signal from the write permission terminal;
  Detecting means for detecting the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer;
  An output terminal for outputting the detection output of the detection means;
  In a data holding circuit comprising
  A current mirror circuit for forcibly setting the voltage applied to the ferroelectric layer in accordance with the signals from the write enable terminal and the input terminal;
  A data holding circuit.   A non-volatile memory device having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage;
  An input terminal for inputting data to be written to the nonvolatile memory element;
  A write enable terminal for inputting a signal as to whether or not data write to the nonvolatile memory element is permitted;
  First switching means for switching whether to apply a voltage corresponding to data input to the input terminal to the ferroelectric layer in accordance with a signal from the write permission terminal;
  A standby terminal for inputting a signal as to whether or not the nonvolatile memory element is in a standby state;
  A second switching means for interrupting a current flowing through the nonvolatile memory element in accordance with a signal from the standby terminal;
  Detecting means for detecting the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer;
  An output terminal for outputting the detection output of the detection means;
  In a data holding circuit comprising
  A current mirror circuit for forcibly setting the voltage applied to the ferroelectric layer in accordance with signals from the write permission terminal and the input terminal or the write permission terminal and the standby terminal;
  A data holding circuit.   A non-volatile memory device having a ferroelectric layer that rewriteably holds at least two polarization states corresponding to the magnitude and polarity of an applied voltage;
  An input terminal for inputting data to be written to the nonvolatile memory element;
  A write enable terminal for inputting a signal as to whether or not data write to the nonvolatile memory element is permitted;
  First switching means for switching whether to apply a voltage corresponding to data input to the input terminal to the ferroelectric layer in accordance with a signal from the write permission terminal;
  A standby terminal for inputting a signal as to whether or not the nonvolatile memory element is in a standby state;
  A second switching means for interrupting a current flowing through the nonvolatile memory element in accordance with a signal from the standby terminal;
  Detecting means for detecting the state of the nonvolatile memory element corresponding to the polarization state of the ferroelectric layer;
  An output terminal for outputting the detection output of the detection means;
  In a data holding circuit that serves both as an input terminal and a standby terminal,
  A current mirror circuit for forcibly setting the voltage applied to the ferroelectric layer in accordance with signals from the write permission terminal and the input terminal or the write permission terminal and the standby terminal;
  A data holding circuit.

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