KR0145227B1 - Column decoder circuit of semiconductor memory to reduce cell stress - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs;

A circuit of a column decoder for controlling a string select transistor and a cell transistor is provided.

2. The technical problem to be solved by the invention;

Provided is a column decoder circuit for applying a low voltage to all word lines in the standby state to which a power supply voltage is applied so that stress is not applied to the gate oxide layer.

3. Summary of the Solution of the Invention;

When the operation is in the standby state, it is turned off, and the voltage of the enhancement transistor unit for applying the string selection signal and the cell selection signal to the drain, the depletion transistor unit for controlling the string selection transistor, and the output terminal of the depletion transistor unit is applied. An inverter means for inverting and one side of the inverter means is connected to the output terminal of some inverters, the other side is always applied a high voltage in the standby state, the output terminal is connected to the gate of the cell transistor, respectively, always in the word line in the standby state It is essential to have a plurality of noah gates that maintain the low voltage state and thereby reduce the cell stress of the cell array.

4. Important uses of the invention

It is suitably used for the column decoder circuit of the semiconductor memory device.

Description

A column decoder circuit in a semiconductor memory device for reducing cell stress.

1 is a circuit diagram of a conventional nonvolatile semiconductor memory device.

2 is a circuit diagram of a nonvolatile semiconductor memory device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit of a column decoder for controlling a string select transistor and a cell transistor. In particular, a stress is applied to a gate oxide layer by applying a low voltage to all word lines in a standby state to which a power supply voltage is applied. The present invention relates to a column decoder circuit of the semiconductor memory device for preventing the addition.

In general, when reading the data recorded in the mask ROM adopting the NAND structure, an appropriate voltage is applied from the sense amplifier, and a low voltage (low) is applied to a word line connecting a cell to be read among a plurality of cells in which data is written. A high voltage (high) is applied to the remaining word lines, and the sense amplifier recognizes and outputs a difference between the high and low of the bit line that changes according to the data content of the corresponding cell.

In the standby state in which the data is not read in the above-described structure, the same voltage as the power supply voltage is applied to all the word lines, and as the degree of integration increases, the area of the cell array in which the gate oxide film is formed is larger than the peripheral circuit. Since the thickness of the thin film is also formed in the inspection step, the voltage of the gate oxide film is applied for a long time, which may cause damage to the gate oxide film of the cell array unit due to voltage stress caused by an electric field, which may lead to a decrease in yield, and some of the potential defect factors. It can affect the reliability and cause quality problems.

1 is a circuit diagram of a conventional nonvolatile semiconductor memory device. As shown in FIG. 1, a string line of a string select transistor constituting the string select transistor unit 100 and a channel of a cell transistor below the string string is connected in series to a ground voltage and bit lines connected to an end of a pair of the strings. And an enhancement transistor (2, 3) in which the cell array unit is turned off when in the standby state, and the first and second string selection signals (SS1, SS2) and the cell selection signals (S1-Sn) are applied as drains. , 4, 5, 6, depletion transistors 7, 8, 9, 10, and 11 for controlling the string select transistor and applying a power supply voltage to the drain, and the depletion transistors 7, Output terminals of the first inverters 12, 13, 14, 15, and 16 and the inverters 14, 15, and 16 of the first inverters that invert the voltage of the output terminals of the 8, 9, 10, and 11; Connected to maintain the high voltage at all times in the word line when in the standby state. It consists of a thermal decoder consisting of two inverters (17, 18, 19).

Therefore, in the standby state, the node A becomes a low voltage and the enhancement transistor whose voltage is applied to the gate is turned off so that the nodes C1 and C2 are in a low voltage state, but the nodes E1-En are in a high voltage state and the standby There is a problem that the state continues to be stressed.

Accordingly, an object of the present invention is to provide a thermal decoder circuit for applying a low voltage to all word lines in the standby state to which a power supply voltage is applied so that stress is not applied to the gate oxide layer of the cell array unit.

According to the technical idea of the present invention to achieve the above object, the control unit is configured to control the string selection transistor and the enhancement transistors which are turned off when the operation is in the standby state and the string selection signal and the cell selection signal are applied to the drain. Depletion transistors in which a power supply voltage is applied to the drain, inverters for inverting the voltage of the output terminal of the depletion transistor, connected to the output terminal of some inverters of the inverters on one side and always high when the standby state is on the other side. The voltage is applied and the output terminal is connected to the gate of the cell transistor, respectively, characterized in that it has a plurality of NOA gates to reduce the cell stress of the cell array by always maintaining a low voltage state on the word line in the standby state.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a nonvolatile semiconductor memory device having a thermal decoder and a cell array unit according to an embodiment of the present invention.

As shown in FIG. 2, the second inverters 17, 18, and 19 of FIG. 1 are replaced by a plurality of Noah gates 20, 21, and 22 to maintain a low voltage at the word line at all times. By doing so, there is an effect that can reduce the stress generated in the gate oxide film. Detailed operation description is as follows.

In a standby state where a power supply voltage is applied and no data is read, a low voltage is applied to the node A to turn off the enhancement transistors 2, 3, 4, 5, and 6. As a result, the nodes B1 and B2 controlling the string select transistor are all at a high voltage due to the influence of the depletion transistors 7, 8, 9, 10, and 11, and the nodes C1 and C2 are at a low voltage. Each string prevents current from flowing from the bit line to ground (GND).

Nodes E1 and E2-En that control the cell transistors are the subject matter of the present invention, although node A is a low voltage and nodes D1 -Dn are a low voltage, but each of the noah gates 20, 21, and 22 depends on each other. Since one input is controlled by a signal CEt and the CEt is always at a high voltage during standby, the nodes E1-En remain at a low voltage so that all cell arrays are not stressed.

On the other hand, in the operating state, node A is in a high voltage state, and the state of the nodes B1, B2, D1-Dn is determined by the S or SS signal at the drain, and the CEt signal is also in a low voltage state. The voltage state determines the voltage state of the nodes E1-En. When a low voltage is applied to SS1, which is a signal for selecting a string transistor, and a high voltage is applied to SS2, all low voltages are applied to gates of the string controlled by SS1, so that the right string of all bit lines is selected. In addition, S1-Sn becomes low voltage with only one S signal, and the E signal, which is the corresponding signal, becomes high voltage and senses whether the current flows from the bit line to the ground by the selected cell and outputs data. .

The present invention described above has been limited to, for example, the drawings, but the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (3)

The string selection transistor and the cell transistor of the semiconductor memory device having a cell array portion having a channel of the string selection transistors and the cell transistors are connected to the ground terminal in series and a bit line connected to the end of the pair of the NAND strings. CLAIMS 1. A column decoder circuit for controlling; Enhancement transistors that are turned off when the operation is in a standby state and to which a string selection signal and a cell selection signal are applied to a drain; Depletion transistors for controlling the string select transistor and applying a power supply voltage to a drain; Inverter means for inverting the voltage at the output terminal of the depletion transistor section; One side is connected to the outputs of some inverters of the inverter means, and the other side is always applied with a high voltage when in the standby state, and the output terminal is connected to the gate of the cell transistor, respectively, so that the voltage line is always maintained at the word line during the standby state. And a plurality of gating means for reducing the cell stress of the cell array. The method of claim 1; And a power supply voltage is applied to the drains of the depletion transistors. The method of claim 1; And said gating means comprises a noah gate.