JPH1153890A - Flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute detection of gate disturbing in a short time by providing a monitoring memory cell for connecting a control gate to a word line of a memory cell array, and a monitoring bit line connected to a drain of the cell. SOLUTION: Monitoring memory cells 1a, 1b control so that a memory VTH at the time of erasing becomes between a first threshold voltage V1 and a second threshold voltage V2. The relationship among a reading voltage VR of the cell, erase verify voltage VE and read voltages V3 of the cells 1a, 1b is set to VR<=V3<V1<V3<VE. The cells 6b to 6n can normally read as long as the memory VTH is not shifted. But, occurrence of gate disturbing of the cells 1a, 1b can be detected by a comparison result of the read value of the cell with an expected value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory capable of efficiently detecting gate disturbance generated at the time of data writing, and more particularly to a flash memory for writing data.
The present invention relates to a flash memory utilizing the N tunnel phenomenon.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram showing a part of the configuration of a conventional flash memory. In the figure, 6a to 6n,
7a to 7n are memory cells, 5a and 5b are memory cells 6a
To 6n and 7a to 7n respectively connected to the control gates, 8a is a bit line connected to the drains of the memory cells 6a and 7a, and 8b is connected to the drains of the memory cells 6b and 7b. Bit lines 8n are bit lines connected to the drains of the memory cells 6n and 7n, and 9 is a memory cell array. FIG. 8 shows the memory cell 6 shown in FIG.
It is an equivalent circuit of the sectional structure of a and 6b. In the figure, 1
5 is a P base, 16b is an N-well formed on the P base 15, 17b is a P-well formed in the N-well 16b, 20a and 20b are floating gates, 21
a and 21b are control gates, 22a is a bit line 8
a, a drain connected to the bit line 8b, and 23a, 23b a source connected to the source line 3.

Hereinafter, a writing operation of a conventional flash memory will be described. When writing to the memory cell 6a, a voltage of -11 V is applied to the word line 5a and a voltage of 12 V is applied to the bit line 8a. The P-well 17b is at 0V, and the source line 3 and the bit line 8b are floating. In the memory cell 6a, the electrons stored in the floating gate 20a are drawn out to the drain 22a by the FN tunnel phenomenon due to the electric field between the control gate 21a and the drain 22a, and writing is performed. At this time, even in the memory cell 6b where writing is not performed, electrons are extracted from the floating gate 20b due to the electric field between the control gate 21b and the P-well 17b, and the memory threshold voltage (hereinafter, referred to as VTH) decreases. This phenomenon is a so-called gate disturbance. A flash memory that uses the FN tunnel phenomenon for writing has a gate disturb due to its structure. Therefore, every time writing is performed, the gate disturb is detected, and erase is performed on a memory cell whose memory VTH is reduced. There is a need.

A memory V of a memory cell to which writing is not performed
In order to detect the decrease in TH, the first time the normal read voltage is applied to the gates of all the memories connected to the word line connected to the memory cell to which the data has been written is connected every time the data is written. Is read. Thereafter, the second read is performed with the erase verify voltage applied to the gate. This reading is performed for each unit defined by the number of sense amplifiers. Then, by comparing the read data after the reading is completed, a decrease in the memory VTH is detected.

[0005]

Since the conventional flash memory is configured as described above, it is necessary to read twice from the same memory in order to detect gate disturb, and the read unit is a sense unit. Since it is limited by the number of amplifiers, it takes time to detect gate disturb, and when the number of memory cells connected to the word line is increased, the detection time becomes longer.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a flash memory capable of detecting gate disturbance in a short time.

[0007]

According to a first aspect of the present invention, there is provided a flash memory in which a control gate is connected to a monitor memory cell connected to a word line of a memory cell array and a drain of the monitor memory cell. And a monitor bit line.

According to a second aspect of the present invention, there is provided a flash memory, comprising: a memory cell array including a plurality of memory cells whose memory threshold voltage at the time of erasing is equal to or higher than an erase verify voltage; and a control gate of the memory cells and a memory cell for monitoring. A word line connected to a control gate, and a bit line connected to the drain of the memory cell; the control gate is connected to the control gate of the memory cell by a word line; and the initial memory threshold voltage is The voltage is controlled within a voltage range between a second threshold voltage lower than the erase verify voltage and a first threshold voltage lower than the second threshold voltage, and after writing data to the memory cell array, a voltage equal to or higher than a read voltage for the memory cell. And a monitor whose contents are read at a monitor cell read voltage lower than the first threshold voltage. It is obtained so as to comprise a memory cell.

According to a third aspect of the present invention, there is provided a flash memory including a plurality of monitoring memory cells each of which has a control gate connected in parallel to a control gate of a memory cell of a memory cell array by a word line. It is.

According to a fourth aspect of the present invention, there is provided a flash memory, comprising: a memory cell array including a plurality of memory cells having a memory threshold voltage at the time of erasing between an erase verify voltage and a fourth threshold voltage higher than the erase verify voltage; ,
A word line connected to a control gate of the memory cell, a bit line connected to a drain of the memory cell, an initial state is an erased state, and a memory threshold voltage at the time of erasing is equal to or higher than the erase verify voltage; 4 threshold voltage or less, and after writing data to the memory cell array,
A plurality of monitor memory cells having respective control gates connected in parallel to the word line, the contents of which are read at a monitor cell read voltage between the erase verify voltage and the read voltage of the memory cell; And a monitor bit line connected to the drain of the memory cell.

A flash memory according to a fifth aspect of the present invention, wherein the conduction / non-conduction state is controlled to perform erase verification of a monitor memory cell simultaneously with write verification of a memory cell of a memory cell array. A first switch connected to a word line between a cell and a control gate of the monitor memory cell; and a second switch connected between a control gate of the monitor memory cell and an erase verify voltage input terminal. It is like that.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a part of the flash memory according to the first embodiment of the present invention.
In the figure, reference numeral 1a designates a control gate as a word line 5a.
, And the monitor memory cell 1b whose source is connected to the source line 3 has a control gate connected to the word line 5b.
And a monitor memory cell 2 whose source is connected to the source line 3 is a monitor bit line connected to the drains of the monitor memory cells 1a and 1b. 6a-6
n, 7a to 7n are memory cells, 5a and 5b are word lines connected to control gates of memory cells 6a to 6n and 7a to 7n, respectively, and 8a is a bit line connected to drains of memory cells 6a and 7a. , 8
b is a bit line connected to the drains of the memory cells 6b and 7b, 8n is a bit line connected to the drains of the memory cells 6n and 7n, and 9 is a memory cell array.

FIG. 2 shows the memory cells 6a to 6n, 7a of FIG.
To 7n and the memory V of the monitor memory cells 1a and 1b
FIG. 7 is an explanatory diagram showing a management range of TH, in which a horizontal axis represents a memory VT
H is shown. In the figure, 100 is a memory VTH when erasing the monitor memory cells 1a and 1b, and 101 is a memory VTH when erasing the memory cells 6a to 6n and 7a to 7n.
Is a maximum allowable shift width of the memory VTH of the monitoring memory cells 1a and 1b.

The monitor memory cells 1a and 1b are controlled so that the memory VTH at the time of erasing is between V1 (first threshold voltage) and V2 (second threshold voltage). Assuming that the read voltage of the memory cell is VR, the erase verify voltage is VE, and the read voltage of the monitor memory cells 1a and 1b is V3, VR ≦ V3 <
V1 <V2 <VE. When writing is performed on the memory cell 6a, -11V is also applied to the control gate of the monitoring memory cell 1a to which the same word line 5a as the memory cell 6a is connected. After the write verify of the memory cell 6a, the contents of the monitor memory cell 1a are read at the read voltage V3. Monitor memory cell 1
The read values a and 1b are inverted from the expected value when the memory VTH shifts by (V2−V3) or more, but the memory cells 6b to 6n can perform normal reading unless the memory VTH shifts by (VE−VR). It is. Therefore, the fact that gate disturbance occurs in the monitoring memory cells 1a and 1b and the memory VTH is shifted by (V2−V3) or more is detected from the comparison result between the read value and the expected value of the monitoring memory cell. By doing so, it is possible to detect the gate disturbance of the memory cell.

As described above, in the first embodiment, reading from the monitoring memory cell 1a is performed, and the read value and the expected value are compared. When the monitor memory cell 1a is read at the read voltage V3 (VR ≦ V3 <V1 <V2 <VE), the read value differs from the expected value (corresponding to a state different from the erase state of the monitor memory cell). In this case, the memory VTH of the monitor memory cell 1a has decreased due to the gate disturb.
At this time, the memory VTH is similarly applied to the memory cells 6b to 6n.
Readout characteristics are degraded due to the decrease in As described above, there is an effect that a flash memory that can determine whether or not the memory cells 6b to 6n cannot be normally read due to the gate disturb can be obtained. Further, since the gate disturbance for each common word line can be detected by the monitoring memory cell, there is an effect that a flash memory capable of shortening the gate disturbance detection time can be obtained.

Embodiment 2 FIG. 3 is a circuit diagram showing a configuration of a part of the flash memory according to the second embodiment of the present invention. In FIG. 3, the same or corresponding parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, reference numerals 1a, 1c and 1x denote monitoring memory cells whose control gates are connected to a word line 5a, 1b, 1d and 1x.
y is a monitor memory cell whose control gate is connected to the word line 5b. Monitor memory cells 1a, 1
The sources of c and 1x are connected to the source line 3 and the drain is connected to the monitoring bit line 2.

FIG. 4 shows the memory cells 6a to 6 shown in FIG.
FIG. 7 is an explanatory diagram showing a management range of the memory VTH of n, 7a to 7n and the monitoring memory cells 1a and 1b, and the horizontal axis represents the memory VTH. In the figure, reference numeral 103 denotes monitor memory cells 1a and 1b and memory cells 6a to 6n,
Management value of memory VTH at the time of erasing of 7a to 7n, 102a
Is a maximum allowable shift width of the memory VTH of the monitor memory cells 1a and 1b, and 102b is a shift width of the memory VTH of the memory cell.

The memory cells 1a and 1b for monitoring and the memory cells 6a to 6n and 7a to 7n
H is controlled to fall between the erase verify voltages VE and V4 (fourth threshold voltage). The read voltage of the memory cell is V
R, assuming that the read voltage of the monitor memory cell is V5, each voltage is set to satisfy the relationship of VR <V5 <VE <V4, and the relationship of (V4-V5) <(VE-VR) is satisfied. . Then, (V4−V5) <(VE−VR)
By setting the read voltage V5 such that the following relationship is established, it is possible to prevent the time required for read from becoming longer as the read voltage V5 approaches the read voltage VR. Memory cell 6a
Is written to the same word line 5 as the memory cell 6a.
a is connected to the monitor memory cells 1a, 1c, 1
-11 V is also applied to the control gate of x. After the write verify of the memory cell 6a, the monitor memory cells 1a, 1c, 1x are read at the read voltage V5.

When the VTH of at least one of the monitor memory cells 1a, 1c, and 1x shifts by (V4−V5) or more, the read value of the monitor memory cell becomes an inverted value from the expected value. In a situation where writing to the memory cell 6a causes gate disturb to occur in other memory cells, it is considered that gate disturb also occurs in the monitoring memory cells 1a, 1c, and 1x. If the memory VTH of at least one of the monitoring memory cells 1a, 1c, 1x is shifted by (V4-V5) or more, the monitoring memory cells 1a, 1c, 1x are shifted.
In contrast, when reading is performed at the reading voltage V5, the read value becomes a value inverted from the expected value.

Therefore, in the second embodiment, since a plurality of monitor memory cells are connected in parallel to the same word line, the state of extraction of electrons from the floating gate in each monitor memory cell depends on the monitor state. As a result of amplification according to the number of memory cells connected in parallel, there is an effect that a flash memory capable of increasing the detection sensitivity of gate disturb can be obtained. In addition, by connecting the monitor memory cells in parallel, it is possible to suppress a decrease in the gate disturb detection accuracy due to variations in characteristics occurring in the monitor memory cells. The effect is obtained.

Embodiment 3 FIG. 5 is a circuit diagram showing a configuration of a part of the flash memory according to the third embodiment of the present invention. 5, parts that are the same as or correspond to those in FIG. 1 are given the same reference numerals, and descriptions thereof are omitted. In the figure, 5c is a word line connected to the monitor memory cell 1a, 5d is a word line connected to the monitor memory cell 1d, and 5e and 5f are connected to a read voltage generation circuit (not shown) of the monitor memory cell. Word line, 4a is word line 5
a and an N-channel transistor (first switch) 4b provided between the word line 5c and the word line 5c.
d, an N-channel transistor (first switch) provided between word lines 5c and 5e, and a P-channel transistor (second switch) provided between word lines 5e and 5e.
Is a P-channel transistor (second switch) provided between word line 5d and word line 5f, 10 is a control signal line connected to the gates of N-channel transistors 4a and 4b, and 11 is N-channel transistors 4a and 4b And a control signal line 12 connected to the gates of the P-channel transistors 4c and 4d.

FIG. 6 shows N-channel transistors 4a and 4
It is sectional drawing of b. 6, the same or corresponding parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.
In the figure, 13 is a source line connected to the word line 5a, 14 is a drain line, 15 is a P base, 16a is an N-well provided on the P base 15, 17a is an N-well 1
5 is a P-well. P board 15 is 0
The V, N-well 16a is floating.

Next, the operation will be described. Memory cell 6
When writing to a, -11 V is applied to the word line 5a. At this time, the N-channel transistor 4a applies -11V to the control voltage line 11 and 0V to the control signal line 10. Since the source line 13 is connected to the word line 5a, -11V is applied. As a result, the N-channel transistor 4a is turned on, and -11 V is supplied to the control gate of the monitoring memory cell 1a. The N-channel transistor 4b is also turned on at the same time, but since 0V is applied to the word line 5b, the word line voltage of the monitoring memory cell 1b also becomes 0V. On the other hand, the P-channel transistors 4c and 4d set the control signal line 12 to the same voltage as the monitor memory cell read voltage. As a result, the P-channel transistors 4c and 4d are turned off, and the voltage of the word line 5a is prevented from flowing back to the read voltage generation circuit.

When performing the write verify of the memory cell 6a, a write verify voltage is applied to the word line 5a.
Here, the write verify voltage is set to 2 V for convenience. At this time, the N-channel transistor 4a is connected to the control voltage line 1
1 is set to 0V, and the control signal line 10 is set to 0V. This gives N
The channel transistor 4a is turned off, and the monitoring memory cell 1a is separated from the word line 5a. The P-channel transistor 4c is turned on by applying 0 V to the control signal line 12, and the monitoring memory cell 1
The monitoring memory cell read voltage is applied to the word line 5c from the read voltage generation circuit.

As a result, in the third embodiment, the memory cell 6
a and the monitor memory cell 1a can be simultaneously applied with different voltages, the write verify of the memory cell 6a and the read of the monitor memory cell 1a can be performed simultaneously, and the time required for gate disturb detection can be reduced. There is an effect that a flash memory can be obtained.

[0026]

As described above, according to the first aspect of the present invention, a monitor memory cell having a control gate connected to a word line of a memory cell array and a monitor connected to a drain of the monitor memory cell. , And by reading the contents of the monitor memory cell connected to the word line of the written memory cell, the shift of the memory threshold voltage due to gate disturb can be performed. The gate disturb does not need to be inspected for all the memories connected to the word line each time writing is performed, and the gate disturb detection time can be shortened.

According to the second aspect of the present invention, the control gate is connected to the control gate of the memory cell by the word line, and the initial memory threshold voltage is lower than the erase verify voltage and the second threshold voltage. The data is controlled within a voltage range between a lower first threshold voltage and, after writing data to the memory cell array, the content is read at a monitor cell read voltage higher than the read voltage for the memory cell and lower than the first threshold voltage. Since the monitor memory cell is provided, when a gate disturbance occurs due to data writing to the memory cell array, the memory threshold voltage of the monitor memory cell shifts and is read by the monitor cell read voltage. Since the contents are inverted, the shift of the memory threshold voltage due to gate disturb is monitored in the monitor. Use may be detected by the memory cell, it is not necessary to inspect the gate disturbance of all memory connected to a word line for each write,
This has the effect of shortening the gate disturb detection time.

According to the third aspect of the present invention, since each control gate is provided with a plurality of monitor memory cells connected in parallel by word lines to the control gates of the memory cells of the memory cell array, The state in which electrons are extracted from the floating gate in the monitor memory cell is amplified in accordance with the number of monitor memory cells connected in parallel. As a result, the gate disturb detection sensitivity can be increased, and the word line can be written every writing. It is not necessary to perform a gate disturb inspection for all memories connected to the memory, and the effect of reducing the gate disturb detection time can be obtained.

According to the fourth aspect of the present invention, the initial state is the erased state, the memory threshold voltage at the time of erasing is equal to or higher than the erase verify voltage and equal to or lower than the fourth threshold voltage, and after writing data to the memory cell array, A plurality of monitor memory cells whose contents are read at a monitor cell read voltage between the erase verify voltage and a read voltage of a memory cell, each control gate being connected in parallel to a word line; Since it is configured to have a monitoring bit line connected to the drain of the cell, the state of extraction of electrons from the floating gate in the monitoring memory cell is amplified according to the number of monitoring memory cells connected in parallel, When the memory threshold voltage of at least one of the monitor memory cells falls below the monitor cell read voltage, Since the value read from the memory cell for the monitor becomes an inverted value from the expected value, the detection sensitivity of the gate disturb can be increased, and furthermore, the detection accuracy of the gate disturb due to the variation in the characteristics of the monitor memory cell is reduced. In addition, it is not necessary to perform a gate disturb inspection for all the memories connected to the word line for each writing, and the gate disturb detection time can be shortened.

According to the fifth aspect of the present invention, the conductive state and the non-conductive state are controlled to perform erase verify of the monitor memory cell simultaneously with write verify to the memory cell of the memory cell array. A first switch connected to a word line between control gates of the monitor memory cell, and a second switch connected between a control gate of the monitor memory cell and an erase verify voltage input terminal. Because we configured
The write verify of the memory cell and the read of the monitor memory cell can be performed at the same time, and the time required for gate disturb detection can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a part of a flash memory according to a first embodiment of the present invention;

FIG. 2 is an explanatory diagram showing a management range of a memory threshold voltage of a memory cell of a flash memory and a monitoring memory cell according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of a part of a flash memory according to a second embodiment of the present invention;

FIG. 4 is an explanatory diagram showing a management range of a memory threshold voltage of a memory cell of a flash memory and a memory cell for monitoring according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram showing a configuration of a part of a flash memory according to a third embodiment of the present invention;

FIG. 6 is a sectional view of an N-channel transistor of a flash memory according to a third embodiment of the present invention;

FIG. 7 is a circuit diagram showing a configuration of a part of a conventional flash memory.

FIG. 8 is a sectional structural view of a memory cell of a conventional flash memory.

[Explanation of symbols]

1a, 1b, 1c, 1d, 1x, 1y Monitor memory cell, 2 Monitor bit line, 4a, 4b N-channel transistor (first switch), 4c, 4d P-channel transistor (second switch), 5a, 5b , 5
c, 5d Word lines, 6a to 6n, 7a to 7n memory cells, 8a, 8b, 8n bit lines, 9 memory cell arrays.

Claims (5)

[Claims] 1. A flash memory comprising: a monitor memory cell in which a control gate is connected to a word line of a memory cell array; and a monitor bit line connected to a drain of the monitor memory cell. 2. A memory cell array comprising a plurality of memory cells having a memory threshold voltage at the time of erasing equal to or higher than an erase verify voltage, a word line connecting a control gate of the memory cell and a control gate of a monitoring memory cell, A bit line connected to the drain of the memory cell, a control gate connected to the control gate of the memory cell by a word line, and an initial memory threshold voltage lower than the erase verify voltage; The monitor cell read is controlled within a voltage range between the first threshold voltage lower than the second threshold voltage and the write voltage to the memory cell array, and after the data write to the memory cell array, is equal to or higher than the read voltage for the memory cell and lower than the first threshold voltage. 2. A flash memory according to claim 1, further comprising: a monitor memory cell whose contents are read by a voltage. Shmemera. 3. The flash according to claim 1, wherein each of the control gates includes a plurality of monitor memory cells connected in parallel by word lines to control gates of the memory cells of the memory cell array. memory. 4. A memory cell array comprising a plurality of memory cells having a memory threshold voltage at the time of erasing between an erase verify voltage and a fourth threshold voltage higher than the erase verify voltage, and connected to a control gate of the memory cell. A word line, a bit line connected to a drain of the memory cell, an initial state is an erased state, a memory threshold voltage at the time of erasing is equal to or higher than the erase verify voltage and equal to or lower than the fourth threshold voltage, After the data is written to the cell array, the contents are read at a monitor cell read voltage between the erase verify voltage and the read voltage of the memory cell. A plurality of monitor gates each having a control gate connected in parallel to the word line are provided. A memory cell, and a monitor bit line connected to drains of the plurality of monitor memory cells. Flash memory according to claim 3, wherein a. 5. A control gate of the memory cell and the monitor memory cell, wherein a conduction state and a non-conduction state are controlled to perform erase verification of the monitor memory cell at the same time as write verification to the memory cell of the memory cell array. 3. The semiconductor device according to claim 2, further comprising a first switch connected to an intervening word line, and a second switch connected between a control gate of the monitor memory cell and an erase verify voltage input terminal. The flash memory according to claim 4.