JP2812202B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a read only memory (ROM) in which data is stored in a nonvolatile manner by a mask program or the like.

[0002]

2. Description of the Related Art Conventionally, NOR type memory cells shown in FIG. Each memory transistor may be in a normal enhancement state (E-type) or by selective channel ion implantation, for example.
It is set to a high threshold state (HiVt state) that does not turn on even at the power supply voltage. This is data writing. When the selected word line is driven, if the memory transistor connected to the selected word line is of the E type, current flows through the bit line, and if the memory transistor is in the HiVt state, no current flows through the bit line. Thus, data can be read.

In the NOR type memory cell configuration shown in FIG. 3, it is necessary to connect the source and drain of each memory transistor to a ground line and a bit line, respectively, and the number of contacts is large, which hinders an improvement in integration. . On the other hand, a NAND memory cell shown in FIG. 4 is known as a memory cell configuration advantageous for improving the degree of integration.

In the NAND type memory cell shown in FIG. 4, a memory transistor is set to either an E type or a depletion type (D type) to write data. Data read is performed by applying a read voltage to a selected word line and detecting whether a current flows through a bit line.
At this time, a high level voltage is applied to the unselected word lines,
Keep unselected memory transistors conductive. This N
In the AND type memory cell, only one bit line contact and one ground line contact are required for a plurality of memory transistors, which is advantageous for higher integration than the NOR type memory cell.

However, in the NAND memory cell configuration,
To read data from one memory transistor, a current must be passed through the channel of another memory transistor in the NAND cell as described above. For this reason, it is substantially equivalent to a state where the channel length of the memory transistor is extremely long, and it is difficult to obtain high-speed performance.

[0006]

As described above, the conventional ROM memory cell configuration has a problem that it is difficult to achieve both high integration and high-speed performance.
The present invention has been made in view of the above points, and has as its object to provide a ROM that can achieve both high integration and high-speed performance.

[0007]

A ROM according to the present invention
The first and second memory transistors driven by one word line form a pair, one end of which is connected to one bit line, and a bias circuit is connected to the other end of the first memory transistor. The other end of the second memory transistor is set to a reference potential to form a memory cell array, and the first and second memory transistors are each set to one of two threshold states to store data in a nonvolatile manner. Writing is performed, and by selecting the word line, a quaternary output is obtained on the bit line corresponding to four combinations of threshold states of the first and second memory transistors. Features.

[0008]

According to the present invention, two memory transistors driven by one word line are paired so that a quaternary output can be obtained on one bit line. Conventional N
Even in the OR type memory cell configuration, when two memory transistors selected by one word line are viewed as a pair, there are four combinations of their data states. However, in this case, the data of the two memory transistors are read to bit lines different from each other. That is, in the case of the present invention, the number of bit lines can be reduced to １ ／ compared with the conventional NOR type memory cell configuration. Further, since the two memory transistors may be completely different, a TFT or SOI
A two-story structure such as a system can be realized, in which case the memory area can be reduced to half. Also, in the present invention, N
Since a plurality of memory transistors are not connected in series to one bit line unlike the AND type memory cell configuration, the same high-speed performance as that of the normal NOR type memory cell configuration can be realized.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a mask R according to an embodiment of the present invention.
The main configuration of the OM is shown. The memory cell 1 includes a word line WLi and a bit line BLj arranged crossing each other, and an n-channel memory MOS arranged at the crossing position between the word line WLi and the bit line BLj.
It is composed of a transistor Mij. Focusing on one bit line BL1 and one word line WL1, a description will be given.
The two memory transistors M11 and M12 driven by the word line WL1 form a pair and constitute one memory cell MC.

One end of each of the first memory transistor M11 and the second memory transistor M12 forming the memory cell MC is connected to the same bit line BL1. The other end of the first memory transistor M11 is connected to a Vp line to which a predetermined bias is given by the bias circuit 2, and the other end of the second memory transistor M12 is connected to a VSS line which is a reference potential line. The bias circuit 2 has a gate
It comprises a p-channel MOS transistor QP1 having a drain connected to the Vp line and a source connected to VDD, and an n-channel MOS transistor QN1.

The bit line BL2 adjacent to the bit line BL1
Similarly, the detailed description is omitted, but in the case of this embodiment, as shown in the figure, the portion on the BL1 side and the portion on the BL2 side are laid out in an inverted pattern with the VSS line interposed therebetween. This enables a two-story structure of the memory transistor. These bit lines BL1, BL
Reference numeral 2 in this embodiment is connected to a sense amplifier 4 via a column selector 3 comprising n-channel MOS transistors QN3 and QN4.

The sense amplifier 4 includes an inverter I for detecting a potential change of the bit line BL, an n-channel MOS transistor QN5 whose source and gate are controlled by the input and output of the inverter I, and whose drain is connected to the output terminal OUT. And a p-channel MOS transistor QP2 for a current source. A current source 5 including an n-channel MOS transistor QN2 is provided at an end of the bit line BL opposite to the sense amplifier 4. MOS transistor QN2 has a common drain / gate bit line B
L and the source is connected to the VSS line. As a result, an increase in the potential of the bit line is suppressed.

Data writing to the memory cell array 1 is performed as follows.
For example, by selective channel ion implantation. Focusing on one memory transistor, it is set to either an E-type state or a high-threshold HiVt state that does not turn on even at the power supply voltage, as in a normal NOR-type memory cell. At this time, focusing on one memory cell MC including two memory transistors forming a pair, there are four combinations of data states. In this embodiment, the voltage levels are different according to the four data states.
A value output is obtained on the bit line BL.

The operation of reading quaternary data will be described with reference to FIG. At the time of data reading, VDD is applied to the selected word line, for example. FIG.
Shows the relationship between the four data states of the memory cell MC and the output read out to the sense amplifier 4 according to each data state. First, when the first and second memory transistors M11 and M12 are in the HiVt data state, both the memory transistors M11 and M12 are off even when the word line WL1 is selected. At this time, the bit line BL1 is at an intermediate level determined by the current drawn by the current source 5. This is amplified by the sense amplifier 4, and an output indicated by the voltage level V2 is obtained at the output terminal OUT.

Next, the first memory transistor M11 is
When the word line WL1 is selected when the second memory transistor M12 is in the HiVt state, the first memory transistor M12 is in the first state.
Is turned on, and the second memory transistor M12 is turned off. Therefore, a current is supplied from the bias circuit 2 to the bit line BL1 via the first memory transistor M11, and this is added to the current from the current source 5 to raise the potential of the bit line BL1. This bit line potential rise is detected by sense amplifier 4 and output terminal OU
At T, a higher level V2 output is obtained compared to the data state.

Next, in a data state where both the first and second memory transistors M11 and M12 are in the E state, when the word line WL1 is selected, these memory transistors M11 and M12 are simultaneously turned on. As a result, a current is supplied from the bias circuit 2 to the bit line BL1 via the first memory transistor M11, and at the same time, the second memory transistor M12 supplies a current from the bit line BL1 to VSS.
Current is drawn into the At this time, if the circuit conditions are designed in advance so that the latter current drawn into VSS becomes larger than the supply current, the potential of the bit line BL1 becomes lower than in the data state. This is detected by the sense amplifier 4, and an output of a level V3 lower than the data state is obtained at the output terminal OUT.

Finally, the first memory transistor M11 is
When the word line WL1 is selected in the HiVt state and the data state of the second memory transistor M12 in the E state, only the second memory transistor M12 is turned on. As a result, the potential of the bit line BL1 becomes lower than that in the data state. The sense amplifier 4 detects this and outputs the output terminal OU
At T, an output of level V4 lower than the data state is obtained.

As described above, according to this embodiment, two memory transistors are paired, and a quaternary output can be obtained on one bit line by a combination of the two threshold states. The quaternary output is passed through, for example, an A / D converter, so that "11", "10", "01", "0
0 ". In the case of a normal NOR type memory cell, a binary output is required. To obtain a data amount corresponding to the quaternary output of this embodiment, two bits are required. Lines are needed, so according to this embodiment,
The number of bit lines can be reduced when the storage capacity is the same as in a normal NOR memory cell configuration. Further, since the two memory transistors are not formed in the same manufacturing process, for example, one may be a TFT, a two-story structure in which transistors are provided above and below a word line can be used. It can be. N
Since the channel of the non-selected memory cell is not used for data reading unlike the AND memory cell, high-speed operation similar to the NOR memory cell configuration is possible.

[0019]

As described above, according to the present invention, it is possible to provide a ROM capable of achieving both high integration and high speed by enabling quaternary data to be output to one bit line by a pair of memory transistors. be able to.

[Brief description of the drawings]

FIG. 1 shows a main configuration of a mask ROM according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment.

FIG. 3 shows a NOR type memory cell configuration.

FIG. 4 shows a NAND memory cell configuration.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Bias circuit, 3 ... Column selector, 4 ... Sense amplifier, 5 ... Current source, M11 ... First
, A memory transistor M12, a second memory transistor, and MC, a memory cell.

Claims (1)

(57) [Claims] A first memory transistor driven by one word line is paired with one end connected to one bit line, and a bias circuit is connected to the other end of the first memory transistor. And the other end of the second memory transistor is set to a reference potential to form a memory cell array. The first and second memory transistors are each set to one of two threshold states. Data is written in a non-volatile manner, and the first word line is selected and the first bit line is written to the bit line.
And a quaternary output corresponding to four combinations of each threshold state of the second memory transistor.