JPH04195455A - System abnormality reporting system - Google Patents

Abstract

PURPOSE:To simplify processing procedures by reporting the occurrence of abnormality of one CPU to another CPU through a signal line by the signal which is outputted from a timer by expiration of a timer which monitors the occurrence of abnormality of one CPU. CONSTITUTION:When expiring, a watchdog timer 13 outputs an interrupt signal to a CPU 11 and a CPU 21 through signal lines 14 and 18 to inform them of the occurrence of abnormality. The CPU 11 receives the interrupt signal from the watchdog timer 13 to recognize the occurrence of abnormality and performs the processing corresponding to the abnormality to report the occurrence of abnormality to an external device through an external interface circuit 15 or to reset a related device. The CPU 21 receives the interrupt signal from the watchdog timer 13 to recognize the occurrence of abnormality on the side of the CPU 11. Thus, the countermeasure of the CPU 11 related to the report of abnormality is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system abnormality notification method for a system using a CPU.

[Conventional technology] CPU (Central Processing)
Unit), CPL' is R
A common method is to execute software stored in a memory such as OM or RAM. When the CPU executes software, if there is a flaw in the software or a failure occurs in the hardware, the system may not operate normally, such as the CPU going out of control or waiting for a condition to occur. There are cases where it stops happening. As a method for detecting such system abnormalities, a method using a timer called a watchdog timer is used.

FIG. 2 shows a configuration diagram of a system using a watchdog timer.

The watchdog timer 3 is set and operated so as to time out at a fixed period (referred to as t). CPU 1 executes software stored in memory 2 . The software stored in the memory 2 is designed to reset the watchdog timer 3 at a cycle shorter than CPU I or t.

If the system is operating normally, CPU1
Since watchdog timer 3 is reset at a shorter cycle than If an abnormality occurs such as the device remaining in a waiting state, the watchdog timer 3 will not be reset by the CPU, so the watchdog timer 3 will time out. Then, the watchdog timer 3 interrupts and notifies the CPU 1 of the occurrence of timeout via the signal line 4. The CPU 1 recognizes an abnormality in the system based on the interrupt notification from the watchdog timer 3, and takes measures to deal with the abnormality, such as notifying external equipment of the system abnormality or resetting related devices through the external interface circuit 5. Process.

By the way, as a system configuration method using a CPU,
There is a multi-CPU method that uses multiple CPUs. The multi-CPU system aims to speed up processing and improve performance by having each CPU operate in cooperation with each other.

FIG. 3 shows an example of a system configuration when two CPUs are used.

The two CPLs 11 and 21 (CPUI, CPU2) are each equipped with a watchdog timer to monitor abnormalities in their respective operations. For example, CPUII
If there is an abnormality in the operation, the watchdog timer 13 times out and notifies the CPU II of an interrupt via the signal line 14. The CPU recognizes a system abnormality based on an interrupt notification from the watchdog timer 13, and performs processing to respond to the abnormality, such as notifying external equipment of the system abnormality or resetting related devices through the external interface circuit 15. Do this.

Furthermore, since the CPU II and the CPU 21 perform processing in cooperation, it may be necessary to notify the other of an abnormality in one.

When an abnormality occurs on the CPU II side, abnormality notification to the CPU 21 is performed, for example, as follows. CPU1l starts CPUIII by notification from watchdog timer 13.
When recognizing an abnormality in the FI, the CPU II writes data indicating that an abnormality has occurred on the CPU II side into the memory 22 through the interface circuit 30.

The CPU 21 periodically refers to the area of the memory 22 where the CPU II notifies the occurrence of an abnormality, and recognizes the occurrence of an abnormality on the CPU II side. Or, CPUII is
When an abnormality on the I side is recognized, the interface circuit 30
is used to connect the CPU 21 to the CPU 21 through the signal line 27.
1g! ! It is also possible to interrupt notification of an abnormality.

Above, we have described an example where an abnormality occurs in the CPU 11m, but if an abnormality occurs in the CPU 21 (FI), the above C
This is a process in which the PU11 and CPU21 are reversed.

"Question B to be solved by the invention" As mentioned above, in a conventional multi-CPU system, when notifying other CPUs that an abnormality has occurred in the operation of one CPU, the CPU that detected the abnormality The CPU notifies the abnormality via the memory or generates an interrupt signal to notify other CPUs of the abnormality.

However, with the method of notifying abnormalities via memory,
In the processing of each CPU, it is necessary to define a procedure for abnormality notification, which makes the processing complicated. Furthermore, each CPU needs to periodically refer to the memory, resulting in an increase in processing overhead.

In addition, in both the notification method via memory and the notification method using an interrupt signal, a CPU that does not detect an abnormality can
It is necessary to notify U of an abnormality, so if there is an abnormality in the CPU itself, it will be sent not only to other CPUs, but also to
There was a problem in that it was no longer possible to notify the outside of an abnormality.

SUMMARY OF THE INVENTION An object of the present invention is to provide a system abnormality notification method that eliminates the drawbacks of the prior art in the multi-CPU system described above, has a simple processing procedure, and is highly illuminating.

[Means for Solving the Problems] The system abnormality notification method of the present invention detects the occurrence of an abnormality in one CPU in a system that includes a plurality of CPUs and uses a timer to detect an abnormality in the operation of each CPU.
A signal is output from the timer when the timer that monitors the occurrence of an abnormality in the PU times out.
This is to notify other CPUs.

In a system equipped with two CPUs and using a timer to detect abnormality in the operation of each CPU, one CPU
The occurrence of an abnormality is notified to the other CPU via a signal line by a signal output from the timer when the timer for monitoring the occurrence of an abnormality in that CPU times out.

[Operation] In a multi-CPU system, this is a method in which the interrupt output signal of the watchdog timer for monitoring abnormal operation of one CPU is input to other CPUs via a signal line, and the interrupt output signal is input to other CPUs via the memory or interrupts. The processing procedure for abnormality notifications is simple, and the CPU
Even if an abnormality occurs in itself, it is possible to notify other CPUs of the abnormality. Therefore, a highly reliable system abnormality notification method is provided.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of the abnormality notification system of the present invention.

CPU II and CPU 21 are connected to system bus 1, respectively.
6, 26, memory 12, 22, watchdog timer 13, 23, external interface circuit 15, 25
, and connected to the interface circuit 30. From the watchdog timer 13, CPUI 1 and CPU
Signal line 14 for notifying system abnormality to 21
．． 18 is provided, and signal lines 24 and 28 are provided from the watchdog timer 23 to notify the CPU 21 and CPU II of a system abnormality. The watchdog timers 13 and 23 are set to time out at fixed intervals (ti and t2), respectively, and the 6 CPU II and CPU 21 that are operated execute software stored in the memories 12 and 22, respectively.

The software stored in the memory 12 is
The watchdog timer 13 is set to be reset at a cycle shorter than tl, and the software stored in the memory 22 is set so that the CPU 21 resets the watchdog timer 23 at a cycle shorter than t2.

If the system is operating normally, the CPU 11
The watchdog timer 13 is reset at a cycle shorter than tl, and the CPU 21 resets the watchdog timer 23 to t2.
Since the watchdog timers 13 and 23 are reset in a shorter cycle, they do not time out.

Due to software deficiencies or hardware failures, C.
If an abnormality occurs such as the PU going out of control or waiting for a condition to occur, the CP on the side where the abnormality occurred
The watchdog timer times out because U no longer resets the watchdog timer.

Let us take as an example a case where the watchdog timer 13 times out.

When the watchdog timer 13 times out, the CPU 11 and CPU 2
1 and outputs an interrupt signal to notify the occurrence of an abnormality. C
The PUI 1 recognizes the occurrence of an abnormality by receiving an interrupt signal from the watchdog timer 13, and responds to the abnormality by notifying external equipment of the occurrence of the abnormality through the external interface circuit 15 and resetting related equipment. Process.

On the other hand, by receiving the interrupt signal from the watchdog timer 13, the CPU 21 can also recognize that an abnormality has occurred on the CPU 1l side. Here the CPU
21 is based on the CPU II side, taking into account that the watchdog timer 13 may time out due to an abnormality occurring in the CPU II itself (in this case, the CPU II may not notify the external device of the abnormality occurrence). The occurrence of an abnormality may be notified to external equipment through the external interface circuit 25.

In the above embodiment, an example is shown in which there are two CPUs, but the number of CPUs is not limited to two, and the abnormality notification method of the present invention can also be applied to a multi-CPU system configured with two or more CPUs. It is possible. If there are two or more CPUs, for example, one watchdog timer is provided for each CPU, and a signal line (1
8, 28, etc.).

[Effects of the Invention] As described above, according to the abnormality notification method of the present invention, when an abnormality occurs, other CPUs are notified of the abnormality by the interrupt output of the watchdog timer. Compared to a system in which an abnormality is notified through the system or by generating an interrupt, the processing by the CPU regarding the abnormality notification becomes simpler.

In addition, in the method using memory, the CPU needs to periodically refer to the memory, but according to the abnormality notification method of the present invention, the CPU does not need to refer to the memory regularly, and there is a corresponding processing overhead. can be reduced.

Furthermore, in the abnormality notification of the present invention, the abnormality is notified to other CPUs by the interrupt output of the watchdog timer, so even if an abnormality occurs in the CPU itself, the abnormality notification is sent to other CPUs. If a CPU that does not receive an abnormality notification notifies the outside that an abnormality has occurred in another CPU, it becomes possible to notify the outside of the abnormality.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of an abnormality notification method according to the present invention, Fig. 2 is a block diagram showing an example of an abnormality notification method using a watchdog timer, and Fig. 3 is a block diagram showing an example of an abnormality notification method using a watchdog timer. FIG. 2 is a configuration diagram showing an example of an abnormality notification method using. In the figure, 1, 11, 21 are CPUs, 2, 12, 22 are memory, 3, 13, 23 are watchdog timers, 4, 14
．． 18, 24.28 are signal lines, 5.15.25 are external interface circuits, 6.16.26 are system buses, 3
0 indicates an interface circuit. Patent Applicant Hitachi Cable Co., Ltd. Representative Patent Attorney Nobuo Kinutani Figure 1

Claims (1)

[Claims] 1. In a system including a plurality of CPUs and using a timer to detect an abnormality in the operation of each CPU, one CPU
A system abnormality notification method characterized in that the occurrence of an abnormality in U is notified to other CPUs via a signal line by a signal output from a timer when a timer for monitoring abnormality occurrence in that CPU times out. 2. In a system equipped with two CPUs and using a timer to detect abnormality in the operation of each CPU, one CPU
A system abnormality notification method characterized in that the occurrence of an abnormality in U is notified to the other CPU via a signal line by a signal output from a timer when a timer for monitoring abnormality occurrence in that CPU times out.