JPH04195241A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by controlling the operation of a data bus buffer amplifier with the signal of a control signal line. CONSTITUTION:A microcomputer 4 outputs the signal which selects an extending function circuit 17 to an address bus 5 and the date signal to a data bus 7 respectively. An address decoder 16 outputs a decoding signal D1 with a selection signal and sends the signal D1 to a date bus buffer amplifier control circuit 13 via the decoding signal lines 18 and 19 and an extension bus 2. Then the decoder 16 outputs an operation control signal E0 in order to make a buffer amplifier 11 output the data signal to a bus 8 from the bus 7. In the same way, a data bus buffer amplifier 12 outputs a data signal to a date bus 10 from a date bus 9 with the signal that selects the circuit 17. The circuit 17 fetches the date signal from the bus 10. When an extending function device 3 is changed to another extension device, the decoder 16 recognizes the address given from the microcomputer 4 as an address given to its own device and produces the signal D1 to the line 18. At the side of a CPU 1, the signal D1 can be fetched by the line 19. As a result, the hardware quantity can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to information processing devices, and more particularly to an interface system for an extended function device between a central processing unit and an extended function device.

Prior Art The conventional expansion bus interface system ζ will be explained with reference to FIG. The central processing unit 1 is connected to an expansion function device 3 via an expansion bus 2.

The central processing unit 1 includes a microcomputer 4 connected to an address node 5 and a data node, and a data bus buffer that electrically connects data buses 7 and 8 in response to input of an operation control signal Eo. amplifier 11 and address bus 5
The data bus buffer amplifier control circuit 13 has an address decode circuit 15 connected to the address decode circuit 15 which decodes an address and outputs an address decode signal Do, and a data bus buffer amplifier control circuit 13 which inputs the decode signal DO and generates an operation control signal Eo.

The expansion bus 2 is connected to an address bus 6 and a data bus 9 for outputting an address 5 and a data bus 8 output from the central processing unit 1 to the expansion function device 3, respectively.

The extended function device 3 includes a data bus buffer amplifier 12 that electrically connects data buses 9 and 10 in response to an operation control signal E1, and a data bus buffer amplifier 12 that is connected to an address bus 6 and outputs a decode signal D.
i, an address decode circuit 16 that outputs the decode signal Dl, a data bus buffer amplifier control circuit 14 that receives the decode signal Dl and generates the operation control signal E1, and an extended function circuit 17 that is connected to the address bus 6 and the data bus 10. have.

When sending data to the extended function circuit 17, the microcomputer 4 outputs an address signal for selecting the extended function circuit JT to the address bus 5 and a data signal to the data bus 7, respectively. The address decode circuit 15 receives an address signal for selecting the extended function circuit 17 and outputs a decode signal DO.
Pressure.

The data bus buffer amplifier control circuit 13 uses the decode signal DO
When inputted manually, it generates an operation control signal EO and controls the data signal on the data bus buffer amplifier 11 or the data bus 8 to be output to the data bus 8. Similarly, the data bus buffer amplifier 12 is controlled to output the data signal on the data bus 9 to the data bus 10 by an address signal that selects the extended function circuit 17. Extension function circuit 17
takes in the data signal on the data bus 10 by the address signal that selects itself.

The above-mentioned conventional expansion bus interface system for information processing devices has a drawback in that circuits for decoding the same address are required at two locations, one on the central processing unit side and the other on the function expansion device side.

OBJECTS OF THE INVENTION An object of the present invention is to provide an information processing device that can reduce hardware by eliminating redundancy in decoding circuits and using a single decoding circuit.

Structure of the Invention An information processing device according to the present invention includes a central processing unit, an extended function device, an address bus that sends out an address for accessing the extended function device, and a connection between the central processing unit and the expanded function device. an expansion bus consisting of a data bus for transmitting and receiving data; a data bus buffer amplifier provided in each of the central processing unit and the expansion function device for transmitting and receiving data to and from the data bus; control means for generating a control signal for controlling the operation of a buffer amplifier of the device in response to generation of the address from the central processing unit; and the extension for sending the control signal to the central processing unit. and a control signal line included in the bus, and the central processing unit receives control signals from the control signal line to control the operation of its own data bus buffer amplifier.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals. The central processing unit 1 is connected to an expansion function device 3 via an expansion bus 2. The central processing unit 1 includes a microcomputer 4 connected to an address bus 5 and a data bus 7, and a data bus buffer amplifier 11 that uses an operation control signal EO as an activation control input and electrically connects the data buses 7 and 8. , and a data bus buffer amplifier control circuit 13 connected to the decode signal line 19 and outputting an operation control signal EO.

The expansion bus 2 connects the address signal RA output from the central processing unit 1 and the data bus 8 to the address bus 6 and data bus 9 of the three expansion function devices, respectively.
connects the decode signal line 18 output from the extended function device 3 to the decode signal line 19 on the central processing unit 1 side.

The extended function device 3 includes a data bus buffer amplifier 12 that uses the operation control signal El as a starting input and electrically connects the data buses 9 and 10, and is connected to the address bus 6 and sends the decode signal D1 to the decode signal line 18 and the data bus buffer amplifier 12. Address decode circuit 16 outputting to bus buffer amplifier control circuit 14
, a data bus buffer amplifier control circuit 14 that receives a decode signal Di and generates an operation control signal E1, and an extended function circuit 17 connected to the address bus 6 and the data bus 10.

When sending data to the extended function circuit 17, the microcomputer 4 outputs an address signal for selecting the extended function circuit 17 to the address bus 5 and a data signal to the data bus 7.

Address decode circuit 16 receives an address signal for selecting extended function circuit 17 and outputs decode signal DI.

The decode signal DI is connected to the decode signal line 18. Expanded lotus 2.
The signal is input to the data bus buffer amplifier control circuit 13 via one decode signal line.

The data bus buffer amplifier control circuit 13 receives the decoded signal Di.
When inputted manually, it generates and outputs an operation control signal EO, and controls the data bus buffer amplifier 11 or the data signal on the data bus 7 to be output to the data bus 8.

Similarly, the data bus buffer amplifier 12 is connected to the extended function circuit 17.
The data signal on the data bus 9 is controlled to be output to the data bus 10 by the address signal that selects the data bus 9 .

The extended function circuit 17 takes in the data signal on the data bus 10 by the address signal selected by itself.

When extended function device 3 is changed to another extended function device,
The address from the microcomputer 4 naturally generates an address for accessing the expanded function circuit (17) in this changed expanded function device, or the address decode circuit (16) in the expanded function device automatically generates an address in this case as well. Recognizing that it is an address for the device, connect the decode signal line (
18), an address decode signal Di is generated. Therefore, on the central processing unit 1 side, this signal DI can be taken in as the decode signal 19 via the expansion bus 2.

In this embodiment, the address decode (g+) is sent and received via the extension lot 2 and the decode signal lines 18 and 19, but the operation control signal El is used instead of the address decode signal Di. It may also be sent to the central processing unit 1 via the expansion lotus 2. In this case, the central processing unit 1
It is also possible to omit the data bus buffer amplifier control circuit 13 inside.

Effects of the Invention As described above, according to the present invention, a signal for starting control of the data bus buffer amplifier on the extended function device side is used as a signal for starting control of the data bus buffer amplifier on the central processing unit side. Since the expansion bus interface is configured in this manner, the hardware on the central processing unit side can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional expansion bus interface section. Explanation of symbols of main parts 1...Central processing unit 2...Expansion bus 3...Extension function device 5.6...Address bus 7.8, 9.10...・Data bus 11.12...
...Data bus buffer amplifier 13.14...Data bus buffer amplifier control circuit

Claims (2)

[Claims] (1) A central processing unit, an extended function device, an address bus that sends an address for accessing the extended function device, and data for exchanging data between the central processing unit and the expanded function device. an expansion bus consisting of a bus; a data bus buffer amplifier provided in each of the central processing unit and the expansion function device for transmitting and receiving data to and from the data bus; a control means for generating a control signal for controlling the operation of a buffer amplifier of its own device in response to the generation of the address; a control signal line included in the expansion bus for sending the control signal to the central processing unit; An information processing device, characterized in that the central processing unit controls the operation of a data bus buffer amplifier of the device itself in response to a control signal on the control signal line. (2) The control means includes an address decode circuit that decodes the address, and a data bus buffer amplifier control circuit that generates a start signal for a data bus buffer amplifier of the own device in response to the address decode output, 2. The information processing apparatus according to claim 1, wherein the control signal line is configured to send out the address decode signal.