JPH04370863A - Information processor - Google Patents

Abstract

PURPOSE:To set the control circuits at the optional positions separate from each other by connecting a storage part, a file control part, an I/O control part, etc., to a central processing unit(CPU) by a serial interface signal line via a serial interface control part. CONSTITUTION:A CPU 1 is connected to a storage part 4, a file control part 5, and an I/O control part 8 by a serial interface signal line 3 via a serial interface control part 2. Then the CPU 1 fetches a program instruction from the part 4 and carries out the input/output of data to an I/O controller part 8 as well as the read/write operations of data based on the program instruction. The line 3 consists of the signals lines 10 and 11 which are connected to an interface function converter 14 via the EIA232C interface drivers/receivers 12 and 13 and then to the CPU 1, the part 4, etc., via a BUS interface 9.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus comprising control circuits such as a central processing circuit (CPU), a storage section, a file control section, and an I/O control section.

0002

[Prior Art] In a conventional information processing device of this type, as shown in FIG.
As shown in the figure, a central processing circuit 1 that executes central processing;
Each control circuit is a storage unit 4, a file control unit 5, and an I/O
The control unit 8 is connected to a bus interface that transmits an address signal 19, a data signal 20, and a control signal 21, respectively.
Data input/output (read/write) or control signal input/output is performed. The electrical signal level of this bus interface is TTL level.

Next, the operation of this conventional example will be explained. Central processing circuit 1 outputs address signal 19 and control signal 2
Activate the program fetch signal and storage read signal included in 1. The storage unit 4 reads data and outputs the data to the central processing circuit 1, which takes in the data and executes it as a program command. Data read/write is executed for the file control unit 5 using an I/O read/write signal as a control signal 21. In this bus interface control method, each signal line (
The signal timing between the address signal 19, data signal 20, and control signal 21) is determined at a certain time interval, and signal delays or timing deviations may cause malfunctions.

0004

[Problems to be Solved by the Invention] In the conventional bus interface control circuit described above, address signals, data signals,
Consists of multiple signal lines that transmit control signals.
Delays on the line that cause signal timing deviations may cause operational failures, or the electrical signal level is TTL level, which limits the interface distance, making mounting and equipment design easier. Alternatively, there is a problem in that it is not possible to create a free layout.

[0005]

[Means for Solving the Problems] An information processing device of the present invention has a serial interface signal line capable of long-distance transmission that connects each control circuit of a central processing circuit, a storage section, a file control section, and an input/output control section. Each control circuit is equipped with a serial interface control unit that converts a bus interface into a serial interface, and data exchange between each control circuit or transmission of control information is performed using serial interface data. It is characterized in that it is configured to be executed by transmission.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The central processing circuit 1 is a serial interface control section 2
are connected to a storage section 4, a file control section 5, and an I/O control section 8 via a serial interface signal line 3, respectively. In this information processing device, a central processing circuit 1 fetches program instructions from a storage unit 4, reads/writes data to the storage unit 4 based on the instructions, and reads data to a floppy disk 6 or hard disk 7 through a file control unit 5. /Write or data input/output to the I/O control section 8.

FIG. 2 is a block diagram of the serial interface control section 2. As shown in FIG. The serial interface signal line 3 consists of signal lines 10 and 11 and is connected to an EIA232C interface driver 12 and an EIA232C interface receiver 13. The interface function conversion circuit 14 receives serial interface data, analyzes the contents, and converts the data into address 15, data 16, and control signal 1, respectively.
7 signal is output to the CPU/storage unit/file control unit/I
/O Controls each circuit of the control section 18. Further, the interface function conversion circuit 14 receives the address 15 from the CPU/storage unit/file control unit/I/O control unit 18.
, data 16, and control signal 17, convert it into serial data, and send it to the EIA232C interface driver 12.
It has a function of outputting to the signal line 10 through.

FIG. 3 shows the contents of data transmitted and received on the serial interface signal line. As shown in the figure, the transmitted and received data is divided into a start signal and an end signal and has a fixed byte length (X
It consists of text data (byte length). Text data consists of ID, command, address, data, and control information. The ID indicates each ID of the CPU, storage section, file control section, and I/O control section. The commands represent various control commands, such as operation commands for fetching a program from the storage unit 4, writing data to the storage unit 4, or inputting keyboard keys from the I/O control unit 8. The address consists of 16 bytes and the data consists of 8 bytes. Control information consists of 4 bytes. These addresses, data,
The control information corresponds to the address 15, data 16, and control signal 17 in FIG. 2, and is mutually converted and functions by the interface function conversion circuit 14.

0010

[Effects of the Invention] As explained above, the present invention converts a bus interface into a serial interface capable of long-distance transmission.
Since the control circuits are separated from each other, it is possible to mount them at any position with distance between the control circuits, which has the effect of greatly simplifying mounting design and device design.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a serial interface control section in FIG. 1;

FIG. 3 is a diagram showing the contents of data on a serial interface signal line in FIG. 1;

FIG. 4 is a configuration diagram of a conventional example.

[Explanation of symbols]

1 Central processing circuit (CPU) 2 Serial interface control section 3 Serial interface signal line 4 Storage section 5 File control section 8 I/O control section 9 Bus interface

Claims (2)

[Claims] Claim 1: A serial interface signal line capable of long-distance transmission connects each control circuit of a central processing circuit, a storage section, a file control section, and an input/output control section, and a bus interface signal line is provided for each control circuit. It is characterized by being equipped with a serial interface control unit that converts a serial interface into a serial interface, and configured to exchange data between each control circuit or transmit control information through data transmission through the serial interface. information processing equipment. [Claim 2] The serial interface control unit receives serial interface data in an interface function conversion circuit, analyzes the contents, outputs address, data, and control signals respectively, and sends the data to the CPU and memory. controls each circuit of the section, file control section, and I/O control section, and receives addresses, data, and control signals from the CPU, storage section, file control section, and I/O control section, converts them into serial data, and outputs them. The information processing device according to claim 1, characterized in that the information processing device has a function.