JPH04195209A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To attain an access to a low speed peripheral equipment and at the same time to prevent the deterioration of the high speed access performance by providing a system clock timing extending means to keep the count value of a timing generating counter at a constant level for a prescribed time. CONSTITUTION:The timing generating FF 1 and 2 count the original oscillation clocks CK and have a set terminal (s) and a reset terminal (r) respectively in order to extend a period of H for system clocks S0 and S2. When the terminal (s) is set at L, the output Q is set at H. Then the output Q is set at L when the terminal. (r) is set at H. In such a period, the input of the clock CK is invalidated. The H periods of the clocks S0 and S2 are extended by the wait signals S0WAIT and S2WAIT respectively. The counters 4 and 5 are used for extension of the H periods of clocks S0 and S2 respectively. Furthermorean FF 6 controls the start/stop of the counter 4, and an FF 7 fixes the outputs of the FF 1 and 2 and also fixes the output S0 of a system clock decoder 3 in an H state.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an arithmetic processing device that can be expanded with external storage devices such as ROM and RAM as a peripheral device. Related to system clock generation circuit.

[Conventional technology]

Processing devices are desired to be faster. However, when configuring a system using an arithmetic processing unit such as a microcomputer, no matter how fast the arithmetic processing unit is used, if some of the peripheral functions are slow, the system as a whole will depend on the slowest peripheral. The speed is specified, and the high speed of the arithmetic processing device itself is wasted. On the other hand, when considering the cost of the system, there may be cases where low-speed peripheral devices must be used.

When expanding ROM and RAM, which are typical storage devices, as peripheral devices, if the ROM or RAM is slow compared to the microcomputer and processing cannot be done in time, it may be a good idea to simply slow down the system clock speed. It will be done.

Another method is to add a function to the microcomputer to stop the clock from the outside at a necessary timing, so that processing of low-speed peripheral devices can be performed during that time.

[Invention or problem to be solved]

When extending storage devices such as ROM and RAM as peripheral devices to an arithmetic processing device, typified by a microcomputer, if the speed of the peripheral device is slow, the speed of the arithmetic processing device must be reduced. However, since the timing of interaction with peripheral devices during the processing execution cycle is fixed, simply reducing the speed will not work.
Other processes are also delayed, and the high-speed performance of the arithmetic processing unit is wasted.

In addition, as a function of a microcomputer, by stopping the clock at the timing required for external peripheral device exchange, the method of processing low-speed peripheral devices during that time requires adding an external circuit that takes timing into consideration. Is it necessary? Because low-speed peripheral devices are often used due to cost considerations, adding extra external circuitry is inconsistent with cost reduction.

[Failure to solve the problem]

The arithmetic processing device of the present invention is an arithmetic processing device that can be expanded with an external storage device as a peripheral device.

This arithmetic processing device includes a system clock generation circuit having the following configuration. This system clock generation circuit includes a timing generation counter that counts the original oscillation clock, a system clock decoder that generates multiple phase system clocks by decoding the count output of this timing generation counter, and multiple In response to the rising edge of the system clock used for communication with peripheral devices in the phase system clock, the count value of the timing generation counter is temporarily disabled by temporarily disabling the count of the original oscillation clock in the timing generation counter. and system clock timing extension means for keeping the system clock timing constant for a predetermined period.

[Effect]

According to the configuration of the present invention, the system clock timing extension means temporarily disables counting of the original oscillation clock in the timing generation counter in response to the rising edge of the system clock used for communication with peripheral devices. Since the count value of the timing generation counter is kept constant for a predetermined period of time, the fall timing of the system clock used for communication with peripheral devices can be extended during that period. At this time, the period during which the system clock timing extension means temporarily invalidates the count of the original oscillation clock can be arbitrarily set by a command.

As mentioned above, since the time from the rise to the fall of the system clock used for communication with peripheral devices, that is, the waiting time of the timing necessary for communication with peripheral devices, can be set arbitrarily by command, there is no need to lose high speed. It also allows the use of slower peripherals.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

As an example, a circuit diagram of a system clock generation circuit provided in an arithmetic processing device is shown in FIG. 1, and the execution timing of each part of the system clock generation circuit is shown in FIG. 1
The processing execution cycles include SO, Sl, S2. There is a 4-phase system clock for S3, and the system clock is SO.
An example of an arithmetic processing device will be explained in which the read timing for the ROM is the high period of the system clock S2, and the read/write timing for the RAM1 is the high period of the system clock S2. When expanding external ROM or RAM as a peripheral device, the processing time is optimized according to the specifications of the peripheral device.
It is desirable to be able to change the length of the high period of the system clocks SO, S2. In order to realize this, the system clock generation circuit in the arithmetic processing device is configured as shown in FIG.

In FIG. 1, 1. Reference numerals 2 denote flip-flops for timing generation, and these constitute a timing generation counter that counts the original oscillation clock CK. Note that the flip-flop 1 counts the rising edge of the original oscillation clock CK, and the flip-flop 2 counts the falling edge of the original oscillation clock CK. Also, flip-flops.

2 has a set terminal S and a reset terminal r in order to extend the high period of the system clocks SO and S2, and when the set terminal S is low, the output Q is high (“1”).
), and when the reset terminal r is high, the output Q becomes low (“0”), and the original oscillation clock GK during this period.
The input will be invalid. In a normal system clock generation circuit, flip-flops 1. Since a four-phase system clock is generated using only a circuit consisting of flip-flops 1 and 2 and system clock decoder 3, it is not possible to extend only a specific period. By adding the above-mentioned set-reset function to 2, it is possible to extend the time by controlling the signal given to this function. The signal for this reset, that is, the system clock S
A signal that extends the high period of O or a wait signal 5OWA
A signal for setting, that is, a signal for extending the high period of the system clock S2 or a wait signal 52
WAIT.

Reference numeral 3 denotes a system clock decoder consisting of four AND gates, which decodes the count outputs of flip-flops 1 and 2, which are timing generation counters, to generate multiple phases, in this example, four-phase system clocks So and S.
l, S2. Generate S3.

4 is a counter for extending the period of the system clock SO; 5 is a counter for extending the period of the system clock S2; 6 is a flip-flop knob for controlling the start/stop of the counter 4; 7; is flip-flop 1
, 2 is a flip-flop knob that fixes the output of the system clock decoder 3 by fixing the output of the system clock decoder 3. 8 fixes the output of the flip-flop 1.2 and fixes the output of the system clock decoder 3. A flip-flop knob 9 fixes the output of the system clock S2 to a high state, and a flip-flop 9 controls the start/stop of the counter 5, which are connected to the four-phase system clocks SO, Sl, S2. Peripheral devices (ROM) in S3
, RAM) in response to the rising edge of the system clock SO, S2 used for communication with the flip-flop 1.
.

The above flip-flop 6 receives a reload signal 5ORELO which is an output signal at the rising edge of the system clock S3.
AD is set high, and the reload signal 5ORELOAD is set low at the rising edge of the system clock Sl.

The flip-flop 7 makes the output signal, the wait signal 5OWAIT, high at the rising edge of the system clock SO, and outputs the overflow signal 5Oove from the counter 4.
Wait signal 5OWAIT at the rising edge of rf low
set to low. The flip-flop 8 outputs a wait signal 52 which is an output signal at the rising edge of the system clock S2.
WAIT is set high, and at the rising edge of the overflow signal 52overf low from the counter 5, the wait signal 52WAIT is set low. Flip-flop 9 is
At the rising edge of the system clock S1, the reload signal 52RELOAD, which is output, is set to /'t, and at the rising edge of the system clock S3, the reload signal 52RELOAD is output.
set to low.

The counter 4 can arbitrarily set data in the built-in register by a command via the bus BUS, and the data in the built-in register is reloaded into the counter itself while the load signal 5ORELOAD from the flip-flop 6 is low. Counts down to 0 according to the original oscillation clock CK while the reload signal 5ORELOAD is high.
At the point in time, the overflow signal 5Ooverf low for canceling the wait signal 5OWA[T, which extends the high period of the system clock SO, is made high.

Counter 5 similarly sends data to the built-in register on bus B.
Can be set arbitrarily by command via US,
Glue load signal 52RELOA from flip-flop 9
While D is low, the data in the built-in register is reloaded into the counter itself, and while the reload signal 52RELOAD is high, it is counted down by the original oscillation clock CK, and when it reaches 0, it is a wait that extends the high period of the system clock S2. The overflow signal 52overf low for canceling the signal 52WArT is set high.

That is, reload signals 5ORELOAD, 52REL
When OAD is active, the register values are always given to counters 4 and 5, respectively, and counters 4 and 5 do not operate based on the original oscillation clock CK. Using this, reload signals 5ORELOAD, 52RELOAD
The start and stop of the counters 4 and 5 are controlled depending on the timing.

Note that each of the counters 4 and 5 can also read the set value of a built-in register.

Flip-flops 1 and 2 receive the original oscillation clock CK and the way from flip-flop 7.8) Signal 5OWA
IT, 52WJITf: Yotte output (0,0), (
0,l), (1,1), or (1,0). The system clock decoder 3 is configured such that the output of the flip-flop 1.2 is (0, O) and the system clock S3 is
is low, the system clock SO is set high, and flip-flop 1. When the output of 2 is (0, 1) and the system clock SO is low, the system clock S1 is set high, and the output of flip-flop 1.2 is (1, 1).
and when the system clock S+ is low, the system clock S2 is set high, and the flip-flop l is set high.

When the output of 2 is (1, 0) and the system clock S2 is low, the system clock S3 is set high.

Here, the wait signals 5OWAIT, 52WAIT controlling the flip-flop It2 and the counter 4
, 5 to control the start and stop of the load signal 5O
The timing of RELOAD and 52 RELOAD will be explained with reference to FIG.

FIGS. 2(a) to 2(a) show timing diagrams of each part of FIG. 1. In FIG. 2, the original oscillation clock CK and the system clock 50-
33, a reload signal 5ORELOAD, a wait signal 5OWAIT, a reload signal 52RELOAD,
Wait signal 52WAIT, count value 5OCOUNT of counter 4, and overflow signal 5Ooverf
low and the count value of counter 5 32COLINT
and an overflow signal 52overf low, respectively.

Wait signal 5 controlling flip-flops I and 2
The timings of OWA■T and 52WAIT are system clocks generated by the system clock decoder 3 by itself, taking care not to cause the same clock to appear twice or to affect other system clocks.

Set the flip-flop 7 by the rise of
Activate wait signal 5OWAIT.

Similarly, the system clock decoder 3 sets the flip-flop 8 at the rising edge of the system clock s2 generated by itself, and outputs the wait signal 52WArT.
Activate. When the wait signal 5OWAIT is active, the counter 4 counts the value set in the start state using the original oscillation clock CK, and then outputs the overflow signal 5Ooverf.
A low signal is generated to reset the flip-flop 7, and the wait signal 5OWA[T is made inactive. Further, when the wait signal 52WAIT is active, the counter 5 counts the value set in the start state using the original oscillation clock CK, and then generates an overflow signal 52overf low to reset the flip-flop 8. Wait signal 52WA
Make IT inactive.

Next, start and stop counters 4 and 5. r No. 5ORELOAD, 52
Regarding RELOAD timing, reload signal 5
ORELOAD sets the flip-flop 6 at the rising edge of the system clock s3 of the previous cycle to bring it into a start state. Also, the system clock Sl of the next cycle
At the rising edge of , the flip-flop 6 is reset and brought to a stop state. In addition, the reload signal 52RELOAD
At the rising edge of the system clock sl in the previous cycle, the flip-flop 9 is set to enter the start state.

Further, at the rising edge of the system clock S3 in the next cycle, the flip-flop tab 9 is reset to a stop state.

Note that counters 4 and 5 operate only at the falling edge of the original oscillation clock CK, so the values set in counters 4 and 5 can be determined by setting 2 on the SO side and l on the S2 side. , can be extended by a length equal to twice the set value plus 1.

〔Effect of the invention〕

According to the arithmetic processing device of this invention, ROM and RAM
When a storage device such as the It is possible to extend only the timing of accessing storage devices such as ROM and RAM to enable access by low-speed peripheral devices without impairing high-speed access performance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a system clock generation circuit according to an embodiment of the present invention, and FIG. 2 is a timing diagram of each part of the system clock generation circuit. 1.2...Flip-flop (timing generation counter), 3...System clock decoder, 4°5.
・Counter (system clock timing extension means)
, 6 to 9...Flip-flop (system clock timing extension means)

Claims (1)

[Scope of Claims] An arithmetic processing device capable of expanding a storage device externally as a peripheral device, comprising: a timing generation counter that counts an original oscillation clock; and a timing generation counter that counts an original oscillation clock; counting the original oscillation clock in the timing generation counter in response to a rising edge of a system clock used for communication between a system clock decoder that generates a phase system clock and the peripheral device among the plurality of phase system clocks; and a system clock timing extension means for temporarily disabling the timing generation counter to keep the count value of the timing generation counter constant for a predetermined period of time.