JPH04192459A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To perform a writing operation with a small power, and to provide excellent universality, reliability and high integration by providing an insulating film to be dielectrically broken down upon heating by heat generated from a heat generator in a state that a predetermined voltage is applied from electrodes and to control stored data to be output to a bit line in breakdown state and in a non-breakdown state. CONSTITUTION:An FETM 1 is conducted in a state that a predetermined voltage is applied to an insulating film 11, the film 11 is heated by heat generated by supplying a current to a heat generator 12 through a writing bit line WB, the film 11 is broken down to shorten the FETM 1 to the generator 12, thereby writing. If the film 22 is broken down to be short-circuited, the potential of a reading bit line RB is lowered, while if the film 22 is not broken down, the potential of the line RB is not lowered, and stored data is read by the potential change. Thus, power of the writing operation can be reduced without complicating a manufacturing process, excellent universality and reliability as well as high integration are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory cell having an irreversible structure.

(Prior Art) Conventionally, fuse blowing type or junction shorting type memory cells in structurally destructive nonvolatile FROM are known.

FIG. 12 is a diagram showing the structure of a fuse in a fuse blowing type FROM, where (a) is a plan view and (b) is a plan view.
) is a cross-sectional view.

In FIG. 12, a fuse 3 made of polycrystalline silicon, nichrome alloy, or the like is formed on a semiconductor substrate 1 with an insulating film 2 in between and has a narrowed fuse section.

A current is caused to flow through the fuse 3 by a voltage applied to electrodes 4 formed at both ends thereof, and the constricted portion is fused by Joule heat generated by this current and the resistance of the fuse 3.

In order to blow out the fuse 3 in this way, it is necessary to bring the fuse 3 to a considerably high temperature. For this purpose, a large current of several tens of mA or more must be supplied to the fuse 3. Therefore, a circuit that supplies a large current to the fuse 3 is required.

If the circuit for supplying a large current to the fuse 3 is constructed using a field effect transistor (FET), the FET must be made larger in order to increase the current drive capability. However, increasing the size of the FET increases the area it occupies, which becomes an obstacle to high integration.

Therefore, if the circuit for supplying a large current to the fuse 3 is composed of a bipolar transistor with a high current driving ability, the above-mentioned problem can be solved. However, because bipolar transistors are used, the manufacturing process is different, for example, M
It is difficult to apply this to memory cells using OS transistors.

Therefore, when bipolar transistors are used, the applications are considerably limited.

On the other hand, in order to make it easier to blow out the fuse 3, as shown in FIG.
Heat conduction at the fused part is suppressed. Therefore, the portion where the passivation film 5 has been removed is more likely to be affected by external influences, resulting in a decrease in reliability.

Furthermore, since the passivation film 5 above the fusing part is opened, a guard ring (protection area) is required to trap ions generated and scattered during the fusing and prevent adverse effects on the surrounding area. For this reason, a space must be provided between the fuse and the transistor constituting the memory cell, which is an obstacle to high integration.

Furthermore, in the fuse blowing type, the moment the fuse blows, the large current that had been flowing is cut off, which induces an undershoot phenomenon and generates noise. For this reason, there is a risk of malfunction or characteristic deterioration of peripheral elements.

FIG. 13 is a diagram showing a cross-sectional structure of a main part of a memory cell in a PN junction short-circuit type FROM.

In FIG. 13, an N-type region 9 is formed in a P-type region 8 forming an emitter of a bipolar transistor formed in a semiconductor substrate 1, with a P-type head region 6 as a collector and an N-type region 7 as a base. A P-N junction diode is formed by the P-type head region 8 and the N-type region 9.

In such a P-N junction, a reverse bias voltage is applied to the N-type region 9 to cause a breakdown current to flow, and this current causes a P-N junction to flow.
Increase the temperature of the N junction. As a result, the N-type region 9
Writing is performed by inducing an alloy spike in the metal electrode 10 formed above to short-circuit the PN junction by growth of a eutectic alloy between the metal electrode 10 and the N-type region 9.

In a write operation of such a structure, the moment the P-N junction is short-circuited, the voltage drop at the P'-N junction becomes small and a large current flows. Therefore, when writing, P
The circuit that supplies current to the -N junction requires a large transistor that cannot be destroyed by this large current, making it difficult to downsize the structure.

(Problems to be Solved by the Invention) As explained above, in the fuse-blown type and junction-shorted type, which are representative of conventional FROM memory cells, a large current flows through the memory cell during data write operation. Become. Therefore, a circuit configuration that can handle this large current has become necessary. Therefore, in order to realize this, the elements to be used are limited, and the structure becomes larger, causing obstacles to high integration.

Therefore, this invention was made in view of the above, and its purpose is to enable a write operation with low power without complicating the manufacturing process, and to provide excellent versatility and reliability. Another object of the present invention is to provide a semiconductor memory cell that can contribute to high integration.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the invention according to claim 1 provides a heating element that selectively controls heat generation, and a heating element that selectively applies a predetermined voltage. an electrode, and an insulation that is heated by heat generated from the heating element when a predetermined voltage is applied from the electrode and causes dielectric breakdown, and controls stored data output to the bit line in a broken state and a non-destructive state. It consists of a membrane and a shell.

On the other hand, in order to achieve the above object, the invention according to claim 2 provides a heating element that selectively controls heat generation, an electrode to which a predetermined voltage is selectively applied, and a predetermined voltage applied from the electrode. The rectifying junction region is heated by the heat generated from the heating element in the short-circuited state and short-circuited, and controls the stored data output to the bit line in the short-circuited state and the non-shorted state.

(Function) In the above configuration, the invention according to claim 1 performs a writing operation by heating the insulating film with the heat generated from the heating element while applying a predetermined voltage to cause dielectric breakdown, and causing the insulating film to break down. The read operation is performed by controlling the potential of the bit line in a non-destructive manner.

On the other hand, in the above configuration, the invention according to claim 2 performs a write operation by heating the rectifying junction region with heat generated from a heating element while applying a predetermined voltage to short-circuit the rectifying junction region. The read operation is performed by controlling the potential of the bit line depending on whether the bit line is short-circuited or not.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing the main structure of a memory cell according to a first embodiment of the present invention, in which FIG. 1(a) is a plan view and FIG.
b) is a cross-sectional view. In the embodiment shown in FIG. 1, writing is performed by destroying an insulating film, and the object to be destroyed and the object to be destroyed are each constructed separately.

First, before explaining the structure shown in FIG. 1, the structure and operation of a memory cell using the main structure shown in FIG. 1 will be explained using the equivalent circuit diagram shown in FIG.

In FIG. 9, the memory cell includes a thin insulating film (capacitor) 11 on one side of which is connected to the read bit line RB via an FET (field effect transistor) Ml whose conduction is controlled by the potential of the read word line RW; A heating element made of a resistor that is connected in series with FETM2 whose conduction is controlled by the potential of the write word line WW, is connected between the write bit line WB and the ground, and is in contact with the other surface of the insulating film 11 to heat the insulating film 11. It consists of 12.

In such a configuration, data is written into the memory cell by destroying the insulating film 11 forming the capacitor. That is, in a state where FETMI is in a conductive state and a predetermined voltage is applied from read bit line RB to insulating film 11 via FETMI, FET
The insulating film 11 is heated by the heat generated by making MI conductive and passing a current through the heating element 12 via the write bit line WB. As a result, the insulating film 11 is destroyed, the FETMI and the heating element 12 are short-circuited, and writing is performed.

Next, the read operation will be explained.

When performing a read operation, first, FET Ml, M2
is rendered non-conductive, the write bit line WB is connected to ground, and the read bit line RB is precharged. In this state, FET M1 is rendered conductive, and a change in the potential of the read bit line RB is detected by a sense amplifier (not shown) connected to the read bit line RB.

That is, when the insulating film 11 is broken and is in a short-circuit state, the potential of the read bit line RB decreases, and the insulating film 11
If the bit line RB is not destroyed, the potential of the read bit line RB does not drop, and the stored data is read out by this potential change.

Next, returning to FIG. 1, the main structure of the memory cell will be explained.

In FIG. 1, for example, a thin oxide film 15 surrounded by a field oxide film 14 is formed on a P-type semiconductor substrate 13 to a thickness of, for example, about 200A, and gate oxide of a transistor of a memory cell is formed. It is formed simultaneously when forming the film. This oxide film 15 corresponds to the insulating film 11 shown in FIG.

In contact with this oxide film 15, the semiconductor substrate 1 under the oxide film 15
3, an N-type diffusion layer 16 is formed by ion implantation. On the other hand, polycrystalline silicon 17 having a width of about 0.7 μm and a thickness of about 4000 A is formed on the oxide film 15 in contact with the oxide film 15, and electrodes 18 are formed on both ends of the polycrystalline silicon 17. There is. This polycrystalline silicon 1
This corresponds to the heating element 12 shown in FIG.

In such a structure, a voltage of about 10 V is supplied to the diffusion layer 16, and a current of about 5 mA is caused to flow through the polycrystalline silicon 17 of the resistor while the voltage is applied to one side of the oxide film 15. As a result, the polycrystalline silicon 17 is heated to 600°C to 80°C.
The temperature rises to about 0.degree. C., and the Joule heat heats the oxide film 15, causing dielectric breakdown, and short-circuiting the diffusion layer 16 and polycrystalline silicon 17. Note that the reason for applying voltage to the oxide film 15 is to promote and facilitate destruction.

In this way, by destroying the insulating film with low voltage and low current, a write operation to the memory cell can be achieved. Furthermore, unlike the conventional short-circuited junction type, it is avoided that a large current flows at the moment of short-circuiting.

Therefore, it is no longer necessary to use a large FET or bipolar transistor to write data, and an FET of a size that is normally used can suffice. This makes it possible to improve the degree of integration.

Further, since it is no longer necessary to open and remove the passivation film (not shown) formed over the entire surface on the oxide film 15, there is no reduction in reliability.

Furthermore, since the guard ring region described in the related art is not required, the distance between the region where the oxide film 15 is formed and the surrounding transistors can be made shorter than in the prior art. Also,
The oxide film 15 as the object to be destroyed, the diffusion layer 16 and the polycrystalline silicon 17 as the objects to be destroyed have separate structures, but since each is formed vertically with respect to the substrate 13, Separate configurations do not increase the area. These factors can significantly reduce the area occupied by the memory memory, contributing to higher integration.

Furthermore, even if the oxide film 15 is destroyed and the diffusion layer 16 and the polycrystalline silicon 17 are short-circuited, a large current will not flow instantaneously or be cut off instantaneously, so noise will be generated during writing. It can also be prevented.

Note that the voltage and current value at which the oxide film 15 is destroyed is determined by the shape of the oxide film 15 and the resistance value of the polycrystalline silicon 17. Further, the diffusion layer 16 may be of P type, as long as it is of a conductivity type opposite to that of the substrate 13.
FIG.
Figure (b) is a cross-sectional view. In the drawings shown below, the same reference numerals as those in FIG. 1 are the same, and the explanation thereof will be omitted.

The feature of the second embodiment shown in FIG. 2 is that an insulating film 19 serving as an object to be destroyed is formed on the circumferential surface of a rectangular polycrystalline silicon 20 formed on a field oxide film 14,
This is because polycrystalline silicon 21 serving as a heating element is formed to cover insulating film 19. This insulating film 19 is formed of a polycrystalline silicon oxide film formed by oxidizing polycrystalline silicon 20, or a multilayer film (ONO film) formed by stacking a silicon oxide film and a silicon nitride film.

In such a structure, the insulating film 19 is heated by heat generated by passing a current through the polycrystalline silicon 21 while a voltage is applied to the polycrystalline silicon 20 forming the base of the insulating film 19. The membrane 19 is destroyed. In such a breakdown process, the insulating film 19 has corners where dielectric breakdown is more likely to occur than flat parts, so it has the characteristic that dielectric breakdown is more likely to occur than in the embodiments described above. are doing.

FIG. 3 is a diagram showing the structure of a third embodiment of the present invention, with FIG. 3(a) being a plan view and FIG. 3(b) being a sectional view.

The third embodiment shown in FIG. 3 is characterized by an insulating film 22 made of a polycrystalline silicon oxide film or an ONO film.
is formed on polycrystalline silicon or high melting point silicide which is formed on the field oxide film 14 and becomes the heating element 12, and an electrode 23 made of aluminum alloy or high melting point silicide is formed on the insulating film 22. be.

In such a structure, the electrode 23 on the insulating film 22 is heated by the heat generated from the heating element 12, forming alloy spikes and forming a eutectic alloy with the insulating film 22. is destroyed. Therefore, in this embodiment, the voltage applied from the electrode 23 to the insulating film 22 can cause dielectric breakdown at a lower value than in the above-mentioned embodiments, and the write operation can be performed at a lower voltage. can be achieved. ' FIG. 4 is a sectional view showing the structure of the fourth embodiment.

The feature of the embodiment shown in the figure is that the semiconductor substrate 1
Diffusion layer 2 formed relatively shallowly with low concentration on the surface layer of 3.
4 forms a heating element, and the substrate 1 is placed on this diffusion layer 24.
In this structure, an insulating film 25 made of an oxide film obtained by oxidizing 3 is formed, and an electrode 26 made of an aluminum alloy is formed on this insulating film 25.

In such a structure, while a voltage is applied to the electrode 26, a voltage is applied between the electrodes 28 whose contact regions are the high concentration diffusion layers 27 formed on both sides of the diffusion layer 24, thereby causing diffusion. For example, a current of about 10 mA is passed through the layer 24. As a result, the insulating film 25 is heated by the heat generated by the diffusion layer 24, and the insulating film 25 is heated in the same manner as in the third embodiment.
destroy. Therefore, even with this structure,
It is possible to obtain the same effects as in the third embodiment.

FIG. 5 is a diagram showing the structure of the fifth embodiment, and FIG.
) is a plan view, (b) is a cross-sectional view, and (C) is a plan view (
It is a sectional view along line BB of b).

The feature of the embodiment shown in FIG. 5 is that, instead of the insulating film shown in the previous embodiment, a Schottky junction having rectifying properties is destroyed by heat generated from a heating element, so that three write operations can be performed. It was designed to do this. As shown in the equivalent circuit diagram of FIG. 10, the circuit configuration is such that a Schottky junction diode 29 connects write bit lines WB and F.
The read operation is performed with the Schottky junction in a reverse bias state.

In order to realize the circuit configuration shown in FIG. 10, as shown in FIG.
1 to form a Schottky junction, and a heating element 12 made of polycrystalline silicon or high melting point silicide insulated from the surroundings is formed near the Schottky junction as shown in FIG. 5(C).

In such a structure, the diffusion layer 30 and the electrode 31 are heated by heating the Schottky junction with the heat generated by passing a current of about 5 mA through the heating element 12 while applying a voltage of about 5 V to the electrode 31. A eutectic alloy is formed, which destroys the Schottky junction.

FIG. 6 is a diagram showing the structure of the sixth embodiment, and FIG.
) is a plan view, and (b) is a sectional view.

The feature of this embodiment is that a Schottky junction diode 34 is formed by a low concentration diffusion layer 32 formed on a substrate 13 and an electrode 33 made of an aluminum alloy formed on and in contact with this diffusion layer 32. The heating element is also constructed from the diffusion layer 32 forming one side of the Schottky junction, and the circuit configuration is as shown in the equivalent circuit diagram of FIG.

In such a structure, while a voltage of about 5 V is applied to the electrode 33, a voltage is applied between the electrodes 35 whose contact regions are the highly concentrated diffusion layers 34 formed on the substrate 13 on both sides of the diffusion layer 32. Then, a current of about 10 mA is passed through the diffusion layer 32, and the heat generated thereby heats and destroys the Schottky junction.

FIG. 7 is a diagram showing the structure of the seventh embodiment, and FIG.
) is a plan view, and (b) is a sectional view.

The feature of the embodiment shown in FIG. 7 is that a P
The reason is that a '-N junction diode is formed, and the circuit configuration is as shown in FIG.

In FIG. 7, a P-type diffusion layer 36 formed in the substrate 13 by, for example, boron ion implantation, and this diffusion layer 36 are shown.
A P-N junction is formed with a high concentration N-type diffusion layer 37 formed shallowly by, for example, arsenic ion implantation, and an electrode 38 made of an aluminum alloy is formed in contact with the diffusion layer 37. 36 forms a heating element.

In such a structure, a reverse bias voltage higher than the junction breakdown voltage is applied to the electrode 38 to bring it into a reverse bias state, and the electrode 40 formed on the three contact regions formed on the substrate 13 on both sides of the P-type diffusion layer 360 A voltage is applied between them to cause a current of about 5 to 10 mA to flow through the P-type diffusion layer 36. As a result, the electrode 38 is heated by the heat generated by the diffusion layer 36,
An alloy spike is formed on the electrode 38, and the PN junction is destroyed by the growth of the eutectic alloy between the diffusion layers 36 and 37 and the aluminum electrode 38. A read operation is performed by applying a reverse bias voltage below the junction breakdown voltage to the PN junction.

FIG. 8 is a diagram showing the structure of the eighth embodiment, and FIG.
) is a plan view, and (b) is a sectional view.

The feature of the embodiment shown in FIG. 8 is that, as shown in FIG. The electrode 43 made of aluminum alloy formed in contact with the N-type diffusion layer 42 is heated by the heat generated by the heating element 12 made of polycrystalline silicon or high melting point silicide formed insulated from the surroundings, and Similar to the seventh embodiment, the P-N junction is destroyed, and the circuit configuration is as shown in FIG. 10.

In such a structure, since the heating element 12 is insulated from the surroundings, the heat generation efficiency is higher than when the heating element is shared with one region of the P-N junction, and the power supply to the heating element is increased. It becomes possible to destroy the p-N junction by reducing the current applied.

Note that the present invention is not limited to the above embodiments; for example, the combination of materials in the insulating film 11, the heating element 12, the insulating film 11, and the metal electrode that destroys the rectifying junction such as the Schottky junction or the P-N junction is as follows: The invention is not limited to the above embodiments. Further, the conductivity type of the diffusion layer may be determined according to the conductivity type of the substrate 13. Further, the voltage and current values at which the insulating film and rectifying junction are destroyed are determined according to the resistance value of the heating element 12 and the like.

[Effects of the Invention] As explained above, according to the present invention, the write operation is performed by heating the insulating film or the rectifying junction by heating it with the heat generated from the heating element and creating a short circuit state. Therefore, it is possible to provide a semiconductor memory cell that can reduce the power consumption of the write operation without complicating the manufacturing process, has excellent versatility and reliability, and is suitable for high integration.

[Brief explanation of the drawing]

FIGS. 1 to 8 are diagrams showing the structure of main parts in the first to eighth embodiments of the present invention, and FIGS. 9 to 11 are diagrams showing structures of main parts in the first to eighth embodiments of the present invention. Equivalent circuit diagrams of memory cells, Figures 12 to 13
The figure shows the main structure of a conventional FROM memory cell. 1.13... Semiconductor substrate, 2.14... Field insulating film, 11.15, 19, 22.25... Insulating film, 12.1
7.21, 24, 32.36...Heating element, 16.30
... Diffusion layer, 20.2B, 26, 31.33.38.43... Electrode, 29... Schottky junction diode, 34... P-
N-junction diode. Figure 5 (a) Figure 5 (b) Figure 5 (C) Figure 6 (a) Figure 6 (b) Figure 7 (b) ~4 ~2 Mo-1 Figure 12 (b) Figure 13

Claims (5)

[Claims] (1) A heating element that selectively controls heat generation, an electrode to which a predetermined voltage is selectively applied, and an insulating material that is heated by the heat generated from the heating element while a predetermined voltage is applied from the electrode. A semiconductor memory cell characterized by having an insulating film that is destroyed and controls stored data output to a bit line in a destroyed state and a non-destructive state. (2) A heating element that selectively controls heat generation, an electrode that selectively applies a predetermined voltage, and a short circuit that is heated by the heat generated from the heating element while the predetermined voltage is applied from the electrode. 1. A semiconductor memory cell comprising a rectifying junction region that controls stored data output to a bit line in a short-circuited state and a non-shorted state. (3) The semiconductor memory cell according to claim 1 or 2, wherein the heating element is formed insulated from the surroundings. (4) The semiconductor memory cell according to claim 1, wherein one of the junction regions forming the rectifying junction region and the heating element are common. (5) The semiconductor memory cell according to claim 1 or 2, wherein the insulating film or the rectifying junction region is dielectrically broken or short-circuited by a eutectic reaction with the electrode.