JPH049388B2 - - Google Patents
Info
- Publication number
- JPH049388B2 JPH049388B2 JP17932380A JP17932380A JPH049388B2 JP H049388 B2 JPH049388 B2 JP H049388B2 JP 17932380 A JP17932380 A JP 17932380A JP 17932380 A JP17932380 A JP 17932380A JP H049388 B2 JPH049388 B2 JP H049388B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- source
- impurity region
- gate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000006378 damage Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 101100521334 Mus musculus Prom1 gene Proteins 0.000 description 5
- 238000007664 blowing Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は半導体記憶装置に係り、特に情報の書
き込みが１回限りで変更のできないPROM
（Programable Read−Only Memory）に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and in particular to a PROM in which information can be written only once and cannot be changed.
(Programmable Read-Only Memory).
従来よりPROMにはヒユーズ溶断形のPROM、
ダイオード短絡形のPROMなどがある。これら
のメモリは使用者がメモリの各ビツトに作られた
ヒユーズやダイオード（Ｐ−ｎ接合）を過電流に
より溶断するか、過電圧により破壊するかにより
各ビツトに情報を記憶させるものである。 Traditionally, fuse-blown PROMs have been used as PROMs.
There are diode-shorted PROMs, etc. In these memories, information is stored in each bit by the user blowing out a fuse or diode (P-n junction) formed in each bit of the memory by overcurrent or destroying it by overvoltage.
しかし、これらPROMはヒユーズの溶断、も
しくはＰ−ｎ接合の永久破壊の再現性が低く、
IC（集積回路）製造上製品の歩留りを低下させて
いること、微細化、高密度化が難しく、プロセス
マージンが小さいこと、溶断破壊に要する電圧が
高いことなどの欠点を有している。 However, these PROMs have low reproducibility of fuse blowing or permanent destruction of P-n junctions.
It has disadvantages such as lowering the yield of IC (integrated circuit) products, making it difficult to miniaturize and increase density, having a small process margin, and requiring a high voltage for fusing and destruction.
本発明は上記実情に鑑みなされたもので、その
目的は、半導体基板上に形成された通常のMOS
形電界効果トランジスタ構造において、例えばソ
ース領域でのソース拡散層とソース用配線材料と
の間に薄い絶縁膜を介在させる構造を取ることに
より、ソース拡散層とソース用配線材料とを絶縁
し、その絶縁膜に使用者が外部より強制的に過電
圧を印加し永久絶縁破壊させることにより、ソー
ス拡散層とソース用配線材料を導通させ、外部か
ら情報を記憶させることのできる半導体記憶装置
を提供することにある。 The present invention has been made in view of the above circumstances, and its purpose is to
In a type field effect transistor structure, for example, by adopting a structure in which a thin insulating film is interposed between the source diffusion layer and the source wiring material in the source region, the source diffusion layer and the source wiring material are insulated, and the source wiring material is insulated. To provide a semiconductor memory device in which a source diffusion layer and a source wiring material are electrically connected to each other by a user forcibly applying an overvoltage to an insulating film from the outside to cause permanent dielectric breakdown, and information can be stored from the outside. It is in.
本発明による半導体記憶装置は、従来のヒユー
ズ溶断形、ダイオード短絡形に比べ、現在の
MOSトランジスタ製造工程に対して、例えばソ
ース拡散層とソース用配線材料との間に薄い絶縁
膜を形成するという簡単な工程を加えることによ
り得られることから、本質的に単純なMOS形電
界効果トランジスタ構造であり、高密度化が容易
であること、絶縁膜形成の制御のよさから、絶縁
膜破壊電圧（書き込み電圧）の再現性の良さ、お
よび低電圧化に有利であることなどの優れた特徴
を有している。 The semiconductor memory device according to the present invention is superior to the conventional fuse blowing type and diode shorting type.
Because it can be obtained by adding a simple step to the MOS transistor manufacturing process, such as forming a thin insulating film between the source diffusion layer and the source wiring material, it is essentially a simple MOS field effect transistor. structure, it is easy to increase the density, the insulation film formation is well controlled, the insulation film breakdown voltage (writing voltage) has good reproducibility, and it is advantageous for lowering the voltage. have.
以下、図面を参照して本発明の一実施例を説明
する。この実施例においてはMOS形電界効果ト
ランジスタとして、エンハンスメント形（チヤネ
ル領域へのボロンのイオン注入によりしきい値電
圧は〜1Vに制御されている。）のｎチヤネルトラ
ンジスタを用いる。第１図はこのｎチヤネル
MOSトランジスタの公知の製造方法において、
コンタクトホールをゲート、ソース、ドレインに
形成した段階における断面図である。図面におい
て１はＰ型シリコン基板、２は例えばヒ素（As）
の高濃度拡散によるソース拡散領域、３は同じく
ドレイン拡散領域、４は例えばシリコン酸化膜に
よるゲート絶縁膜、５は例えばリン拡散を施した
多結晶シリコンで形成されたゲート電極、６はチ
ヤネル領域、７〜１０は例えば酸化シリコンによ
る絶縁膜、１１はソースコンタクトホール、１２
はゲートコンタクトホール、１３はドレインコン
タクトホールを示す。本発明における製造工程
は、第１図に示す工程まで公知のMOSトランジ
スタの製造工程と同様であり、その特徴は引き続
き行う工程にある。すなわち、第１図に示した構
造を得た後、例えば公知の熱酸化法によりシリコ
ン酸化膜をコンタクトホール開孔面１１，１２，
１３に薄く形成する。シリコン酸化膜厚は一例と
して〜100Åとする。引き続き公知のフオトエツ
チング方法を用いて第２図に示すようにソースコ
ンタクトホール１１にのみ薄いシリコン酸化膜１
４を残す。この段階でゲートコンタクトホール１
２ではゲート電極５の多結晶シリコンが、ドレイ
ンコンタクトホール１３ではドレイン拡散領域３
が露出している。次に、基板全面に例えばアルミ
ニウム（Al）を公知の方法により堆積し、フオ
トエツチング方法を用いて第３図に示すようにソ
ース配線（電極）１５、ゲート配線（電極）１
６、ドレイン配線（電極）１７を加工する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In this embodiment, an enhancement type n-channel transistor (threshold voltage is controlled to 1 V by boron ion implantation into the channel region) is used as the MOS field effect transistor. Figure 1 shows this n channel.
In a known method for manufacturing MOS transistors,
FIG. 3 is a cross-sectional view at a stage where contact holes are formed in the gate, source, and drain. In the drawing, 1 is a P-type silicon substrate, and 2 is, for example, arsenic (As).
3 is also a drain diffusion region, 4 is a gate insulating film made of, for example, a silicon oxide film, 5 is a gate electrode formed of, for example, polycrystalline silicon subjected to phosphorus diffusion, 6 is a channel region, 7 to 10 are insulating films made of silicon oxide, 11 are source contact holes, and 12 are
13 indicates a gate contact hole, and 13 indicates a drain contact hole. The manufacturing process of the present invention is similar to the known manufacturing process of MOS transistors up to the step shown in FIG. 1, and its feature lies in the subsequent steps. That is, after obtaining the structure shown in FIG. 1, a silicon oxide film is formed on contact hole opening surfaces 11, 12,
Form into a thin layer of 13. The thickness of the silicon oxide film is, for example, ~100 Å. Subsequently, using a known photoetching method, a thin silicon oxide film 1 is formed only in the source contact hole 11, as shown in FIG.
Leave 4. At this stage, gate contact hole 1
2, the polycrystalline silicon of the gate electrode 5 and the drain diffusion region 3 of the drain contact hole 13
is exposed. Next, aluminum (Al), for example, is deposited on the entire surface of the substrate by a known method, and a source wiring (electrode) 15 and a gate wiring (electrode) 1 are formed using a photoetching method as shown in FIG.
6. Process the drain wiring (electrode) 17.
これら一連の工程により通常のMOSトランジ
スタの製造工程に対して、ソース拡散領域２とソ
ース配線１５との間に薄い絶縁膜（シリコン酸化
膜１４）を有するMOSトランジスタが製造され
る。 Through these series of steps, a MOS transistor having a thin insulating film (silicon oxide film 14) between the source diffusion region 2 and the source wiring 15 is manufactured, compared to the normal MOS transistor manufacturing process.
次に本発明による半導体記憶装置の動作原理に
ついて述べる。第３図に示すようにソース電位を
VS、ゲート電位をVG、ドレイン電位をVDとし、
またシリコン基板１の裏面は接地電位（＝OV）
とする。 Next, the operating principle of the semiconductor memory device according to the present invention will be described. The source potential is changed as shown in Figure 3.
V S , gate potential V G , drain potential V D ,
Also, the back surface of the silicon substrate 1 is at ground potential (=OV)
shall be.
ゲート電位VG＝10V、ソース電位VS＝OVの状
態でドレイン電位VD＝10Vとすると、このトラ
ンジスタのしきい値電位は、1Vに設定してあれ
ば、ゲート絶縁膜４下にチヤネル領域６が形成さ
れる。この時ドレイン電位VD＝10Vはソース拡
散領域２とソース配線１５間の薄いシリコン酸化
膜１４にかかることになる。シリコン酸化膜１４
の永久破壊に要する電界は〜106V／cmであるの
で、シリコン酸化膜１４（100Å）内の電界が
107V／cmであることから永久破壊を起こし、ソ
ース拡散領域２とソース配線１５は導通状態とな
る。この時、本発明の構造は通常のMOSトラン
ジスタと同一の特性を持つことになる。 If the gate potential V G = 10 V, the source potential V S = OV, and the drain potential V D = 10 V, then if the threshold potential of this transistor is set to 1 V, there will be a channel region under the gate insulating film 4. 6 is formed. At this time, the drain potential V D =10V is applied to the thin silicon oxide film 14 between the source diffusion region 2 and the source wiring 15. Silicon oxide film 14
Since the electric field required for permanent destruction of is ~10 6 V/cm, the electric field within the silicon oxide film 14 (100 Å) is
Since the voltage is 10 7 V/cm, permanent destruction occurs, and the source diffusion region 2 and the source wiring 15 become electrically connected. At this time, the structure of the present invention has the same characteristics as a normal MOS transistor.
一方、ゲート電位VG＝OVの時はゲート絶縁膜
４下にはチヤネルが形成されず、ドレイン電位
VD＝10Vはシリコン基板１が接地されているこ
とから、ドレイン拡散領域３とＰ型シリコン基板
１からなるＰ−ｎ接合に逆バイアスとしてかか
り、シリコン酸化膜１４にはかからない。従つ
て、シリコン酸化膜１４の永久破壊は起こらず、
通常のMOSトランジスタ構造にはならない。 On the other hand, when the gate potential V G =OV, no channel is formed under the gate insulating film 4, and the drain potential
Since the silicon substrate 1 is grounded, V D =10V is applied as a reverse bias to the P-n junction formed by the drain diffusion region 3 and the P-type silicon substrate 1, and is not applied to the silicon oxide film 14. Therefore, permanent destruction of the silicon oxide film 14 does not occur.
It does not have a normal MOS transistor structure.
このようにVD＝10V、VS＝OV、シリコン基板
１が接地の状態で、ゲート電位VGを変えること
により、本発明の構造を持つMOSトランジスタ
は安定な２つの状態に変わり得ることから、半導
体記憶装置となり得る。 In this way, when V D = 10 V, V S = OV, and the silicon substrate 1 is grounded, by changing the gate potential V G , the MOS transistor having the structure of the present invention can be changed into two stable states. , can be a semiconductor memory device.
本発明による半導体記憶装置は、従来のMOS
トランジスタ製造工程に対してソース領域上に薄
いシリコン酸化膜を形成するという工程を加える
のみでよく、簡便であること、シリコン酸化膜の
膜厚の制御が再現性よく簡単であること、シリコ
ン酸化膜の永久破壊に要する電圧がシリコン酸化
膜の膜厚のみにより決まることからシリコン酸化
膜厚を適当に選ぶことにより書き込みに要する電
圧（ドレイン電圧）を任意に選ぶことができ、ま
た低電圧化も容易である。 The semiconductor memory device according to the present invention is a conventional MOS
The transistor manufacturing process requires only the addition of a step of forming a thin silicon oxide film on the source region, which is simple; the thickness of the silicon oxide film can be easily controlled with good reproducibility; Since the voltage required for permanent destruction of the device is determined only by the thickness of the silicon oxide film, by appropriately selecting the thickness of the silicon oxide film, the voltage required for writing (drain voltage) can be arbitrarily selected, and it is also easy to lower the voltage. It is.
以上、本発明の半導体記憶装置についてその構
造及び特徴について、ソース領域上の絶縁膜とし
てシリコン酸化膜を、また配線材料としてアルミ
ニウムを用いて説明を行なつたが、他の例として
シリコン酸化膜としてはシリコン窒化膜、金属酸
化物、配線材料としては高融点金属（Mo、Ｗ、
Ti、Ta、Pt）などを用いることもできる。さら
に、シリコン酸化膜の絶縁破壊時に流れる過電流
によるMOSトランジスタ自体の破壊を防ぐ目的
で、ドレイン領域側若しくはソース領域側の配線
中に数KΩの抵抗（例えば多結晶シリコン）を入
れるのが望ましい。 Above, the structure and characteristics of the semiconductor memory device of the present invention have been explained using a silicon oxide film as an insulating film on the source region and aluminum as a wiring material. are silicon nitride films, metal oxides, and high melting point metals (Mo, W,
Ti, Ta, Pt), etc. can also be used. Furthermore, in order to prevent the MOS transistor itself from being destroyed by an overcurrent flowing when the silicon oxide film breaks down, it is desirable to insert a resistor of several kilohms (for example, polycrystalline silicon) into the wiring on the drain region side or the source region side.
また、上記実施例ではソース領域側に絶縁膜を
設ける構成としたが、これに限定するものではな
く、ドレイン領域側に設ける構成としてもよく、
さらにソース領域及びドレイン領域の両方に設
け、両者が同時に破壊する構成としてもよい。 Further, in the above embodiment, the insulating film is provided on the source region side, but the insulating film is not limited to this, and may be provided on the drain region side.
Furthermore, it may be provided in both the source region and the drain region so that both are destroyed at the same time.
第１図乃至第３図は本発明の一実施例に係わる
半導体記憶装置の製造工程を示す断面図である。
１……Ｐ型シリコン基板、２……ソース拡散領
域、３……ドレイン拡散領域、４……ゲート絶縁
膜、５……ゲート電極、６……チヤネル領域、７
〜１０……絶縁膜、１１〜１３……コンタクトホ
ール、１４……シリコン酸化膜。
1 to 3 are cross-sectional views showing the manufacturing process of a semiconductor memory device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Source diffusion region, 3... Drain diffusion region, 4... Gate insulating film, 5... Gate electrode, 6... Channel region, 7
~10...Insulating film, 11-13...Contact hole, 14...Silicon oxide film.
Claims (1)
と、この半導体基板に形成された反対導電型のソ
ース不純物領域及びドレイン不純物領域と、 上記ソース不純物領域とドレイン不純物領域と
の間の半導体基板表面にゲート絶縁膜を介して形
成されたゲート電極と、 上記ソース不純物領域あるいはドレイン不純物
領域の何れか一方の不純物領域表面に形成された
薄い絶縁膜と、 この薄い絶縁膜上に形成され接地電位に設定さ
れた電極とを具備し、 前記薄い絶縁膜が形成されない側の他方の不純
物領域には、前記ゲート電極にゲート電圧を印加
した際に前記ゲート絶縁膜直下に形成されるチヤ
ネル領域及び前記一方の不純物領域を介して、前
記薄い絶縁膜にその絶縁破壊に要する電圧を印加
する電極を有することを特徴とする半導体記憶装
置。[Claims] 1. A semiconductor substrate of one conductivity type set to a ground potential, a source impurity region and a drain impurity region of opposite conductivity type formed in this semiconductor substrate, and the source impurity region and drain impurity region a gate electrode formed on the surface of the semiconductor substrate between them via a gate insulating film; a thin insulating film formed on the surface of either the source impurity region or the drain impurity region; the other impurity region on the side where the thin insulating film is not formed has an electrode formed directly under the gate insulating film when a gate voltage is applied to the gate electrode; A semiconductor memory device comprising an electrode for applying a voltage required for dielectric breakdown to the thin insulating film through the channel region and the one impurity region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17932380A JPS57103348A (en) | 1980-12-18 | 1980-12-18 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17932380A JPS57103348A (en) | 1980-12-18 | 1980-12-18 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57103348A JPS57103348A (en) | 1982-06-26 |
| JPH049388B2 true JPH049388B2 (en) | 1992-02-20 |
Family
ID=16063820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17932380A Granted JPS57103348A (en) | 1980-12-18 | 1980-12-18 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57103348A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4782466A (en) * | 1985-09-04 | 1988-11-01 | Fujitsu Limited | Programmable semiconductor read only memory device |
| KR101927443B1 (en) * | 2012-08-22 | 2018-12-10 | 에스케이하이닉스 주식회사 | Semiconductor device and method for fabricating the same |
| US10090360B2 (en) * | 2015-02-13 | 2018-10-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor structure including a plurality of trenches |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5691464A (en) * | 1979-12-25 | 1981-07-24 | Fujitsu Ltd | Semiconductor device |
| JPS5691466A (en) * | 1979-12-25 | 1981-07-24 | Fujitsu Ltd | Selective writing possible semiconductor element |
-
1980
- 1980-12-18 JP JP17932380A patent/JPS57103348A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5691464A (en) * | 1979-12-25 | 1981-07-24 | Fujitsu Ltd | Semiconductor device |
| JPS5691466A (en) * | 1979-12-25 | 1981-07-24 | Fujitsu Ltd | Selective writing possible semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57103348A (en) | 1982-06-26 |
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