JPH04192362A - Manufacture of electrostatic induction semiconductor device - Google Patents
Manufacture of electrostatic induction semiconductor deviceInfo
- Publication number
- JPH04192362A JPH04192362A JP19353190A JP19353190A JPH04192362A JP H04192362 A JPH04192362 A JP H04192362A JP 19353190 A JP19353190 A JP 19353190A JP 19353190 A JP19353190 A JP 19353190A JP H04192362 A JPH04192362 A JP H04192362A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- semiconductor device
- conductivity type
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 230000006698 induction Effects 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000003068 static effect Effects 0.000 claims description 8
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 7
- 230000001133 acceleration Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000002347 injection Methods 0.000 abstract 3
- 239000007924 injection Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 101000635799 Homo sapiens Run domain Beclin-1-interacting and cysteine-rich domain-containing protein Proteins 0.000 abstract 1
- 102100030852 Run domain Beclin-1-interacting and cysteine-rich domain-containing protein Human genes 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 241000238557 Decapoda Species 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 241001663154 Electron Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
この発明は半導体装置、特に静電誘導型の半導体装置の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, particularly an electrostatic induction type semiconductor device.
（従来の技術〕
第２図（ｉ）は従来の埋込みゲート層を有する静電誘導
型サイリスタ（以下５ＩＴｈと称する）の断面図であり
、図におて、１はＮ−基板、４はガードリングＰ″領域
、６は埋込みＰ令頁域、７はＮ−エビ層、８はカソード
Ａ１電極、９はアノードＰ゛領域、１２はパッシベーシ
ョン膜、１３はカソードＡ１電極、１４はゲートＡｆｆ
ｉ電極、１５はセグメントパッシベーション膜、１６は
Ｔｉ蒸着膜、１７はＮｉ蒸着膜、１８はＡｕ蒸着膜であ
る。(Prior Art) FIG. 2(i) is a cross-sectional view of a conventional static induction thyristor (hereinafter referred to as 5ITh) having a buried gate layer. In the figure, 1 is an N-substrate, 4 is a guard Ring P'' area, 6 is embedded P area, 7 is N-layer, 8 is cathode A1 electrode, 9 is anode P'' area, 12 is passivation film, 13 is cathode A1 electrode, 14 is gate Aff
In the i-electrode, 15 is a segment passivation film, 16 is a Ti vapor deposited film, 17 is a Ni vapor deposited film, and 18 is an Au vapor deposited film.
５ＩＴｈはゲート電極１４に印加する電圧によってゲー
ト近傍の空乏層を制御して電流をオン。5ITh controls the depletion layer near the gate by the voltage applied to the gate electrode 14 to turn on the current.
オフするものであり、その特性は例えば、Ｊ、Ｎ１５ｈ
ｉｚａｈａ、に、Ｍｕｒａｏｋａ、Ｔ、Ｔａｍａｍｕｓ
ｈｉ、ａｎｄ Ｙ、Ｋａｗａｍｕｒａ。It turns off, and its characteristics are, for example, J, N15h
izaha, ni, Muraoka, T, Tamamus
Hi, and Y, Kawamura.
’Ｌｏｗ−１ｏｓｓ ｈｉｇｈ−ｓｐｅｅｄ ｓｓｍｉ
ｔｃｈｉｎｇ ｄｅｖｔｃｅｓ、２３００−ｖ１５０−
＾５ｔａｔｉｃ １ｎｄｕｃｔｉｏｎ ｔｈｙｒｉｓｔ
ｏｒ、”ＩＥＥＥ Ｔｒａｎｓ、Ｅｌｅｃｔｒｏｎ Ｄ
ｅｖｉｃｅｓ、ｖｏｌ、ＥＤ−３２，ｎｏ、４．ｐｐ、
８２２−８３０、１９８５に記載されているように、高
耐圧、大容量デバイスとして高速スイッチングを実現で
きる等の利点がある。'Low-1oss high-speed ssmi
tching devtces, 2300-v150-
＾5tatic 1induction thyrist
or, “IEEE Trans, Electron D
evices, vol, ED-32, no, 4. pp,
822-830, 1985, it has advantages such as being able to realize high-speed switching as a high-voltage, large-capacity device.
以上の構造を有する５ＩＴｈの製造方法の一例を第２図
を用いて順次説明する。An example of a method for manufacturing 5ITh having the above structure will be sequentially explained using FIG. 2.
Ｎ−シリコン基板１にＦＺ＜１１１＞を用い、その裏面
に裏面保護用の５ｉＯｚ膜２を形成し、基板１上面に拡
散マスクとしてのＳｉｎｇ膜３を設はボロン気相デボを
用いた選択拡散によってガードリングＰ″領域４を形成
する。FZ<111> is used for the N-silicon substrate 1, a 5iOz film 2 for back surface protection is formed on the back surface, and a Sing film 3 as a diffusion mask is provided on the top surface of the substrate 1. Selective diffusion using boron vapor phase deposition is performed. A guard ring P'' region 4 is formed by this.
次に図（ｂ）に示すように一旦、５ｉｆｔ膜３を除去し
た後、全面にＳ ＩＯｚ膜５を形成し更にレジストマス
ク５０を形成した後、ボロンイオン注入１００によって
Ｐゲート９Ｍ域６を形成する。Next, as shown in Figure (b), after removing the 5ift film 3, a SIOz film 5 is formed on the entire surface, a resist mask 50 is formed, and a P gate 9M region 6 is formed by boron ion implantation 100. do.
次に図（Ｃ）に示すようにレジストマスク５０と５ｔｏ
ｔ）ｌＩ５を除去後に１段目のエビ成長層７ａを形成す
る。このエビ層７ａの比抵抗は０．１〜０゜２Ω・ｃｍ
であり、基Ｆｉ１に比較して低く、その厚さは２μｍ程
変である。Next, as shown in Figure (C), resist masks 50 and 5to
t) After removing lI5, the first shrimp growth layer 7a is formed. The specific resistance of this shrimp layer 7a is 0.1~0゜2Ω・cm
is lower than that of the base Fi1, and its thickness varies by about 2 μm.
次に図（ｄ）に示すように２段目のエビ成長層７ｂを形
成する。その比抵抗は１０〜５０Ω・ｃｍ。Next, as shown in Figure (d), a second shrimp growth layer 7b is formed. Its specific resistance is 10 to 50 Ω·cm.
厚さは約２６μｍ程度である。The thickness is approximately 26 μm.
上記エビ成長層７ａ、７ｂ影形成の熱ドライブ効果によ
り２段目のエビ成長層７ｂ形成終了後にはエビ成長層全
体として、はぼ比抵抗が２段目のエビ成長層７ｂに近い
、−様なエビ層７が形成されることとなる。Due to the thermal drive effect of the shadow formation of the shrimp growth layers 7a and 7b, after the formation of the second shrimp growth layer 7b, the resistivity of the shrimp growth layer as a whole is close to that of the second shrimp growth layer 7b. A shrimp layer 7 will be formed.
次に図（ｅ）に示すように、カソードＮ′９．１域８、
アノードＰ″領域９を順次拡散によって形成し、図げ）
に示すようにシリコン・エッチを行なうことによって段
差部１０を形成し、セグメントを形成すると共にガード
リングＰ″領域４を表面に露出させる。Next, as shown in Figure (e), the cathode N'9.1 area 8,
The anode P'' region 9 is sequentially formed by diffusion (Fig.
As shown in FIG. 3, a step portion 10 is formed by performing a silicon etch to form a segment and expose the guard ring P'' region 4 to the surface.
次に図（粉に示すように段差部１０を熱酸化膜、ＣＶＤ
酸化１１１によって覆い、パッシベーション膜１２を形
成する。Next, as shown in the figure (powder), the stepped portion 10 is coated with thermal oxide film, CVD.
Cover with oxide 111 to form a passivation film 12.
次に図（ハ）に示すようにカソードＡｌ電極１３゜ゲー
トＡｆ電極１４をＡｌＳｉスパッタによって形成するが
、コンタクト抵抗を極力下げるために予め下地にＰｔＳ
ｉを形成してから行ない、その後、パッシベーション膜
１２の強化及び、ゲート電極１４の取り出し部分以外を
保護する目的でプラズマシリコン窒化膜を用いてセグメ
ントパッシベーション膜１５を形成し、図（ｉ）に示す
ように表面電極としてＴｉ蒸気）１！１６．Ｎｉ蒸気膜
１７゜Ａｕ蒸気膜１８を！＠次影形成る。Next, as shown in FIG.
After that, a segment passivation film 15 is formed using a plasma silicon nitride film for the purpose of strengthening the passivation film 12 and protecting the area other than the extraction portion of the gate electrode 14, as shown in FIG. Ti vapor as a surface electrode)1!16. Ni vapor film 17° Au vapor film 18! @ Next shadow is formed.
従来の５ＩＴｈの製造方法は以上のように構成されてい
たので、第２図（Ｃ）で行うエビ成長層の下地はＮ−基
板ｌとガードリングＰ’６．１域４及びゲー トＰ ９
Ｍ域６が混在して表面に露出するものであった。このよ
うな下地の上にエビ成長を行なうと、ゲートやガードリ
ングのＰ゛不純物の高濃度領域からＢ原子が飛び出して
、比抵抗の高いＮ−基板のチャネル領域に拡散する「オ
ートドーピング」現象が起こる。この現象については、
例えば Ｇｕｒｕｍａｋｏｎｄａ Ｒ，５ｒｉｎｉｖａ
ｓａｎ、”Ａ Ｍｏｄｅｌ ｆｏｒ ｔｈｅ Ｌａｔｅ
ｒａｌ Ｖａｒｉａｔｉｏｎ ｏｆ Ａｕｔｏｄｏｐｉ
ｎｇ ｉｎ Ｅｐｉｔａｘｉａｌ ＦｉｌＩＩＩＳ″Ｉ
ＥＥＥ Ｔｒａｎｓａｃｔｉｏｎｓ ｏｎ Ｅｌｅｃｔ
ｒｏｎ Ｄｅｖｔｃｅｓ、ｖ。Since the conventional 5ITh manufacturing method was configured as described above, the base of the shrimp growth layer shown in FIG.
The M region 6 was mixed and exposed on the surface. When growth is performed on such a substrate, an "autodoping" phenomenon occurs in which B atoms jump out from the high concentration region of P impurity in the gate or guard ring and diffuse into the channel region of the N substrate with high resistivity. happens. Regarding this phenomenon,
For example Gurumakonda R,5riniva
san,”A Model for the Late
ral Variation of Autodopi
ng in Epitaxial FilIIIS''I
EEE Transactions on Elect
Ron Devtces, v.
１、ＨＤ−２７，Ｎｏ、８．Ａｕｇ、１９８０ ｐｐ、
１４９３−１４９６等に詳細な解説があるが、５ＩＴｈ
の製造中にこの「オートドーピング」が起これば、第３
図に示すようにＮ−高比抵抗エビ層４０ｂの下にＰ４反
転層４０ａが形成されてしまい、本来の５ＩＴｈとは違
う、ノーマリ−オフ型の素子が製造されてしまう等の問
題があづた。そしてこのような問題を避けるために第２
図（Ｃ）、 （ｄ）のプロセスに示したようにエビ成長
を２段回に分けて行ない、１段回目で高濃度ドーピング
を行うことによりボロンとコンペンセートさせる「カウ
ンタードーピング」法を用いているが、制御性が向上し
たとは言えず、又エビ成長工程を２回に分けて行なうこ
とからその製造工程が繁雑である等の問題があった。1, HD-27, No. 8. August, 1980 pp.
There are detailed explanations in 1493-1496 etc., but 5ITh
If this "autodoping" occurs during the production of
As shown in the figure, a P4 inversion layer 40a is formed under the N-high resistivity layer 40b, leading to problems such as manufacturing a normally-off type device, which is different from the original 5ITh. Ta. And to avoid such problems, the second
As shown in the process in Figures (C) and (d), shrimp growth is carried out in two stages, and a "counter-doping" method is used in which boron is compensated by high concentration doping in the first stage. However, it cannot be said that the controllability has been improved, and there are problems such as the manufacturing process is complicated because the shrimp growth process is carried out in two steps.
この発明は上記のような問題を解消するためになされた
もので、「オートドーピング」現象が発生しないととも
に、制御性がよくかつ製造工程が簡略な５ＩＴｈの製造
方法を捉供することを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a method for manufacturing 5ITh that does not cause the "autodoping" phenomenon, has good controllability, and has a simple manufacturing process. .
この発明に係る静電誘導型半導体装置の製造方法は、第
１導電型の半導体基板の主面にイオンビームを加速注入
して、第２導電型領域層を上記第１導電型の半導体基板
主面に露呈しないように形成し、上記第２導電型領域層
が形成された基板の主面上に、第１導電型のエピタキシ
ャル成長層を形成するようにしたものである。A method for manufacturing a static induction type semiconductor device according to the present invention includes accelerating implantation of an ion beam into the main surface of a semiconductor substrate of a first conductivity type to form a second conductivity type region layer on the main surface of the semiconductor substrate of a first conductivity type. The epitaxial growth layer of the first conductivity type is formed on the main surface of the substrate on which the second conductivity type region layer is formed so as not to be exposed on the surface.
この発明においては、第１導電型の半導体基板の主面に
イオンビームを加速注入して、第２導電型領域層を上記
第１導電型の半導体基板主面に露呈しないように形成し
、上託第２導電型領域層が形成された基板の主面上に、
第１導電型のエピタキシャル成長層を形成するようにし
たので、エビ成長には高濃度の第２導電型領域層がエビ
成長層と接触しないのでオートドーピングが起こらず、
従って反転層の形成によるチャネルの閉鎖等の問題が解
消される。In this invention, an ion beam is acceleratedly implanted into the main surface of the semiconductor substrate of the first conductivity type to form a second conductivity type region layer so as not to be exposed on the main surface of the semiconductor substrate of the first conductivity type. On the main surface of the substrate on which the second conductivity type region layer is formed,
Since the epitaxial growth layer of the first conductivity type is formed, the highly concentrated second conductivity type region layer does not come into contact with the shrimp growth layer, so autodoping does not occur.
Therefore, problems such as channel closure due to the formation of an inversion layer are eliminated.
以下、本発明の一実施例を図について説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例による静電誘導型半導体装置
の製造方法の製造工程図であり、第２図と同一符号は同
一または相当部分を示し、図において、５はイオン注入
時の下敷きＳｉ０ｇ膜、５１はレジスト、１０１はボロ
ンビームであり、その加速エネルギーはＩＭｅＶ以上で
あるため、住人時に形成されたガードリングＰ″領域４
は基板１中に埋め込まれた状態で形成される。FIG. 1 is a manufacturing process diagram of a method for manufacturing an electrostatic induction type semiconductor device according to an embodiment of the present invention, and the same reference numerals as in FIG. 2 indicate the same or corresponding parts. The underlying Si0g film, 51 is a resist, and 101 is a boron beam, whose acceleration energy is more than IMeV, so the guard ring P'' region 4 formed during inhabitation is
is formed embedded in the substrate 1.
次に図（ロ）に示すようにレジスト５２を形成し、高エ
ネルギーボロンビーム１０１を注入しＰゲート領域６を
形成し、その後回（Ｃ）に示すようにＮ−半導体基板１
と同等な比抵抗をもつエビ成長層７ｂを形成する。Next, as shown in Figure (B), a resist 52 is formed, a high energy boron beam 101 is implanted to form a P gate region 6, and then, as shown in Figure (C), a
A shrimp growth layer 7b having a resistivity equivalent to that of the shrimp is formed.
その後の工程は従来と同一であるためここでは省略する
。Since the subsequent steps are the same as those of the conventional method, they will be omitted here.
なお、上記実施例では基板１の片方面にのみゲートを有
する片面ゲートサイリスタを形成したが、第４図に示す
ようにＮ−半導体基板１の一方の主面側に形成されたＰ
−半導体基板２１について各々の基板上に第１上述した
ような工程を加えることによって両面ゲー）Ｓ ＩＴｈ
を製造することも可能であるり、Ｎ゛ガードリング領域
２４．Ｎゲート領域２６．Ｐ”アノード領域２Ｂ、Ｐ−
エビ成長層２７が各々上記片面サイリスタの場合と逆の
導電形で形成されている。In the above embodiment, a single-sided gate thyristor having a gate only on one side of the substrate 1 was formed, but as shown in FIG.
- For semiconductor substrates 21, by adding the first above-mentioned process on each substrate, a double-sided game)S ITh
It is also possible to manufacture N' guard ring region 24. N gate region 26. P” anode area 2B, P-
Each shrimp growth layer 27 is formed with a conductivity type opposite to that of the single-sided thyristor.
尚３０はアノード電極、３１はゲート電極であり、ゲー
ト電極１４とゲート電極３１は、各々第１、第２ゲート
として別々に駆動する。Note that 30 is an anode electrode, 31 is a gate electrode, and the gate electrode 14 and the gate electrode 31 are driven separately as first and second gates, respectively.
［発明の効果〕
以上のように、本発明に係る静電誘導型半導体装置の製
造方法によれば、埋込みゲートを有する静電誘導型半導
体装置の製造において、基板にイオン注入してゲート領
域を形成する工程において、基板表面にゲー） ＄５域
が露呈しないような加速エネルギーでもってイオン注入
を行なうようにしたので、オートドーピングが起こらず
、従って反転層の形成によるチャネルの閉鎖等の恐れが
なく製造時の制御性が向上するという効果がある。[Effects of the Invention] As described above, according to the method for manufacturing a static induction type semiconductor device according to the present invention, in manufacturing a static induction type semiconductor device having a buried gate, ions are implanted into a substrate to form a gate region. In the formation process, ions were implanted with an acceleration energy that would not expose the Ga $5 region on the substrate surface, so autodoping would not occur and there would be no risk of channel closure due to the formation of an inversion layer. This has the effect of improving controllability during manufacturing.
第１′はこの発明の一実施例による静電誘導型半導体装
置の製造方法を示す断面図、第２図は従来の静電誘導型
半導体装置の製造方法を示す断面図、第３図はエビ成長
時にオートドーピング現象が発生した状態を説明するた
めの断面図、第４図はこの発明の応用例で、両面ゲート
静電誘導型半導体装置の構造を示す断面図である。
１はＮ−半導体基板、４はＰ°ガードリング領域、６は
Ｐゲート領域、７はエビ成長層、１０１はボロンビーム
である。
なお、各図中同一符号は同一または、相当部分を示す。1' is a cross-sectional view showing a method for manufacturing a static induction semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a conventional method for manufacturing a static induction semiconductor device, and FIG. FIG. 4 is a cross-sectional view for explaining a state in which an auto-doping phenomenon occurs during growth, and FIG. 4 is a cross-sectional view showing the structure of a double-sided gate electrostatic induction type semiconductor device, which is an application example of the present invention. 1 is an N-semiconductor substrate, 4 is a P° guard ring region, 6 is a P gate region, 7 is a shrimp growth layer, and 101 is a boron beam. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
の製造方法において、 第１導電型の半導体基板の主面にイオンビームを加速注
入して、第２導電型領域層を上記第１導電型の半導体基
板主面に露呈しないように形成する工程と、 上記第２導電型領域層が形成された基板の主面上に、第
１導電型のエピタキシャル成長層を形成する工程とを含
むことを特徴とする静電誘導型半導体装置の製造方法。(1) In a method for manufacturing a static induction type semiconductor device having a buried gate electrode, an ion beam is acceleratedly implanted into the main surface of a semiconductor substrate of a first conductivity type to form a second conductivity type region layer of the first conductivity type. and forming an epitaxial growth layer of the first conductivity type on the main surface of the substrate on which the second conductivity type region layer is formed. A method for manufacturing a static induction type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19353190A JPH04192362A (en) | 1990-07-20 | 1990-07-20 | Manufacture of electrostatic induction semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19353190A JPH04192362A (en) | 1990-07-20 | 1990-07-20 | Manufacture of electrostatic induction semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04192362A true JPH04192362A (en) | 1992-07-10 |
Family
ID=16309625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19353190A Pending JPH04192362A (en) | 1990-07-20 | 1990-07-20 | Manufacture of electrostatic induction semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04192362A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007258591A (en) * | 2006-03-24 | 2007-10-04 | Ngk Insulators Ltd | Electrostatic inductive thyristor with current control layer and protect circuit/pulse generating circuit of electrostatic inductive thyristor with current control layer |
-
1990
- 1990-07-20 JP JP19353190A patent/JPH04192362A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007258591A (en) * | 2006-03-24 | 2007-10-04 | Ngk Insulators Ltd | Electrostatic inductive thyristor with current control layer and protect circuit/pulse generating circuit of electrostatic inductive thyristor with current control layer |
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