JPH04191946A - スヌープキャッシュメモリ制御方式 - Google Patents

スヌープキャッシュメモリ制御方式

Info

Publication number
JPH04191946A
JPH04191946A JP2320914A JP32091490A JPH04191946A JP H04191946 A JPH04191946 A JP H04191946A JP 2320914 A JP2320914 A JP 2320914A JP 32091490 A JP32091490 A JP 32091490A JP H04191946 A JPH04191946 A JP H04191946A
Authority
JP
Japan
Prior art keywords
block
shared
cache memory
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2320914A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0532776B2 (fr
Inventor
Masaki Sato
正樹 佐藤
Akira Yamamoto
明 山本
Teruhiko Ohara
輝彦 大原
Koichi Takeda
浩一 武田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP2320914A priority Critical patent/JPH04191946A/ja
Publication of JPH04191946A publication Critical patent/JPH04191946A/ja
Publication of JPH0532776B2 publication Critical patent/JPH0532776B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP2320914A 1990-11-27 1990-11-27 スヌープキャッシュメモリ制御方式 Granted JPH04191946A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2320914A JPH04191946A (ja) 1990-11-27 1990-11-27 スヌープキャッシュメモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2320914A JPH04191946A (ja) 1990-11-27 1990-11-27 スヌープキャッシュメモリ制御方式

Publications (2)

Publication Number Publication Date
JPH04191946A true JPH04191946A (ja) 1992-07-10
JPH0532776B2 JPH0532776B2 (fr) 1993-05-17

Family

ID=18126682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2320914A Granted JPH04191946A (ja) 1990-11-27 1990-11-27 スヌープキャッシュメモリ制御方式

Country Status (1)

Country Link
JP (1) JPH04191946A (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0784877A (ja) * 1993-08-27 1995-03-31 Internatl Business Mach Corp <Ibm> マルチプロセッサ・システムにおけるコヒーレンシィ制御装置及び維持方法
JPH07152646A (ja) * 1993-07-15 1995-06-16 Bull Sa 記憶階層レベル間での交換のコヒーレンシー管理方法
US5923898A (en) * 1997-05-14 1999-07-13 International Business Machines Corporation System for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not matched
JPH11508375A (ja) * 1995-06-26 1999-07-21 ラプラント、パトリック、アール． 流体圧による引っ張り及び同調システム
US6240491B1 (en) 1993-07-15 2001-05-29 Bull S.A. Process and system for switching between an update and invalidate mode for each cache block
JP2009122787A (ja) * 2007-11-13 2009-06-04 Nec Computertechno Ltd マルチプロセッサシステム
US8489862B2 (en) 2007-06-12 2013-07-16 Panasonic Corporation Multiprocessor control apparatus for controlling a plurality of processors sharing a memory and an internal bus and multiprocessor control method and multiprocessor control circuit for performing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07152646A (ja) * 1993-07-15 1995-06-16 Bull Sa 記憶階層レベル間での交換のコヒーレンシー管理方法
US6240491B1 (en) 1993-07-15 2001-05-29 Bull S.A. Process and system for switching between an update and invalidate mode for each cache block
JPH0784877A (ja) * 1993-08-27 1995-03-31 Internatl Business Mach Corp <Ibm> マルチプロセッサ・システムにおけるコヒーレンシィ制御装置及び維持方法
JPH11508375A (ja) * 1995-06-26 1999-07-21 ラプラント、パトリック、アール． 流体圧による引っ張り及び同調システム
US5923898A (en) * 1997-05-14 1999-07-13 International Business Machines Corporation System for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not matched
US8489862B2 (en) 2007-06-12 2013-07-16 Panasonic Corporation Multiprocessor control apparatus for controlling a plurality of processors sharing a memory and an internal bus and multiprocessor control method and multiprocessor control circuit for performing the same
JP2009122787A (ja) * 2007-11-13 2009-06-04 Nec Computertechno Ltd マルチプロセッサシステム

Also Published As

Publication number Publication date
JPH0532776B2 (fr) 1993-05-17

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term