JPH0419024U - - Google Patents

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Publication number
JPH0419024U
JPH0419024U JP6053790U JP6053790U JPH0419024U JP H0419024 U JPH0419024 U JP H0419024U JP 6053790 U JP6053790 U JP 6053790U JP 6053790 U JP6053790 U JP 6053790U JP H0419024 U JPH0419024 U JP H0419024U
Authority
JP
Japan
Prior art keywords
resistor
transistor
collector
npn transistor
npn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6053790U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6053790U priority Critical patent/JPH0419024U/ja
Publication of JPH0419024U publication Critical patent/JPH0419024U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bはそれぞれ本考案の大出力マルチ
バイブレータの第1実施例による回路構成図とタ
イムチヤート、第2図a,bはそれぞれ本考案の
大出力用マルチバイブレータの第2実施例による
回路構成図とタイムチヤート、第3図a,bはそ
れぞれ従来の双安定マルチバイブレータの回路構
成図とタイムチヤート、第4図a,bはそれぞれ
従来の単安定マルチバイブレータの回路構成図と
タイムチヤートである。 Q1……PNPトランジスタ、Q2……NPN
トランジスタ、C1……コンデンサ、D1……ダ
イオード、R1,R2,R3,R4,R5,R6
……抵抗、SW,SW1,SW2……スイツチ。
Figures 1a and b are the circuit configuration diagram and time chart of the first embodiment of the high-output multivibrator of the present invention, and Figures 2a and b are respectively the second embodiment of the high-output multivibrator of the present invention. Circuit configuration diagram and time chart, Figures 3a and b are the circuit configuration diagram and time chart of a conventional bistable multivibrator, respectively, and Figures 4a and b are the circuit configuration diagram and time chart of a conventional monostable multivibrator, respectively. It is. Q1...PNP transistor, Q2...NPN
Transistor, C1... Capacitor, D1... Diode, R1, R2, R3, R4, R5, R6
...Resistance, SW, SW1, SW2...Switch.

Claims (1)

【実用新案登録請求の範囲】 (1) PNPトランジスタとNPNトランジスタ
を用い、PNPトランジスタのエミツタを電源ラ
インに、コレクタを出力ラインにそれぞれ接続し
、ベースを抵抗を介してNPNトランジスタのコ
レクタに接続し、前記PNPトランジスタのコレ
クタとNPNトランジスタのベースとの間に帰還
用のダイオードと抵抗の直列路を接続し、電源ラ
インとNPNトランジスタのコレクタの間に抵抗
を接続し、電源ラインと接地間に抵抗と2つの出
力切替用のスイツチの直列路を接続し、これらス
イツチの接続中点をNPNトランジスタのベース
に接続すると共に抵抗を介して接地し、かつ、N
PNトランジスタのエミツタを接地したことを特
徴とする大出力用マルチバイブレータ。 (2) PNPトランジスタとNPNトランジスタ
を用い、PNPトランジスタのエミツタを電源ラ
インに、コレクタを出力ラインにそれぞれ接続し
、ベースを抵抗を介してNPNトランジスタのコ
レクタに接続し、前記PNPトランジスタのコレ
クタとNPNトランジスタのベースとの間に帰還
用のダイオードとコンデンサと抵抗の直列路を接
続し、電源ラインとNPNトランジスタのコレク
タの間に抵抗を接続し、電源ラインとNPNトラ
ンジスタのベース間に抵抗とトリガー用スイツチ
の直列路を接続すると共に抵抗を介して接地し、
かつ、NPNトランジスタのエミツタを接地した
ことを特徴とする大出力用マルチバイブレータ。
[Claims for Utility Model Registration] (1) A PNP transistor and an NPN transistor are used, the emitter of the PNP transistor is connected to the power supply line, the collector is connected to the output line, and the base is connected to the collector of the NPN transistor through a resistor. , a series path of a feedback diode and a resistor is connected between the collector of the PNP transistor and the base of the NPN transistor, a resistor is connected between the power supply line and the collector of the NPN transistor, and a resistor is connected between the power supply line and ground. and two output switching switches are connected in series, and the midpoint of these switches is connected to the base of the NPN transistor and grounded via a resistor, and the NPN
A high output multivibrator characterized by a grounded emitter of a PN transistor. (2) Using a PNP transistor and an NPN transistor, the emitter of the PNP transistor is connected to the power supply line, the collector is connected to the output line, the base is connected to the collector of the NPN transistor via a resistor, and the collector of the PNP transistor and the NPN Connect a feedback diode, capacitor, and resistor in series between the base of the transistor, connect a resistor between the power line and the collector of the NPN transistor, and connect a resistor and trigger between the power line and the base of the NPN transistor. Connect the series circuit of the switch and ground it through a resistor.
A large output multivibrator characterized in that the emitter of the NPN transistor is grounded.
JP6053790U 1990-06-07 1990-06-07 Pending JPH0419024U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6053790U JPH0419024U (en) 1990-06-07 1990-06-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6053790U JPH0419024U (en) 1990-06-07 1990-06-07

Publications (1)

Publication Number Publication Date
JPH0419024U true JPH0419024U (en) 1992-02-18

Family

ID=31587985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6053790U Pending JPH0419024U (en) 1990-06-07 1990-06-07

Country Status (1)

Country Link
JP (1) JPH0419024U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850529B2 (en) * 1980-06-11 1983-11-11 有限会社 ニシオカ emulsifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850529B2 (en) * 1980-06-11 1983-11-11 有限会社 ニシオカ emulsifier

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