JPH03101042U - - Google Patents
Info
- Publication number
- JPH03101042U JPH03101042U JP1027190U JP1027190U JPH03101042U JP H03101042 U JPH03101042 U JP H03101042U JP 1027190 U JP1027190 U JP 1027190U JP 1027190 U JP1027190 U JP 1027190U JP H03101042 U JPH03101042 U JP H03101042U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- whose
- transistor
- collector
- collector terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例を示す回路構成図、
第２図は他の実施例を示す回路構成図、第３図は
従来例を示す回路構成図、第４図はヒシテリシス
付電流コンパレータの動作を示す図である。
Ｑ１〜Ｑ７，Ｑ１０，Ｑ２０，Ｑ２５……トラ
ンジスタ、Ｒ１〜Ｒ５，ＲＡ……抵抗、Ｄ１……
ダイオード。
FIG. 1 is a circuit diagram showing an embodiment of the present invention;
FIG. 2 is a circuit diagram showing another embodiment, FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 is a diagram showing the operation of a current comparator with hysteresis. Q1 to Q7 , Q10 , Q20 , Q25 ...Transistor, R1 to R5 , RA...Resistor, D1 ...
diode.
Claims (1)
とベースが接続された第１のトランジスタＱ１と
、前記Ｑ１のベース端子にベースが接続されエミ
ツタ端子がグランドに接続された第２のトランジ
スタＱ２と、前記Ｑ２のコレクタ端子にベース端
子が接続され、エミツタ端子がグランドに接続さ
れた第３のトランジスタＱ３と、ベース端子が前
記Ｑ３のコレクタ端子と抵抗を介して接続されエ
ミツタ端子がグランドに接続された第４のトラン
ジスタＱ４と、ベース同士が接続されエミツタ端
子が電源Ｖｃｃに接続された３個のトランジスタ
Ｑ５〜Ｑ７のコレクタ端子のそれぞれ前記Ｑ２〜
Ｑ４のコレクタ端子に接続されるとともに前記Ｑ
２のコレクタ端子にカソードが前記Ｑ４のコレク
タ端子にアノードが接続されたダイオードを備え
、前記Ｑ１のコレクタに信号を入力し、前記第３
のトランジスタＱ３のコレクタ端子側から出力を
取出す様に構成したことを特徴とするヒシテリシ
ス付電流コンパレータ。 a first transistor Q1 whose emitter is connected to ground and whose collector terminal and base are connected; a second transistor Q2 whose base is connected to the base terminal of Q1 and whose emitter terminal is connected to ground; A third transistor Q3 has a base terminal connected to the collector terminal of Q2 and an emitter terminal connected to ground, and a third transistor Q3 whose base terminal is connected to the collector terminal of Q3 via a resistor and whose emitter terminal is connected to ground. A fourth transistor Q4 is connected to the collector terminals of three transistors Q5 to Q7 whose bases are connected to each other and whose emitter terminals are connected to the power supply Vcc, respectively .
It is connected to the collector terminal of Q4 and the Q4 is connected to the collector terminal of Q4.
A diode is provided, the cathode of which is connected to the collector terminal of Q2 , the anode of which is connected to the collector terminal of Q4 , and a signal is input to the collector of Q1 .
A current comparator with hysteresis characterized in that the output is taken out from the collector terminal side of the transistor Q3 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027190U JPH03101042U (en) | 1990-02-05 | 1990-02-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027190U JPH03101042U (en) | 1990-02-05 | 1990-02-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03101042U true JPH03101042U (en) | 1991-10-22 |
Family
ID=31513850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1027190U Pending JPH03101042U (en) | 1990-02-05 | 1990-02-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03101042U (en) |
-
1990
- 1990-02-05 JP JP1027190U patent/JPH03101042U/ja active Pending